2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
27 #include "radeon_drm_cs.h"
29 #include "util/u_hash_table.h"
30 #include "util/u_memory.h"
31 #include "util/simple_list.h"
32 #include "util/u_double_list.h"
33 #include "os/os_thread.h"
34 #include "os/os_mman.h"
35 #include "os/os_time.h"
37 #include "state_tracker/drm_driver.h"
39 #include <sys/ioctl.h>
45 extern const struct pb_vtbl radeon_bo_vtbl
;
47 static INLINE
struct radeon_bo
*radeon_bo(struct pb_buffer
*bo
)
49 assert(bo
->vtbl
== &radeon_bo_vtbl
);
50 return (struct radeon_bo
*)bo
;
53 struct radeon_bo_va_hole
{
54 struct list_head list
;
61 struct pb_manager base
;
64 struct radeon_drm_winsys
*rws
;
66 /* List of buffer GEM names. Protected by bo_handles_mutex. */
67 struct util_hash_table
*bo_names
;
68 /* List of buffer handles. Protectded by bo_handles_mutex. */
69 struct util_hash_table
*bo_handles
;
70 /* List of buffer virtual memory ranges. Protectded by bo_handles_mutex. */
71 struct util_hash_table
*bo_vas
;
72 pipe_mutex bo_handles_mutex
;
73 pipe_mutex bo_va_mutex
;
75 /* is virtual address supported */
78 struct list_head va_holes
;
81 static INLINE
struct radeon_bomgr
*radeon_bomgr(struct pb_manager
*mgr
)
83 return (struct radeon_bomgr
*)mgr
;
86 static struct radeon_bo
*get_radeon_bo(struct pb_buffer
*_buf
)
88 struct radeon_bo
*bo
= NULL
;
90 if (_buf
->vtbl
== &radeon_bo_vtbl
) {
93 struct pb_buffer
*base_buf
;
95 pb_get_base_buffer(_buf
, &base_buf
, &offset
);
97 if (base_buf
->vtbl
== &radeon_bo_vtbl
)
98 bo
= radeon_bo(base_buf
);
104 static void radeon_bo_wait(struct pb_buffer
*_buf
, enum radeon_bo_usage usage
)
106 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
107 struct drm_radeon_gem_wait_idle args
= {0};
109 while (p_atomic_read(&bo
->num_active_ioctls
)) {
113 args
.handle
= bo
->handle
;
114 while (drmCommandWrite(bo
->rws
->fd
, DRM_RADEON_GEM_WAIT_IDLE
,
115 &args
, sizeof(args
)) == -EBUSY
);
118 static boolean
radeon_bo_is_busy(struct pb_buffer
*_buf
,
119 enum radeon_bo_usage usage
)
121 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
122 struct drm_radeon_gem_busy args
= {0};
124 if (p_atomic_read(&bo
->num_active_ioctls
)) {
128 args
.handle
= bo
->handle
;
129 return drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_BUSY
,
130 &args
, sizeof(args
)) != 0;
133 static enum radeon_bo_domain
get_valid_domain(enum radeon_bo_domain domain
)
135 /* Zero domains the driver doesn't understand. */
136 domain
&= RADEON_DOMAIN_VRAM_GTT
;
138 /* If no domain is set, we must set something... */
140 domain
= RADEON_DOMAIN_VRAM_GTT
;
145 static enum radeon_bo_domain
radeon_bo_get_initial_domain(
146 struct radeon_winsys_cs_handle
*buf
)
148 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
149 struct drm_radeon_gem_op args
;
151 if (bo
->rws
->info
.drm_minor
< 38)
152 return RADEON_DOMAIN_VRAM_GTT
;
154 memset(&args
, 0, sizeof(args
));
155 args
.handle
= bo
->handle
;
156 args
.op
= RADEON_GEM_OP_GET_INITIAL_DOMAIN
;
158 drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_OP
,
159 &args
, sizeof(args
));
161 /* GEM domains and winsys domains are defined the same. */
162 return get_valid_domain(args
.value
);
165 static uint64_t radeon_bomgr_find_va(struct radeon_bomgr
*mgr
, uint64_t size
, uint64_t alignment
)
167 struct radeon_bo_va_hole
*hole
, *n
;
168 uint64_t offset
= 0, waste
= 0;
170 alignment
= MAX2(alignment
, 4096);
171 size
= align(size
, 4096);
173 pipe_mutex_lock(mgr
->bo_va_mutex
);
174 /* first look for a hole */
175 LIST_FOR_EACH_ENTRY_SAFE(hole
, n
, &mgr
->va_holes
, list
) {
176 offset
= hole
->offset
;
177 waste
= offset
% alignment
;
178 waste
= waste
? alignment
- waste
: 0;
180 if (offset
>= (hole
->offset
+ hole
->size
)) {
183 if (!waste
&& hole
->size
== size
) {
184 offset
= hole
->offset
;
185 list_del(&hole
->list
);
187 pipe_mutex_unlock(mgr
->bo_va_mutex
);
190 if ((hole
->size
- waste
) > size
) {
192 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
194 n
->offset
= hole
->offset
;
195 list_add(&n
->list
, &hole
->list
);
197 hole
->size
-= (size
+ waste
);
198 hole
->offset
+= size
+ waste
;
199 pipe_mutex_unlock(mgr
->bo_va_mutex
);
202 if ((hole
->size
- waste
) == size
) {
204 pipe_mutex_unlock(mgr
->bo_va_mutex
);
209 offset
= mgr
->va_offset
;
210 waste
= offset
% alignment
;
211 waste
= waste
? alignment
- waste
: 0;
213 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
216 list_add(&n
->list
, &mgr
->va_holes
);
219 mgr
->va_offset
+= size
+ waste
;
220 pipe_mutex_unlock(mgr
->bo_va_mutex
);
224 static void radeon_bomgr_free_va(struct radeon_bomgr
*mgr
, uint64_t va
, uint64_t size
)
226 struct radeon_bo_va_hole
*hole
;
228 size
= align(size
, 4096);
230 pipe_mutex_lock(mgr
->bo_va_mutex
);
231 if ((va
+ size
) == mgr
->va_offset
) {
233 /* Delete uppermost hole if it reaches the new top */
234 if (!LIST_IS_EMPTY(&mgr
->va_holes
)) {
235 hole
= container_of(mgr
->va_holes
.next
, hole
, list
);
236 if ((hole
->offset
+ hole
->size
) == va
) {
237 mgr
->va_offset
= hole
->offset
;
238 list_del(&hole
->list
);
243 struct radeon_bo_va_hole
*next
;
245 hole
= container_of(&mgr
->va_holes
, hole
, list
);
246 LIST_FOR_EACH_ENTRY(next
, &mgr
->va_holes
, list
) {
247 if (next
->offset
< va
)
252 if (&hole
->list
!= &mgr
->va_holes
) {
253 /* Grow upper hole if it's adjacent */
254 if (hole
->offset
== (va
+ size
)) {
257 /* Merge lower hole if it's adjacent */
258 if (next
!= hole
&& &next
->list
!= &mgr
->va_holes
&&
259 (next
->offset
+ next
->size
) == va
) {
260 next
->size
+= hole
->size
;
261 list_del(&hole
->list
);
268 /* Grow lower hole if it's adjacent */
269 if (next
!= hole
&& &next
->list
!= &mgr
->va_holes
&&
270 (next
->offset
+ next
->size
) == va
) {
275 /* FIXME on allocation failure we just lose virtual address space
276 * maybe print a warning
278 next
= CALLOC_STRUCT(radeon_bo_va_hole
);
282 list_add(&next
->list
, &hole
->list
);
286 pipe_mutex_unlock(mgr
->bo_va_mutex
);
289 static void radeon_bo_destroy(struct pb_buffer
*_buf
)
291 struct radeon_bo
*bo
= radeon_bo(_buf
);
292 struct radeon_bomgr
*mgr
= bo
->mgr
;
293 struct drm_gem_close args
;
295 memset(&args
, 0, sizeof(args
));
297 pipe_mutex_lock(bo
->mgr
->bo_handles_mutex
);
298 util_hash_table_remove(bo
->mgr
->bo_handles
, (void*)(uintptr_t)bo
->handle
);
299 if (bo
->flink_name
) {
300 util_hash_table_remove(bo
->mgr
->bo_names
,
301 (void*)(uintptr_t)bo
->flink_name
);
303 pipe_mutex_unlock(bo
->mgr
->bo_handles_mutex
);
306 os_munmap(bo
->ptr
, bo
->base
.size
);
309 args
.handle
= bo
->handle
;
310 drmIoctl(bo
->rws
->fd
, DRM_IOCTL_GEM_CLOSE
, &args
);
313 radeon_bomgr_free_va(mgr
, bo
->va
, bo
->base
.size
);
316 pipe_mutex_destroy(bo
->map_mutex
);
318 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
319 bo
->rws
->allocated_vram
-= align(bo
->base
.size
, 4096);
320 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
321 bo
->rws
->allocated_gtt
-= align(bo
->base
.size
, 4096);
325 void *radeon_bo_do_map(struct radeon_bo
*bo
)
327 struct drm_radeon_gem_mmap args
= {0};
330 /* If the buffer is created from user memory, return the user pointer. */
334 /* Return the pointer if it's already mapped. */
338 /* Map the buffer. */
339 pipe_mutex_lock(bo
->map_mutex
);
340 /* Return the pointer if it's already mapped (in case of a race). */
342 pipe_mutex_unlock(bo
->map_mutex
);
345 args
.handle
= bo
->handle
;
347 args
.size
= (uint64_t)bo
->base
.size
;
348 if (drmCommandWriteRead(bo
->rws
->fd
,
352 pipe_mutex_unlock(bo
->map_mutex
);
353 fprintf(stderr
, "radeon: gem_mmap failed: %p 0x%08X\n",
358 ptr
= os_mmap(0, args
.size
, PROT_READ
|PROT_WRITE
, MAP_SHARED
,
359 bo
->rws
->fd
, args
.addr_ptr
);
360 if (ptr
== MAP_FAILED
) {
361 pipe_mutex_unlock(bo
->map_mutex
);
362 fprintf(stderr
, "radeon: mmap failed, errno: %i\n", errno
);
366 pipe_mutex_unlock(bo
->map_mutex
);
371 static void *radeon_bo_map(struct radeon_winsys_cs_handle
*buf
,
372 struct radeon_winsys_cs
*rcs
,
373 enum pipe_transfer_usage usage
)
375 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
376 struct radeon_drm_cs
*cs
= (struct radeon_drm_cs
*)rcs
;
378 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
379 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
380 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
381 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
382 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
385 * Since we are mapping for read, we don't need to wait
386 * if the GPU is using the buffer for read too
387 * (neither one is changing it).
389 * Only check whether the buffer is being used for write. */
390 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
391 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
395 if (radeon_bo_is_busy((struct pb_buffer
*)bo
,
396 RADEON_USAGE_WRITE
)) {
400 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
401 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
405 if (radeon_bo_is_busy((struct pb_buffer
*)bo
,
406 RADEON_USAGE_READWRITE
)) {
411 uint64_t time
= os_time_get_nano();
413 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
416 * Since we are mapping for read, we don't need to wait
417 * if the GPU is using the buffer for read too
418 * (neither one is changing it).
420 * Only check whether the buffer is being used for write. */
421 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
422 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
424 radeon_bo_wait((struct pb_buffer
*)bo
,
427 /* Mapping for write. */
429 if (radeon_bo_is_referenced_by_cs(cs
, bo
)) {
430 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
432 /* Try to avoid busy-waiting in radeon_bo_wait. */
433 if (p_atomic_read(&bo
->num_active_ioctls
))
434 radeon_drm_cs_sync_flush(rcs
);
438 radeon_bo_wait((struct pb_buffer
*)bo
, RADEON_USAGE_READWRITE
);
441 bo
->mgr
->rws
->buffer_wait_time
+= os_time_get_nano() - time
;
445 return radeon_bo_do_map(bo
);
448 static void radeon_bo_unmap(struct radeon_winsys_cs_handle
*_buf
)
453 static void radeon_bo_get_base_buffer(struct pb_buffer
*buf
,
454 struct pb_buffer
**base_buf
,
461 static enum pipe_error
radeon_bo_validate(struct pb_buffer
*_buf
,
462 struct pb_validate
*vl
,
469 static void radeon_bo_fence(struct pb_buffer
*buf
,
470 struct pipe_fence_handle
*fence
)
474 const struct pb_vtbl radeon_bo_vtbl
= {
476 NULL
, /* never called */
477 NULL
, /* never called */
480 radeon_bo_get_base_buffer
,
483 #ifndef RADEON_GEM_GTT_WC
484 #define RADEON_GEM_GTT_WC (1 << 2)
486 #ifndef RADEON_GEM_CPU_ACCESS
487 /* BO is expected to be accessed by the CPU */
488 #define RADEON_GEM_CPU_ACCESS (1 << 3)
490 #ifndef RADEON_GEM_NO_CPU_ACCESS
491 /* CPU access is not expected to work for this BO */
492 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
495 static struct pb_buffer
*radeon_bomgr_create_bo(struct pb_manager
*_mgr
,
497 const struct pb_desc
*desc
)
499 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
500 struct radeon_drm_winsys
*rws
= mgr
->rws
;
501 struct radeon_bo
*bo
;
502 struct drm_radeon_gem_create args
;
503 struct radeon_bo_desc
*rdesc
= (struct radeon_bo_desc
*)desc
;
506 memset(&args
, 0, sizeof(args
));
508 assert(rdesc
->initial_domains
);
509 assert((rdesc
->initial_domains
&
510 ~(RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
)) == 0);
513 args
.alignment
= desc
->alignment
;
514 args
.initial_domain
= rdesc
->initial_domains
;
517 if (rdesc
->flags
& RADEON_FLAG_GTT_WC
)
518 args
.flags
|= RADEON_GEM_GTT_WC
;
519 if (rdesc
->flags
& RADEON_FLAG_CPU_ACCESS
)
520 args
.flags
|= RADEON_GEM_CPU_ACCESS
;
521 if (rdesc
->flags
& RADEON_FLAG_NO_CPU_ACCESS
)
522 args
.flags
|= RADEON_GEM_NO_CPU_ACCESS
;
524 if (drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_CREATE
,
525 &args
, sizeof(args
))) {
526 fprintf(stderr
, "radeon: Failed to allocate a buffer:\n");
527 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
528 fprintf(stderr
, "radeon: alignment : %d bytes\n", desc
->alignment
);
529 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
530 fprintf(stderr
, "radeon: flags : %d\n", args
.flags
);
534 bo
= CALLOC_STRUCT(radeon_bo
);
538 pipe_reference_init(&bo
->base
.reference
, 1);
539 bo
->base
.alignment
= desc
->alignment
;
540 bo
->base
.usage
= desc
->usage
;
541 bo
->base
.size
= size
;
542 bo
->base
.vtbl
= &radeon_bo_vtbl
;
545 bo
->handle
= args
.handle
;
547 bo
->initial_domain
= rdesc
->initial_domains
;
548 pipe_mutex_init(bo
->map_mutex
);
551 struct drm_radeon_gem_va va
;
553 bo
->va
= radeon_bomgr_find_va(mgr
, size
, desc
->alignment
);
555 va
.handle
= bo
->handle
;
557 va
.operation
= RADEON_VA_MAP
;
558 va
.flags
= RADEON_VM_PAGE_READABLE
|
559 RADEON_VM_PAGE_WRITEABLE
|
560 RADEON_VM_PAGE_SNOOPED
;
562 r
= drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
563 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
564 fprintf(stderr
, "radeon: Failed to allocate virtual address for buffer:\n");
565 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
566 fprintf(stderr
, "radeon: alignment : %d bytes\n", desc
->alignment
);
567 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
568 fprintf(stderr
, "radeon: va : 0x%016llx\n", (unsigned long long)bo
->va
);
569 radeon_bo_destroy(&bo
->base
);
572 pipe_mutex_lock(mgr
->bo_handles_mutex
);
573 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
574 struct pb_buffer
*b
= &bo
->base
;
575 struct radeon_bo
*old_bo
=
576 util_hash_table_get(mgr
->bo_vas
, (void*)(uintptr_t)va
.offset
);
578 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
579 pb_reference(&b
, &old_bo
->base
);
583 util_hash_table_set(mgr
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
584 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
587 if (rdesc
->initial_domains
& RADEON_DOMAIN_VRAM
)
588 rws
->allocated_vram
+= align(size
, 4096);
589 else if (rdesc
->initial_domains
& RADEON_DOMAIN_GTT
)
590 rws
->allocated_gtt
+= align(size
, 4096);
595 static void radeon_bomgr_flush(struct pb_manager
*mgr
)
600 /* This is for the cache bufmgr. */
601 static boolean
radeon_bomgr_is_buffer_busy(struct pb_manager
*_mgr
,
602 struct pb_buffer
*_buf
)
604 struct radeon_bo
*bo
= radeon_bo(_buf
);
606 if (radeon_bo_is_referenced_by_any_cs(bo
)) {
610 if (radeon_bo_is_busy((struct pb_buffer
*)bo
, RADEON_USAGE_READWRITE
)) {
617 static void radeon_bomgr_destroy(struct pb_manager
*_mgr
)
619 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
620 util_hash_table_destroy(mgr
->bo_names
);
621 util_hash_table_destroy(mgr
->bo_handles
);
622 util_hash_table_destroy(mgr
->bo_vas
);
623 pipe_mutex_destroy(mgr
->bo_handles_mutex
);
624 pipe_mutex_destroy(mgr
->bo_va_mutex
);
628 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
630 static unsigned handle_hash(void *key
)
632 return PTR_TO_UINT(key
);
635 static int handle_compare(void *key1
, void *key2
)
637 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
640 struct pb_manager
*radeon_bomgr_create(struct radeon_drm_winsys
*rws
)
642 struct radeon_bomgr
*mgr
;
644 mgr
= CALLOC_STRUCT(radeon_bomgr
);
648 mgr
->base
.destroy
= radeon_bomgr_destroy
;
649 mgr
->base
.create_buffer
= radeon_bomgr_create_bo
;
650 mgr
->base
.flush
= radeon_bomgr_flush
;
651 mgr
->base
.is_buffer_busy
= radeon_bomgr_is_buffer_busy
;
654 mgr
->bo_names
= util_hash_table_create(handle_hash
, handle_compare
);
655 mgr
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
656 mgr
->bo_vas
= util_hash_table_create(handle_hash
, handle_compare
);
657 pipe_mutex_init(mgr
->bo_handles_mutex
);
658 pipe_mutex_init(mgr
->bo_va_mutex
);
660 mgr
->va
= rws
->info
.r600_virtual_address
;
661 mgr
->va_offset
= rws
->va_start
;
662 list_inithead(&mgr
->va_holes
);
667 static unsigned eg_tile_split(unsigned tile_split
)
669 switch (tile_split
) {
670 case 0: tile_split
= 64; break;
671 case 1: tile_split
= 128; break;
672 case 2: tile_split
= 256; break;
673 case 3: tile_split
= 512; break;
675 case 4: tile_split
= 1024; break;
676 case 5: tile_split
= 2048; break;
677 case 6: tile_split
= 4096; break;
682 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
684 switch (eg_tile_split
) {
696 static void radeon_bo_get_tiling(struct pb_buffer
*_buf
,
697 enum radeon_bo_layout
*microtiled
,
698 enum radeon_bo_layout
*macrotiled
,
699 unsigned *bankw
, unsigned *bankh
,
700 unsigned *tile_split
,
701 unsigned *stencil_tile_split
,
705 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
706 struct drm_radeon_gem_set_tiling args
;
708 memset(&args
, 0, sizeof(args
));
710 args
.handle
= bo
->handle
;
712 drmCommandWriteRead(bo
->rws
->fd
,
713 DRM_RADEON_GEM_GET_TILING
,
717 *microtiled
= RADEON_LAYOUT_LINEAR
;
718 *macrotiled
= RADEON_LAYOUT_LINEAR
;
719 if (args
.tiling_flags
& RADEON_TILING_MICRO
)
720 *microtiled
= RADEON_LAYOUT_TILED
;
721 else if (args
.tiling_flags
& RADEON_TILING_MICRO_SQUARE
)
722 *microtiled
= RADEON_LAYOUT_SQUARETILED
;
724 if (args
.tiling_flags
& RADEON_TILING_MACRO
)
725 *macrotiled
= RADEON_LAYOUT_TILED
;
726 if (bankw
&& tile_split
&& stencil_tile_split
&& mtilea
&& tile_split
) {
727 *bankw
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
728 *bankh
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
729 *tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
730 *stencil_tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
;
731 *mtilea
= (args
.tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
732 *tile_split
= eg_tile_split(*tile_split
);
735 *scanout
= bo
->rws
->gen
>= DRV_SI
&& !(args
.tiling_flags
& RADEON_TILING_R600_NO_SCANOUT
);
738 static void radeon_bo_set_tiling(struct pb_buffer
*_buf
,
739 struct radeon_winsys_cs
*rcs
,
740 enum radeon_bo_layout microtiled
,
741 enum radeon_bo_layout macrotiled
,
742 unsigned bankw
, unsigned bankh
,
744 unsigned stencil_tile_split
,
749 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
750 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
751 struct drm_radeon_gem_set_tiling args
;
753 memset(&args
, 0, sizeof(args
));
755 /* Tiling determines how DRM treats the buffer data.
756 * We must flush CS when changing it if the buffer is referenced. */
757 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
758 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
761 while (p_atomic_read(&bo
->num_active_ioctls
)) {
765 if (microtiled
== RADEON_LAYOUT_TILED
)
766 args
.tiling_flags
|= RADEON_TILING_MICRO
;
767 else if (microtiled
== RADEON_LAYOUT_SQUARETILED
)
768 args
.tiling_flags
|= RADEON_TILING_MICRO_SQUARE
;
770 if (macrotiled
== RADEON_LAYOUT_TILED
)
771 args
.tiling_flags
|= RADEON_TILING_MACRO
;
773 args
.tiling_flags
|= (bankw
& RADEON_TILING_EG_BANKW_MASK
) <<
774 RADEON_TILING_EG_BANKW_SHIFT
;
775 args
.tiling_flags
|= (bankh
& RADEON_TILING_EG_BANKH_MASK
) <<
776 RADEON_TILING_EG_BANKH_SHIFT
;
778 args
.tiling_flags
|= (eg_tile_split_rev(tile_split
) &
779 RADEON_TILING_EG_TILE_SPLIT_MASK
) <<
780 RADEON_TILING_EG_TILE_SPLIT_SHIFT
;
782 args
.tiling_flags
|= (stencil_tile_split
&
783 RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
) <<
784 RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
;
785 args
.tiling_flags
|= (mtilea
& RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
) <<
786 RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
;
788 if (bo
->rws
->gen
>= DRV_SI
&& !scanout
)
789 args
.tiling_flags
|= RADEON_TILING_R600_NO_SCANOUT
;
791 args
.handle
= bo
->handle
;
794 drmCommandWriteRead(bo
->rws
->fd
,
795 DRM_RADEON_GEM_SET_TILING
,
800 static struct radeon_winsys_cs_handle
*radeon_drm_get_cs_handle(struct pb_buffer
*_buf
)
802 /* return radeon_bo. */
803 return (struct radeon_winsys_cs_handle
*)get_radeon_bo(_buf
);
806 static struct pb_buffer
*
807 radeon_winsys_bo_create(struct radeon_winsys
*rws
,
810 boolean use_reusable_pool
,
811 enum radeon_bo_domain domain
,
812 enum radeon_bo_flag flags
)
814 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
815 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
816 struct radeon_bo_desc desc
;
817 struct pb_manager
*provider
;
818 struct pb_buffer
*buffer
;
820 memset(&desc
, 0, sizeof(desc
));
821 desc
.base
.alignment
= alignment
;
823 /* Only set one usage bit each for domains and flags, or the cache manager
824 * might consider different sets of domains / flags compatible
826 if (domain
== RADEON_DOMAIN_VRAM_GTT
)
827 desc
.base
.usage
= 1 << 2;
829 desc
.base
.usage
= domain
>> 1;
830 assert(flags
< sizeof(desc
.base
.usage
) * 8 - 3);
831 desc
.base
.usage
|= 1 << (flags
+ 3);
833 desc
.initial_domains
= domain
;
836 /* Assign a buffer manager. */
837 if (use_reusable_pool
)
842 buffer
= provider
->create_buffer(provider
, size
, &desc
.base
);
846 pipe_mutex_lock(mgr
->bo_handles_mutex
);
847 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)get_radeon_bo(buffer
)->handle
, buffer
);
848 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
850 return (struct pb_buffer
*)buffer
;
853 static struct pb_buffer
*radeon_winsys_bo_from_ptr(struct radeon_winsys
*rws
,
854 void *pointer
, unsigned size
)
856 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
857 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
858 struct drm_radeon_gem_userptr args
;
859 struct radeon_bo
*bo
;
862 bo
= CALLOC_STRUCT(radeon_bo
);
866 memset(&args
, 0, sizeof(args
));
867 args
.addr
= (uintptr_t)pointer
;
868 args
.size
= align(size
, sysconf(_SC_PAGE_SIZE
));
869 args
.flags
= RADEON_GEM_USERPTR_ANONONLY
|
870 RADEON_GEM_USERPTR_VALIDATE
|
871 RADEON_GEM_USERPTR_REGISTER
;
872 if (drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_USERPTR
,
873 &args
, sizeof(args
))) {
878 pipe_mutex_lock(mgr
->bo_handles_mutex
);
881 pipe_reference_init(&bo
->base
.reference
, 1);
882 bo
->handle
= args
.handle
;
883 bo
->base
.alignment
= 0;
884 bo
->base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
885 bo
->base
.size
= size
;
886 bo
->base
.vtbl
= &radeon_bo_vtbl
;
889 bo
->user_ptr
= pointer
;
891 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
892 pipe_mutex_init(bo
->map_mutex
);
894 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
896 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
899 struct drm_radeon_gem_va va
;
901 bo
->va
= radeon_bomgr_find_va(mgr
, bo
->base
.size
, 1 << 20);
903 va
.handle
= bo
->handle
;
904 va
.operation
= RADEON_VA_MAP
;
907 va
.flags
= RADEON_VM_PAGE_READABLE
|
908 RADEON_VM_PAGE_WRITEABLE
|
909 RADEON_VM_PAGE_SNOOPED
;
911 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
912 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
913 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
914 radeon_bo_destroy(&bo
->base
);
917 pipe_mutex_lock(mgr
->bo_handles_mutex
);
918 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
919 struct pb_buffer
*b
= &bo
->base
;
920 struct radeon_bo
*old_bo
=
921 util_hash_table_get(mgr
->bo_vas
, (void*)(uintptr_t)va
.offset
);
923 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
924 pb_reference(&b
, &old_bo
->base
);
928 util_hash_table_set(mgr
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
929 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
932 ws
->allocated_gtt
+= align(bo
->base
.size
, 4096);
934 return (struct pb_buffer
*)bo
;
937 static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys
*rws
,
938 struct winsys_handle
*whandle
,
941 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
942 struct radeon_bo
*bo
;
943 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
948 /* We must maintain a list of pairs <handle, bo>, so that we always return
949 * the same BO for one particular handle. If we didn't do that and created
950 * more than one BO for the same handle and then relocated them in a CS,
951 * we would hit a deadlock in the kernel.
953 * The list of pairs is guarded by a mutex, of course. */
954 pipe_mutex_lock(mgr
->bo_handles_mutex
);
956 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
957 /* First check if there already is an existing bo for the handle. */
958 bo
= util_hash_table_get(mgr
->bo_names
, (void*)(uintptr_t)whandle
->handle
);
959 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
960 /* We must first get the GEM handle, as fds are unreliable keys */
961 r
= drmPrimeFDToHandle(ws
->fd
, whandle
->handle
, &handle
);
964 bo
= util_hash_table_get(mgr
->bo_handles
, (void*)(uintptr_t)handle
);
966 /* Unknown handle type */
971 /* Increase the refcount. */
972 struct pb_buffer
*b
= NULL
;
973 pb_reference(&b
, &bo
->base
);
977 /* There isn't, create a new one. */
978 bo
= CALLOC_STRUCT(radeon_bo
);
983 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
984 struct drm_gem_open open_arg
= {};
985 memset(&open_arg
, 0, sizeof(open_arg
));
987 open_arg
.name
= whandle
->handle
;
988 if (drmIoctl(ws
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
)) {
992 handle
= open_arg
.handle
;
993 size
= open_arg
.size
;
994 bo
->flink_name
= whandle
->handle
;
995 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
996 size
= lseek(whandle
->handle
, 0, SEEK_END
);
998 * Could check errno to determine whether the kernel is new enough, but
999 * it doesn't really matter why this failed, just that it failed.
1001 if (size
== (off_t
)-1) {
1005 lseek(whandle
->handle
, 0, SEEK_SET
);
1008 bo
->handle
= handle
;
1010 /* Initialize it. */
1011 pipe_reference_init(&bo
->base
.reference
, 1);
1012 bo
->base
.alignment
= 0;
1013 bo
->base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
1014 bo
->base
.size
= (unsigned) size
;
1015 bo
->base
.vtbl
= &radeon_bo_vtbl
;
1019 pipe_mutex_init(bo
->map_mutex
);
1022 util_hash_table_set(mgr
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
1024 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
1027 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
1030 *stride
= whandle
->stride
;
1032 if (mgr
->va
&& !bo
->va
) {
1033 struct drm_radeon_gem_va va
;
1035 bo
->va
= radeon_bomgr_find_va(mgr
, bo
->base
.size
, 1 << 20);
1037 va
.handle
= bo
->handle
;
1038 va
.operation
= RADEON_VA_MAP
;
1041 va
.flags
= RADEON_VM_PAGE_READABLE
|
1042 RADEON_VM_PAGE_WRITEABLE
|
1043 RADEON_VM_PAGE_SNOOPED
;
1045 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
1046 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
1047 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
1048 radeon_bo_destroy(&bo
->base
);
1051 pipe_mutex_lock(mgr
->bo_handles_mutex
);
1052 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
1053 struct pb_buffer
*b
= &bo
->base
;
1054 struct radeon_bo
*old_bo
=
1055 util_hash_table_get(mgr
->bo_vas
, (void*)(uintptr_t)va
.offset
);
1057 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
1058 pb_reference(&b
, &old_bo
->base
);
1062 util_hash_table_set(mgr
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
1063 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
1066 bo
->initial_domain
= radeon_bo_get_initial_domain((void*)bo
);
1068 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1069 ws
->allocated_vram
+= align(bo
->base
.size
, 4096);
1070 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1071 ws
->allocated_gtt
+= align(bo
->base
.size
, 4096);
1073 return (struct pb_buffer
*)bo
;
1076 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
1080 static boolean
radeon_winsys_bo_get_handle(struct pb_buffer
*buffer
,
1082 struct winsys_handle
*whandle
)
1084 struct drm_gem_flink flink
;
1085 struct radeon_bo
*bo
= get_radeon_bo(buffer
);
1087 memset(&flink
, 0, sizeof(flink
));
1089 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
1090 if (!bo
->flink_name
) {
1091 flink
.handle
= bo
->handle
;
1093 if (ioctl(bo
->rws
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
)) {
1097 bo
->flink_name
= flink
.name
;
1099 pipe_mutex_lock(bo
->mgr
->bo_handles_mutex
);
1100 util_hash_table_set(bo
->mgr
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
1101 pipe_mutex_unlock(bo
->mgr
->bo_handles_mutex
);
1103 whandle
->handle
= bo
->flink_name
;
1104 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
1105 whandle
->handle
= bo
->handle
;
1106 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
1107 if (drmPrimeHandleToFD(bo
->rws
->fd
, bo
->handle
, DRM_CLOEXEC
, (int*)&whandle
->handle
))
1111 whandle
->stride
= stride
;
1115 static uint64_t radeon_winsys_bo_va(struct radeon_winsys_cs_handle
*buf
)
1117 return ((struct radeon_bo
*)buf
)->va
;
1120 void radeon_bomgr_init_functions(struct radeon_drm_winsys
*ws
)
1122 ws
->base
.buffer_get_cs_handle
= radeon_drm_get_cs_handle
;
1123 ws
->base
.buffer_set_tiling
= radeon_bo_set_tiling
;
1124 ws
->base
.buffer_get_tiling
= radeon_bo_get_tiling
;
1125 ws
->base
.buffer_map
= radeon_bo_map
;
1126 ws
->base
.buffer_unmap
= radeon_bo_unmap
;
1127 ws
->base
.buffer_wait
= radeon_bo_wait
;
1128 ws
->base
.buffer_is_busy
= radeon_bo_is_busy
;
1129 ws
->base
.buffer_create
= radeon_winsys_bo_create
;
1130 ws
->base
.buffer_from_handle
= radeon_winsys_bo_from_handle
;
1131 ws
->base
.buffer_from_ptr
= radeon_winsys_bo_from_ptr
;
1132 ws
->base
.buffer_get_handle
= radeon_winsys_bo_get_handle
;
1133 ws
->base
.buffer_get_virtual_address
= radeon_winsys_bo_va
;
1134 ws
->base
.buffer_get_initial_domain
= radeon_bo_get_initial_domain
;