2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
27 #define _FILE_OFFSET_BITS 64
28 #include "radeon_drm_cs.h"
30 #include "util/u_hash_table.h"
31 #include "util/u_memory.h"
32 #include "util/u_simple_list.h"
33 #include "util/u_double_list.h"
34 #include "os/os_thread.h"
35 #include "os/os_mman.h"
36 #include "os/os_time.h"
38 #include "state_tracker/drm_driver.h"
40 #include <sys/ioctl.h>
46 * this are copy from radeon_drm, once an updated libdrm is released
47 * we should bump configure.ac requirement for it and remove the following
50 #define RADEON_BO_FLAGS_MACRO_TILE 1
51 #define RADEON_BO_FLAGS_MICRO_TILE 2
52 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
54 #ifndef DRM_RADEON_GEM_WAIT
55 #define DRM_RADEON_GEM_WAIT 0x2b
57 #define RADEON_GEM_NO_WAIT 0x1
58 #define RADEON_GEM_USAGE_READ 0x2
59 #define RADEON_GEM_USAGE_WRITE 0x4
61 struct drm_radeon_gem_wait
{
63 uint32_t flags
; /* one of RADEON_GEM_* */
70 #define RADEON_VA_MAP 1
71 #define RADEON_VA_UNMAP 2
73 #define RADEON_VA_RESULT_OK 0
74 #define RADEON_VA_RESULT_ERROR 1
75 #define RADEON_VA_RESULT_VA_EXIST 2
77 #define RADEON_VM_PAGE_VALID (1 << 0)
78 #define RADEON_VM_PAGE_READABLE (1 << 1)
79 #define RADEON_VM_PAGE_WRITEABLE (1 << 2)
80 #define RADEON_VM_PAGE_SYSTEM (1 << 3)
81 #define RADEON_VM_PAGE_SNOOPED (1 << 4)
83 struct drm_radeon_gem_va
{
91 #define DRM_RADEON_GEM_VA 0x2b
96 extern const struct pb_vtbl radeon_bo_vtbl
;
99 static INLINE
struct radeon_bo
*radeon_bo(struct pb_buffer
*bo
)
101 assert(bo
->vtbl
== &radeon_bo_vtbl
);
102 return (struct radeon_bo
*)bo
;
105 struct radeon_bo_va_hole
{
106 struct list_head list
;
111 struct radeon_bomgr
{
113 struct pb_manager base
;
116 struct radeon_drm_winsys
*rws
;
118 /* List of buffer GEM names. Protected by bo_handles_mutex. */
119 struct util_hash_table
*bo_names
;
120 /* List of buffer handles. Protectded by bo_handles_mutex. */
121 struct util_hash_table
*bo_handles
;
122 pipe_mutex bo_handles_mutex
;
123 pipe_mutex bo_va_mutex
;
125 /* is virtual address supported */
128 struct list_head va_holes
;
131 static INLINE
struct radeon_bomgr
*radeon_bomgr(struct pb_manager
*mgr
)
133 return (struct radeon_bomgr
*)mgr
;
136 static struct radeon_bo
*get_radeon_bo(struct pb_buffer
*_buf
)
138 struct radeon_bo
*bo
= NULL
;
140 if (_buf
->vtbl
== &radeon_bo_vtbl
) {
141 bo
= radeon_bo(_buf
);
143 struct pb_buffer
*base_buf
;
145 pb_get_base_buffer(_buf
, &base_buf
, &offset
);
147 if (base_buf
->vtbl
== &radeon_bo_vtbl
)
148 bo
= radeon_bo(base_buf
);
154 static void radeon_bo_wait(struct pb_buffer
*_buf
, enum radeon_bo_usage usage
)
156 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
158 while (p_atomic_read(&bo
->num_active_ioctls
)) {
162 /* XXX use this when it's ready */
163 /*if (bo->rws->info.drm_minor >= 12) {
164 struct drm_radeon_gem_wait args = {};
165 args.handle = bo->handle;
167 while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
168 &args, sizeof(args)) == -EBUSY);
170 struct drm_radeon_gem_wait_idle args
;
171 memset(&args
, 0, sizeof(args
));
172 args
.handle
= bo
->handle
;
173 while (drmCommandWrite(bo
->rws
->fd
, DRM_RADEON_GEM_WAIT_IDLE
,
174 &args
, sizeof(args
)) == -EBUSY
);
178 static boolean
radeon_bo_is_busy(struct pb_buffer
*_buf
,
179 enum radeon_bo_usage usage
)
181 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
183 if (p_atomic_read(&bo
->num_active_ioctls
)) {
187 /* XXX use this when it's ready */
188 /*if (bo->rws->info.drm_minor >= 12) {
189 struct drm_radeon_gem_wait args = {};
190 args.handle = bo->handle;
191 args.flags = usage | RADEON_GEM_NO_WAIT;
192 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
193 &args, sizeof(args)) != 0;
195 struct drm_radeon_gem_busy args
;
196 memset(&args
, 0, sizeof(args
));
197 args
.handle
= bo
->handle
;
198 return drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_BUSY
,
199 &args
, sizeof(args
)) != 0;
203 static uint64_t radeon_bomgr_find_va(struct radeon_bomgr
*mgr
, uint64_t size
, uint64_t alignment
)
205 struct radeon_bo_va_hole
*hole
, *n
;
206 uint64_t offset
= 0, waste
= 0;
208 alignment
= MAX2(alignment
, 4096);
209 size
= align(size
, 4096);
211 pipe_mutex_lock(mgr
->bo_va_mutex
);
212 /* first look for a hole */
213 LIST_FOR_EACH_ENTRY_SAFE(hole
, n
, &mgr
->va_holes
, list
) {
214 offset
= hole
->offset
;
215 waste
= offset
% alignment
;
216 waste
= waste
? alignment
- waste
: 0;
218 if (offset
>= (hole
->offset
+ hole
->size
)) {
221 if (!waste
&& hole
->size
== size
) {
222 offset
= hole
->offset
;
223 list_del(&hole
->list
);
225 pipe_mutex_unlock(mgr
->bo_va_mutex
);
228 if ((hole
->size
- waste
) > size
) {
230 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
232 n
->offset
= hole
->offset
;
233 list_add(&n
->list
, &hole
->list
);
235 hole
->size
-= (size
+ waste
);
236 hole
->offset
+= size
+ waste
;
237 pipe_mutex_unlock(mgr
->bo_va_mutex
);
240 if ((hole
->size
- waste
) == size
) {
242 pipe_mutex_unlock(mgr
->bo_va_mutex
);
247 offset
= mgr
->va_offset
;
248 waste
= offset
% alignment
;
249 waste
= waste
? alignment
- waste
: 0;
251 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
254 list_add(&n
->list
, &mgr
->va_holes
);
257 mgr
->va_offset
+= size
+ waste
;
258 pipe_mutex_unlock(mgr
->bo_va_mutex
);
262 static void radeon_bomgr_force_va(struct radeon_bomgr
*mgr
, uint64_t va
, uint64_t size
)
264 size
= align(size
, 4096);
266 pipe_mutex_lock(mgr
->bo_va_mutex
);
267 if (va
>= mgr
->va_offset
) {
268 if (va
> mgr
->va_offset
) {
269 struct radeon_bo_va_hole
*hole
;
270 hole
= CALLOC_STRUCT(radeon_bo_va_hole
);
272 hole
->size
= va
- mgr
->va_offset
;
273 hole
->offset
= mgr
->va_offset
;
274 list_add(&hole
->list
, &mgr
->va_holes
);
277 mgr
->va_offset
= va
+ size
;
279 struct radeon_bo_va_hole
*hole
, *n
;
280 uint64_t hole_end
, va_end
;
282 /* Prune/free all holes that fall into the range
284 LIST_FOR_EACH_ENTRY_SAFE(hole
, n
, &mgr
->va_holes
, list
) {
285 hole_end
= hole
->offset
+ hole
->size
;
287 if (hole
->offset
>= va_end
|| hole_end
<= va
)
289 if (hole
->offset
>= va
&& hole_end
<= va_end
) {
290 list_del(&hole
->list
);
294 if (hole
->offset
>= va
)
295 hole
->offset
= va_end
;
298 hole
->size
= hole_end
- hole
->offset
;
301 pipe_mutex_unlock(mgr
->bo_va_mutex
);
304 static void radeon_bomgr_free_va(struct radeon_bomgr
*mgr
, uint64_t va
, uint64_t size
)
306 struct radeon_bo_va_hole
*hole
;
308 size
= align(size
, 4096);
310 pipe_mutex_lock(mgr
->bo_va_mutex
);
311 if ((va
+ size
) == mgr
->va_offset
) {
313 /* Delete uppermost hole if it reaches the new top */
314 if (!LIST_IS_EMPTY(&mgr
->va_holes
)) {
315 hole
= container_of(mgr
->va_holes
.next
, hole
, list
);
316 if ((hole
->offset
+ hole
->size
) == va
) {
317 mgr
->va_offset
= hole
->offset
;
318 list_del(&hole
->list
);
323 struct radeon_bo_va_hole
*next
;
325 hole
= container_of(&mgr
->va_holes
, hole
, list
);
326 LIST_FOR_EACH_ENTRY(next
, &mgr
->va_holes
, list
) {
327 if (next
->offset
< va
)
332 if (&hole
->list
!= &mgr
->va_holes
) {
333 /* Grow upper hole if it's adjacent */
334 if (hole
->offset
== (va
+ size
)) {
337 /* Merge lower hole if it's adjacent */
338 if (next
!= hole
&& &next
->list
!= &mgr
->va_holes
&&
339 (next
->offset
+ next
->size
) == va
) {
340 next
->size
+= hole
->size
;
341 list_del(&hole
->list
);
348 /* Grow lower hole if it's adjacent */
349 if (next
!= hole
&& &next
->list
!= &mgr
->va_holes
&&
350 (next
->offset
+ next
->size
) == va
) {
355 /* FIXME on allocation failure we just lose virtual address space
356 * maybe print a warning
358 next
= CALLOC_STRUCT(radeon_bo_va_hole
);
362 list_add(&next
->list
, &hole
->list
);
366 pipe_mutex_unlock(mgr
->bo_va_mutex
);
369 static void radeon_bo_destroy(struct pb_buffer
*_buf
)
371 struct radeon_bo
*bo
= radeon_bo(_buf
);
372 struct radeon_bomgr
*mgr
= bo
->mgr
;
373 struct drm_gem_close args
;
375 memset(&args
, 0, sizeof(args
));
377 pipe_mutex_lock(bo
->mgr
->bo_handles_mutex
);
378 util_hash_table_remove(bo
->mgr
->bo_handles
, (void*)(uintptr_t)bo
->handle
);
380 util_hash_table_remove(bo
->mgr
->bo_names
,
381 (void*)(uintptr_t)bo
->name
);
383 pipe_mutex_unlock(bo
->mgr
->bo_handles_mutex
);
386 os_munmap(bo
->ptr
, bo
->base
.size
);
389 args
.handle
= bo
->handle
;
390 drmIoctl(bo
->rws
->fd
, DRM_IOCTL_GEM_CLOSE
, &args
);
393 radeon_bomgr_free_va(mgr
, bo
->va
, bo
->base
.size
);
396 pipe_mutex_destroy(bo
->map_mutex
);
398 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
399 bo
->rws
->allocated_vram
-= align(bo
->base
.size
, 4096);
400 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
401 bo
->rws
->allocated_gtt
-= align(bo
->base
.size
, 4096);
405 void *radeon_bo_do_map(struct radeon_bo
*bo
)
407 struct drm_radeon_gem_mmap args
= {0};
410 /* Return the pointer if it's already mapped. */
414 /* Map the buffer. */
415 pipe_mutex_lock(bo
->map_mutex
);
416 /* Return the pointer if it's already mapped (in case of a race). */
418 pipe_mutex_unlock(bo
->map_mutex
);
421 args
.handle
= bo
->handle
;
423 args
.size
= (uint64_t)bo
->base
.size
;
424 if (drmCommandWriteRead(bo
->rws
->fd
,
428 pipe_mutex_unlock(bo
->map_mutex
);
429 fprintf(stderr
, "radeon: gem_mmap failed: %p 0x%08X\n",
434 ptr
= os_mmap(0, args
.size
, PROT_READ
|PROT_WRITE
, MAP_SHARED
,
435 bo
->rws
->fd
, args
.addr_ptr
);
436 if (ptr
== MAP_FAILED
) {
437 pipe_mutex_unlock(bo
->map_mutex
);
438 fprintf(stderr
, "radeon: mmap failed, errno: %i\n", errno
);
442 pipe_mutex_unlock(bo
->map_mutex
);
447 static void *radeon_bo_map(struct radeon_winsys_cs_handle
*buf
,
448 struct radeon_winsys_cs
*rcs
,
449 enum pipe_transfer_usage usage
)
451 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
452 struct radeon_drm_cs
*cs
= (struct radeon_drm_cs
*)rcs
;
454 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
455 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
456 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
457 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
458 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
461 * Since we are mapping for read, we don't need to wait
462 * if the GPU is using the buffer for read too
463 * (neither one is changing it).
465 * Only check whether the buffer is being used for write. */
466 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
467 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
);
471 if (radeon_bo_is_busy((struct pb_buffer
*)bo
,
472 RADEON_USAGE_WRITE
)) {
476 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
477 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
);
481 if (radeon_bo_is_busy((struct pb_buffer
*)bo
,
482 RADEON_USAGE_READWRITE
)) {
487 uint64_t time
= os_time_get_nano();
489 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
492 * Since we are mapping for read, we don't need to wait
493 * if the GPU is using the buffer for read too
494 * (neither one is changing it).
496 * Only check whether the buffer is being used for write. */
497 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
498 cs
->flush_cs(cs
->flush_data
, 0);
500 radeon_bo_wait((struct pb_buffer
*)bo
,
503 /* Mapping for write. */
505 if (radeon_bo_is_referenced_by_cs(cs
, bo
)) {
506 cs
->flush_cs(cs
->flush_data
, 0);
508 /* Try to avoid busy-waiting in radeon_bo_wait. */
509 if (p_atomic_read(&bo
->num_active_ioctls
))
510 radeon_drm_cs_sync_flush(rcs
);
514 radeon_bo_wait((struct pb_buffer
*)bo
, RADEON_USAGE_READWRITE
);
517 bo
->mgr
->rws
->buffer_wait_time
+= os_time_get_nano() - time
;
521 return radeon_bo_do_map(bo
);
524 static void radeon_bo_unmap(struct radeon_winsys_cs_handle
*_buf
)
529 static void radeon_bo_get_base_buffer(struct pb_buffer
*buf
,
530 struct pb_buffer
**base_buf
,
537 static enum pipe_error
radeon_bo_validate(struct pb_buffer
*_buf
,
538 struct pb_validate
*vl
,
545 static void radeon_bo_fence(struct pb_buffer
*buf
,
546 struct pipe_fence_handle
*fence
)
550 const struct pb_vtbl radeon_bo_vtbl
= {
552 NULL
, /* never called */
553 NULL
, /* never called */
556 radeon_bo_get_base_buffer
,
559 static struct pb_buffer
*radeon_bomgr_create_bo(struct pb_manager
*_mgr
,
561 const struct pb_desc
*desc
)
563 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
564 struct radeon_drm_winsys
*rws
= mgr
->rws
;
565 struct radeon_bo
*bo
;
566 struct drm_radeon_gem_create args
;
567 struct radeon_bo_desc
*rdesc
= (struct radeon_bo_desc
*)desc
;
570 memset(&args
, 0, sizeof(args
));
572 assert(rdesc
->initial_domains
);
573 assert((rdesc
->initial_domains
&
574 ~(RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
)) == 0);
577 args
.alignment
= desc
->alignment
;
578 args
.initial_domain
= rdesc
->initial_domains
;
580 if (drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_CREATE
,
581 &args
, sizeof(args
))) {
582 fprintf(stderr
, "radeon: Failed to allocate a buffer:\n");
583 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
584 fprintf(stderr
, "radeon: alignment : %d bytes\n", desc
->alignment
);
585 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
589 bo
= CALLOC_STRUCT(radeon_bo
);
593 pipe_reference_init(&bo
->base
.reference
, 1);
594 bo
->base
.alignment
= desc
->alignment
;
595 bo
->base
.usage
= desc
->usage
;
596 bo
->base
.size
= size
;
597 bo
->base
.vtbl
= &radeon_bo_vtbl
;
600 bo
->handle
= args
.handle
;
602 bo
->initial_domain
= rdesc
->initial_domains
;
603 pipe_mutex_init(bo
->map_mutex
);
606 struct drm_radeon_gem_va va
;
608 bo
->va
= radeon_bomgr_find_va(mgr
, size
, desc
->alignment
);
610 va
.handle
= bo
->handle
;
612 va
.operation
= RADEON_VA_MAP
;
613 va
.flags
= RADEON_VM_PAGE_READABLE
|
614 RADEON_VM_PAGE_WRITEABLE
|
615 RADEON_VM_PAGE_SNOOPED
;
617 r
= drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
618 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
619 fprintf(stderr
, "radeon: Failed to allocate virtual address for buffer:\n");
620 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
621 fprintf(stderr
, "radeon: alignment : %d bytes\n", desc
->alignment
);
622 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
623 fprintf(stderr
, "radeon: va : 0x%016llx\n", (unsigned long long)bo
->va
);
624 radeon_bo_destroy(&bo
->base
);
627 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
628 radeon_bomgr_free_va(mgr
, bo
->va
, size
);
630 radeon_bomgr_force_va(mgr
, bo
->va
, size
);
634 if (rdesc
->initial_domains
& RADEON_DOMAIN_VRAM
)
635 rws
->allocated_vram
+= align(size
, 4096);
636 else if (rdesc
->initial_domains
& RADEON_DOMAIN_GTT
)
637 rws
->allocated_gtt
+= align(size
, 4096);
642 static void radeon_bomgr_flush(struct pb_manager
*mgr
)
647 /* This is for the cache bufmgr. */
648 static boolean
radeon_bomgr_is_buffer_busy(struct pb_manager
*_mgr
,
649 struct pb_buffer
*_buf
)
651 struct radeon_bo
*bo
= radeon_bo(_buf
);
653 if (radeon_bo_is_referenced_by_any_cs(bo
)) {
657 if (radeon_bo_is_busy((struct pb_buffer
*)bo
, RADEON_USAGE_READWRITE
)) {
664 static void radeon_bomgr_destroy(struct pb_manager
*_mgr
)
666 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
667 util_hash_table_destroy(mgr
->bo_names
);
668 util_hash_table_destroy(mgr
->bo_handles
);
669 pipe_mutex_destroy(mgr
->bo_handles_mutex
);
670 pipe_mutex_destroy(mgr
->bo_va_mutex
);
674 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
676 static unsigned handle_hash(void *key
)
678 return PTR_TO_UINT(key
);
681 static int handle_compare(void *key1
, void *key2
)
683 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
686 struct pb_manager
*radeon_bomgr_create(struct radeon_drm_winsys
*rws
)
688 struct radeon_bomgr
*mgr
;
690 mgr
= CALLOC_STRUCT(radeon_bomgr
);
694 mgr
->base
.destroy
= radeon_bomgr_destroy
;
695 mgr
->base
.create_buffer
= radeon_bomgr_create_bo
;
696 mgr
->base
.flush
= radeon_bomgr_flush
;
697 mgr
->base
.is_buffer_busy
= radeon_bomgr_is_buffer_busy
;
700 mgr
->bo_names
= util_hash_table_create(handle_hash
, handle_compare
);
701 mgr
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
702 pipe_mutex_init(mgr
->bo_handles_mutex
);
703 pipe_mutex_init(mgr
->bo_va_mutex
);
705 mgr
->va
= rws
->info
.r600_virtual_address
;
706 mgr
->va_offset
= rws
->info
.r600_va_start
;
707 list_inithead(&mgr
->va_holes
);
712 static unsigned eg_tile_split(unsigned tile_split
)
714 switch (tile_split
) {
715 case 0: tile_split
= 64; break;
716 case 1: tile_split
= 128; break;
717 case 2: tile_split
= 256; break;
718 case 3: tile_split
= 512; break;
720 case 4: tile_split
= 1024; break;
721 case 5: tile_split
= 2048; break;
722 case 6: tile_split
= 4096; break;
727 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
729 switch (eg_tile_split
) {
741 static void radeon_bo_get_tiling(struct pb_buffer
*_buf
,
742 enum radeon_bo_layout
*microtiled
,
743 enum radeon_bo_layout
*macrotiled
,
744 unsigned *bankw
, unsigned *bankh
,
745 unsigned *tile_split
,
746 unsigned *stencil_tile_split
,
750 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
751 struct drm_radeon_gem_set_tiling args
;
753 memset(&args
, 0, sizeof(args
));
755 args
.handle
= bo
->handle
;
757 drmCommandWriteRead(bo
->rws
->fd
,
758 DRM_RADEON_GEM_GET_TILING
,
762 *microtiled
= RADEON_LAYOUT_LINEAR
;
763 *macrotiled
= RADEON_LAYOUT_LINEAR
;
764 if (args
.tiling_flags
& RADEON_BO_FLAGS_MICRO_TILE
)
765 *microtiled
= RADEON_LAYOUT_TILED
;
767 if (args
.tiling_flags
& RADEON_BO_FLAGS_MACRO_TILE
)
768 *macrotiled
= RADEON_LAYOUT_TILED
;
769 if (bankw
&& tile_split
&& stencil_tile_split
&& mtilea
&& tile_split
) {
770 *bankw
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
771 *bankh
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
772 *tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
773 *stencil_tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
;
774 *mtilea
= (args
.tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
775 *tile_split
= eg_tile_split(*tile_split
);
778 *scanout
= bo
->rws
->gen
>= DRV_SI
&& !(args
.tiling_flags
& RADEON_TILING_R600_NO_SCANOUT
);
781 static void radeon_bo_set_tiling(struct pb_buffer
*_buf
,
782 struct radeon_winsys_cs
*rcs
,
783 enum radeon_bo_layout microtiled
,
784 enum radeon_bo_layout macrotiled
,
785 unsigned bankw
, unsigned bankh
,
787 unsigned stencil_tile_split
,
792 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
793 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
794 struct drm_radeon_gem_set_tiling args
;
796 memset(&args
, 0, sizeof(args
));
798 /* Tiling determines how DRM treats the buffer data.
799 * We must flush CS when changing it if the buffer is referenced. */
800 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
801 cs
->flush_cs(cs
->flush_data
, 0);
804 while (p_atomic_read(&bo
->num_active_ioctls
)) {
808 if (microtiled
== RADEON_LAYOUT_TILED
)
809 args
.tiling_flags
|= RADEON_BO_FLAGS_MICRO_TILE
;
810 else if (microtiled
== RADEON_LAYOUT_SQUARETILED
)
811 args
.tiling_flags
|= RADEON_BO_FLAGS_MICRO_TILE_SQUARE
;
813 if (macrotiled
== RADEON_LAYOUT_TILED
)
814 args
.tiling_flags
|= RADEON_BO_FLAGS_MACRO_TILE
;
816 args
.tiling_flags
|= (bankw
& RADEON_TILING_EG_BANKW_MASK
) <<
817 RADEON_TILING_EG_BANKW_SHIFT
;
818 args
.tiling_flags
|= (bankh
& RADEON_TILING_EG_BANKH_MASK
) <<
819 RADEON_TILING_EG_BANKH_SHIFT
;
821 args
.tiling_flags
|= (eg_tile_split_rev(tile_split
) &
822 RADEON_TILING_EG_TILE_SPLIT_MASK
) <<
823 RADEON_TILING_EG_TILE_SPLIT_SHIFT
;
825 args
.tiling_flags
|= (stencil_tile_split
&
826 RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
) <<
827 RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
;
828 args
.tiling_flags
|= (mtilea
& RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
) <<
829 RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
;
831 if (bo
->rws
->gen
>= DRV_SI
&& !scanout
)
832 args
.tiling_flags
|= RADEON_TILING_R600_NO_SCANOUT
;
834 args
.handle
= bo
->handle
;
837 drmCommandWriteRead(bo
->rws
->fd
,
838 DRM_RADEON_GEM_SET_TILING
,
843 static struct radeon_winsys_cs_handle
*radeon_drm_get_cs_handle(struct pb_buffer
*_buf
)
845 /* return radeon_bo. */
846 return (struct radeon_winsys_cs_handle
*)get_radeon_bo(_buf
);
849 static struct pb_buffer
*
850 radeon_winsys_bo_create(struct radeon_winsys
*rws
,
853 boolean use_reusable_pool
,
854 enum radeon_bo_domain domain
)
856 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
857 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
858 struct radeon_bo_desc desc
;
859 struct pb_manager
*provider
;
860 struct pb_buffer
*buffer
;
862 memset(&desc
, 0, sizeof(desc
));
863 desc
.base
.alignment
= alignment
;
865 /* Additional criteria for the cache manager. */
866 desc
.base
.usage
= domain
;
867 desc
.initial_domains
= domain
;
869 /* Assign a buffer manager. */
870 if (use_reusable_pool
)
875 buffer
= provider
->create_buffer(provider
, size
, &desc
.base
);
879 pipe_mutex_lock(mgr
->bo_handles_mutex
);
880 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)get_radeon_bo(buffer
)->handle
, buffer
);
881 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
883 return (struct pb_buffer
*)buffer
;
886 static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys
*rws
,
887 struct winsys_handle
*whandle
,
890 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
891 struct radeon_bo
*bo
;
892 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
893 struct drm_radeon_gem_busy args
;
898 /* We must maintain a list of pairs <handle, bo>, so that we always return
899 * the same BO for one particular handle. If we didn't do that and created
900 * more than one BO for the same handle and then relocated them in a CS,
901 * we would hit a deadlock in the kernel.
903 * The list of pairs is guarded by a mutex, of course. */
904 pipe_mutex_lock(mgr
->bo_handles_mutex
);
906 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
907 /* First check if there already is an existing bo for the handle. */
908 bo
= util_hash_table_get(mgr
->bo_names
, (void*)(uintptr_t)whandle
->handle
);
909 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
910 /* We must first get the GEM handle, as fds are unreliable keys */
911 r
= drmPrimeFDToHandle(ws
->fd
, whandle
->handle
, &handle
);
914 bo
= util_hash_table_get(mgr
->bo_handles
, (void*)(uintptr_t)handle
);
916 /* Unknown handle type */
921 /* Increase the refcount. */
922 struct pb_buffer
*b
= NULL
;
923 pb_reference(&b
, &bo
->base
);
927 /* There isn't, create a new one. */
928 bo
= CALLOC_STRUCT(radeon_bo
);
933 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
934 struct drm_gem_open open_arg
= {};
935 memset(&open_arg
, 0, sizeof(open_arg
));
937 open_arg
.name
= whandle
->handle
;
938 if (drmIoctl(ws
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
)) {
942 handle
= open_arg
.handle
;
943 size
= open_arg
.size
;
944 bo
->name
= whandle
->handle
;
945 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
946 size
= lseek(whandle
->handle
, 0, SEEK_END
);
948 * Could check errno to determine whether the kernel is new enough, but
949 * it doesn't really matter why this failed, just that it failed.
951 if (size
== (off_t
)-1) {
955 lseek(whandle
->handle
, 0, SEEK_SET
);
961 pipe_reference_init(&bo
->base
.reference
, 1);
962 bo
->base
.alignment
= 0;
963 bo
->base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
964 bo
->base
.size
= (unsigned) size
;
965 bo
->base
.vtbl
= &radeon_bo_vtbl
;
969 pipe_mutex_init(bo
->map_mutex
);
972 util_hash_table_set(mgr
->bo_names
, (void*)(uintptr_t)bo
->name
, bo
);
974 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
977 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
980 *stride
= whandle
->stride
;
982 if (mgr
->va
&& !bo
->va
) {
983 struct drm_radeon_gem_va va
;
985 bo
->va
= radeon_bomgr_find_va(mgr
, bo
->base
.size
, 1 << 20);
987 va
.handle
= bo
->handle
;
988 va
.operation
= RADEON_VA_MAP
;
991 va
.flags
= RADEON_VM_PAGE_READABLE
|
992 RADEON_VM_PAGE_WRITEABLE
|
993 RADEON_VM_PAGE_SNOOPED
;
995 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
996 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
997 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
998 radeon_bo_destroy(&bo
->base
);
1001 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
1002 radeon_bomgr_free_va(mgr
, bo
->va
, bo
->base
.size
);
1004 radeon_bomgr_force_va(mgr
, bo
->va
, bo
->base
.size
);
1008 memset(&args
, 0, sizeof(args
));
1010 args
.handle
= bo
->handle
;
1011 r
= drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_BUSY
, &args
, sizeof(args
));
1012 /* We don't mind if the bo is busy; we're just after the memory domain */
1013 if (r
&& r
!= -EBUSY
) {
1014 fprintf(stderr
, "radeon: Failed to find initial domain for imported bo\n");
1015 radeon_bo_destroy(&bo
->base
);
1018 bo
->initial_domain
= args
.domain
;
1020 switch (bo
->initial_domain
) {
1021 case RADEON_DOMAIN_GTT
:
1022 ws
->allocated_gtt
+= align(size
, 4096);
1024 case RADEON_DOMAIN_VRAM
:
1025 ws
->allocated_vram
+= align(size
, 4096);
1030 return (struct pb_buffer
*)bo
;
1033 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
1037 static boolean
radeon_winsys_bo_get_handle(struct pb_buffer
*buffer
,
1039 struct winsys_handle
*whandle
)
1041 struct drm_gem_flink flink
;
1042 struct radeon_bo
*bo
= get_radeon_bo(buffer
);
1044 memset(&flink
, 0, sizeof(flink
));
1046 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
1048 flink
.handle
= bo
->handle
;
1050 if (ioctl(bo
->rws
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
)) {
1055 bo
->flink
= flink
.name
;
1057 pipe_mutex_lock(bo
->mgr
->bo_handles_mutex
);
1058 util_hash_table_set(bo
->mgr
->bo_names
, (void*)(uintptr_t)bo
->flink
, bo
);
1059 pipe_mutex_unlock(bo
->mgr
->bo_handles_mutex
);
1061 whandle
->handle
= bo
->flink
;
1062 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
1063 whandle
->handle
= bo
->handle
;
1064 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
1065 if (drmPrimeHandleToFD(bo
->rws
->fd
, bo
->handle
, DRM_CLOEXEC
, (int*)&whandle
->handle
))
1069 whandle
->stride
= stride
;
1073 static uint64_t radeon_winsys_bo_va(struct radeon_winsys_cs_handle
*buf
)
1075 return ((struct radeon_bo
*)buf
)->va
;
1078 void radeon_bomgr_init_functions(struct radeon_drm_winsys
*ws
)
1080 ws
->base
.buffer_get_cs_handle
= radeon_drm_get_cs_handle
;
1081 ws
->base
.buffer_set_tiling
= radeon_bo_set_tiling
;
1082 ws
->base
.buffer_get_tiling
= radeon_bo_get_tiling
;
1083 ws
->base
.buffer_map
= radeon_bo_map
;
1084 ws
->base
.buffer_unmap
= radeon_bo_unmap
;
1085 ws
->base
.buffer_wait
= radeon_bo_wait
;
1086 ws
->base
.buffer_is_busy
= radeon_bo_is_busy
;
1087 ws
->base
.buffer_create
= radeon_winsys_bo_create
;
1088 ws
->base
.buffer_from_handle
= radeon_winsys_bo_from_handle
;
1089 ws
->base
.buffer_get_handle
= radeon_winsys_bo_get_handle
;
1090 ws
->base
.buffer_get_virtual_address
= radeon_winsys_bo_va
;