src/gallium/winsys/radeon/drm/radeon_drm_bo.c

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 #define _FILE_OFFSET_BITS 64
  28 #include "radeon_drm_cs.h"
  29
  30 #include "util/u_hash_table.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_simple_list.h"
  33 #include "os/os_thread.h"
  34
  35 #include "state_tracker/drm_driver.h"
  36
  37 #include <sys/ioctl.h>
  38 #include <sys/mman.h>
  39 #include <xf86drm.h>
  40 #include <errno.h>
  41
  42 #define RADEON_BO_FLAGS_MACRO_TILE  1
  43 #define RADEON_BO_FLAGS_MICRO_TILE  2
  44 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
  45
  46 extern const struct pb_vtbl radeon_bo_vtbl;
  47
  48
  49 static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
  50 {
  51     assert(bo->vtbl == &radeon_bo_vtbl);
  52     return (struct radeon_bo *)bo;
  53 }
  54
  55 struct radeon_bomgr {
  56     /* Base class. */
  57     struct pb_manager base;
  58
  59     /* Winsys. */
  60     struct radeon_drm_winsys *rws;
  61
  62     /* List of buffer handles and its mutex. */
  63     struct util_hash_table *bo_handles;
  64     pipe_mutex bo_handles_mutex;
  65 };
  66
  67 static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
  68 {
  69     return (struct radeon_bomgr *)mgr;
  70 }
  71
  72 static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
  73 {
  74     struct radeon_bo *bo = NULL;
  75
  76     if (_buf->vtbl == &radeon_bo_vtbl) {
  77         bo = radeon_bo(_buf);
  78     } else {
  79         struct pb_buffer *base_buf;
  80         pb_size offset;
  81         pb_get_base_buffer(_buf, &base_buf, &offset);
  82
  83         if (base_buf->vtbl == &radeon_bo_vtbl)
  84             bo = radeon_bo(base_buf);
  85     }
  86
  87     return bo;
  88 }
  89
  90 static void radeon_bo_wait(struct pb_buffer *_buf)
  91 {
  92     struct radeon_bo *bo = get_radeon_bo(_buf);
  93     struct drm_radeon_gem_wait_idle args = {};
  94
  95     while (p_atomic_read(&bo->num_active_ioctls)) {
  96         sched_yield();
  97     }
  98
  99     args.handle = bo->handle;
 100     while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
 101                                &args, sizeof(args)) == -EBUSY);
 102
 103     bo->busy_for_write = FALSE;
 104 }
 105
 106 static boolean radeon_bo_is_busy(struct pb_buffer *_buf)
 107 {
 108     struct radeon_bo *bo = get_radeon_bo(_buf);
 109     struct drm_radeon_gem_busy args = {};
 110     boolean busy;
 111
 112     if (p_atomic_read(&bo->num_active_ioctls)) {
 113         return TRUE;
 114     }
 115
 116     args.handle = bo->handle;
 117     busy = drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
 118                                &args, sizeof(args)) != 0;
 119
 120     if (!busy)
 121         bo->busy_for_write = FALSE;
 122     return busy;
 123 }
 124
 125 static void radeon_bo_destroy(struct pb_buffer *_buf)
 126 {
 127     struct radeon_bo *bo = radeon_bo(_buf);
 128     struct drm_gem_close args = {};
 129
 130     if (bo->name) {
 131         pipe_mutex_lock(bo->mgr->bo_handles_mutex);
 132         util_hash_table_remove(bo->mgr->bo_handles,
 133                                (void*)(uintptr_t)bo->name);
 134         pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
 135     }
 136
 137     if (bo->ptr)
 138         munmap(bo->ptr, bo->size);
 139
 140     /* Close object. */
 141     args.handle = bo->handle;
 142     drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
 143     pipe_mutex_destroy(bo->map_mutex);
 144     FREE(bo);
 145 }
 146
 147 static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage)
 148 {
 149     unsigned res = 0;
 150
 151     if (usage & PIPE_TRANSFER_WRITE)
 152         res |= PB_USAGE_CPU_WRITE;
 153
 154     if (usage & PIPE_TRANSFER_DONTBLOCK)
 155         res |= PB_USAGE_DONTBLOCK;
 156
 157     if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
 158         res |= PB_USAGE_UNSYNCHRONIZED;
 159
 160     return res;
 161 }
 162
 163 static void *radeon_bo_map_internal(struct pb_buffer *_buf,
 164                                     unsigned flags, void *flush_ctx)
 165 {
 166     struct radeon_bo *bo = radeon_bo(_buf);
 167     struct radeon_drm_cs *cs = flush_ctx;
 168     struct drm_radeon_gem_mmap args = {};
 169     void *ptr;
 170
 171     /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
 172     if (!(flags & PB_USAGE_UNSYNCHRONIZED)) {
 173         /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
 174         if (flags & PB_USAGE_DONTBLOCK) {
 175             if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 176                 cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
 177                 return NULL;
 178             }
 179
 180             if (radeon_bo_is_busy((struct pb_buffer*)bo)) {
 181                 return NULL;
 182             }
 183         } else {
 184             if (!(flags & PB_USAGE_CPU_WRITE)) {
 185                 /* Mapping for read.
 186                  *
 187                  * Since we are mapping for read, we don't need to wait
 188                  * if the GPU is using the buffer for read too
 189                  * (neither one is changing it).
 190                  *
 191                  * Only check whether the buffer is being used for write. */
 192                 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
 193                     cs->flush_cs(cs->flush_data, 0);
 194                     radeon_bo_wait((struct pb_buffer*)bo);
 195                 } else if (bo->busy_for_write) {
 196                     /* Update the busy_for_write field (done by radeon_bo_is_busy)
 197                      * and wait if needed. */
 198                     if (radeon_bo_is_busy((struct pb_buffer*)bo)) {
 199                         radeon_bo_wait((struct pb_buffer*)bo);
 200                     }
 201                 }
 202             } else {
 203                 /* Mapping for write. */
 204                 if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 205                     cs->flush_cs(cs->flush_data, 0);
 206                 } else {
 207                     /* Try to avoid busy-waiting in radeon_bo_wait. */
 208                     if (p_atomic_read(&bo->num_active_ioctls))
 209                         radeon_drm_cs_sync_flush(cs);
 210                 }
 211
 212                 radeon_bo_wait((struct pb_buffer*)bo);
 213             }
 214         }
 215     }
 216
 217     /* Return the pointer if it's already mapped. */
 218     if (bo->ptr)
 219         return bo->ptr;
 220
 221     /* Map the buffer. */
 222     pipe_mutex_lock(bo->map_mutex);
 223     /* Return the pointer if it's already mapped (in case of a race). */
 224     if (bo->ptr) {
 225         pipe_mutex_unlock(bo->map_mutex);
 226         return bo->ptr;
 227     }
 228     args.handle = bo->handle;
 229     args.offset = 0;
 230     args.size = (uint64_t)bo->size;
 231     if (drmCommandWriteRead(bo->rws->fd,
 232                             DRM_RADEON_GEM_MMAP,
 233                             &args,
 234                             sizeof(args))) {
 235         pipe_mutex_unlock(bo->map_mutex);
 236         fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
 237                 bo, bo->handle);
 238         return NULL;
 239     }
 240
 241     ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
 242                bo->rws->fd, args.addr_ptr);
 243     if (ptr == MAP_FAILED) {
 244         pipe_mutex_unlock(bo->map_mutex);
 245         fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
 246         return NULL;
 247     }
 248     bo->ptr = ptr;
 249     pipe_mutex_unlock(bo->map_mutex);
 250
 251     return bo->ptr;
 252 }
 253
 254 static void radeon_bo_unmap_internal(struct pb_buffer *_buf)
 255 {
 256     /* NOP */
 257 }
 258
 259 static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
 260                                       struct pb_buffer **base_buf,
 261                                       unsigned *offset)
 262 {
 263     *base_buf = buf;
 264     *offset = 0;
 265 }
 266
 267 static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
 268                                           struct pb_validate *vl,
 269                                           unsigned flags)
 270 {
 271     /* Always pinned */
 272     return PIPE_OK;
 273 }
 274
 275 static void radeon_bo_fence(struct pb_buffer *buf,
 276                             struct pipe_fence_handle *fence)
 277 {
 278 }
 279
 280 const struct pb_vtbl radeon_bo_vtbl = {
 281     radeon_bo_destroy,
 282     radeon_bo_map_internal,
 283     radeon_bo_unmap_internal,
 284     radeon_bo_validate,
 285     radeon_bo_fence,
 286     radeon_bo_get_base_buffer,
 287 };
 288
 289 static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
 290                                                 pb_size size,
 291                                                 const struct pb_desc *desc)
 292 {
 293     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 294     struct radeon_drm_winsys *rws = mgr->rws;
 295     struct radeon_bo *bo;
 296     struct drm_radeon_gem_create args = {};
 297
 298     args.size = size;
 299     args.alignment = desc->alignment;
 300     args.initial_domain =
 301         (desc->usage & RADEON_PB_USAGE_DOMAIN_GTT  ?
 302          RADEON_GEM_DOMAIN_GTT  : 0) |
 303         (desc->usage & RADEON_PB_USAGE_DOMAIN_VRAM ?
 304          RADEON_GEM_DOMAIN_VRAM : 0);
 305
 306     if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
 307                             &args, sizeof(args))) {
 308         fprintf(stderr, "radeon: Failed to allocate a buffer:\n");
 309         fprintf(stderr, "radeon:    size      : %d bytes\n", size);
 310         fprintf(stderr, "radeon:    alignment : %d bytes\n", desc->alignment);
 311         fprintf(stderr, "radeon:    domains   : %d\n", args.initial_domain);
 312         return NULL;
 313     }
 314
 315     bo = CALLOC_STRUCT(radeon_bo);
 316     if (!bo)
 317         return NULL;
 318
 319     pipe_reference_init(&bo->base.base.reference, 1);
 320     bo->base.base.alignment = desc->alignment;
 321     bo->base.base.usage = desc->usage;
 322     bo->base.base.size = size;
 323     bo->base.vtbl = &radeon_bo_vtbl;
 324     bo->mgr = mgr;
 325     bo->rws = mgr->rws;
 326     bo->handle = args.handle;
 327     bo->size = size;
 328     pipe_mutex_init(bo->map_mutex);
 329
 330     return &bo->base;
 331 }
 332
 333 static void radeon_bomgr_flush(struct pb_manager *mgr)
 334 {
 335     /* NOP */
 336 }
 337
 338 /* This is for the cache bufmgr. */
 339 static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr,
 340                                            struct pb_buffer *_buf)
 341 {
 342    struct radeon_bo *bo = radeon_bo(_buf);
 343
 344    if (radeon_bo_is_referenced_by_any_cs(bo)) {
 345        return TRUE;
 346    }
 347
 348    if (radeon_bo_is_busy((struct pb_buffer*)bo)) {
 349        return TRUE;
 350    }
 351
 352    return FALSE;
 353 }
 354
 355 static void radeon_bomgr_destroy(struct pb_manager *_mgr)
 356 {
 357     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 358     util_hash_table_destroy(mgr->bo_handles);
 359     pipe_mutex_destroy(mgr->bo_handles_mutex);
 360     FREE(mgr);
 361 }
 362
 363 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 364
 365 static unsigned handle_hash(void *key)
 366 {
 367     return PTR_TO_UINT(key);
 368 }
 369
 370 static int handle_compare(void *key1, void *key2)
 371 {
 372     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 373 }
 374
 375 struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
 376 {
 377     struct radeon_bomgr *mgr;
 378
 379     mgr = CALLOC_STRUCT(radeon_bomgr);
 380     if (!mgr)
 381         return NULL;
 382
 383     mgr->base.destroy = radeon_bomgr_destroy;
 384     mgr->base.create_buffer = radeon_bomgr_create_bo;
 385     mgr->base.flush = radeon_bomgr_flush;
 386     mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
 387
 388     mgr->rws = rws;
 389     mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 390     pipe_mutex_init(mgr->bo_handles_mutex);
 391     return &mgr->base;
 392 }
 393
 394 static void *radeon_bo_map(struct pb_buffer *buf,
 395                            struct radeon_winsys_cs *cs,
 396                            enum pipe_transfer_usage usage)
 397 {
 398     return pb_map(buf, get_pb_usage_from_transfer_flags(usage), cs);
 399 }
 400
 401 static void radeon_bo_get_tiling(struct pb_buffer *_buf,
 402                                  enum radeon_bo_layout *microtiled,
 403                                  enum radeon_bo_layout *macrotiled)
 404 {
 405     struct radeon_bo *bo = get_radeon_bo(_buf);
 406     struct drm_radeon_gem_set_tiling args = {};
 407
 408     args.handle = bo->handle;
 409
 410     drmCommandWriteRead(bo->rws->fd,
 411                         DRM_RADEON_GEM_GET_TILING,
 412                         &args,
 413                         sizeof(args));
 414
 415     *microtiled = RADEON_LAYOUT_LINEAR;
 416     *macrotiled = RADEON_LAYOUT_LINEAR;
 417     if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE)
 418         *microtiled = RADEON_LAYOUT_TILED;
 419
 420     if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE)
 421         *macrotiled = RADEON_LAYOUT_TILED;
 422 }
 423
 424 static void radeon_bo_set_tiling(struct pb_buffer *_buf,
 425                                  struct radeon_winsys_cs *rcs,
 426                                  enum radeon_bo_layout microtiled,
 427                                  enum radeon_bo_layout macrotiled,
 428                                  uint32_t pitch)
 429 {
 430     struct radeon_bo *bo = get_radeon_bo(_buf);
 431     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 432     struct drm_radeon_gem_set_tiling args = {};
 433
 434     /* Tiling determines how DRM treats the buffer data.
 435      * We must flush CS when changing it if the buffer is referenced. */
 436     if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
 437         cs->flush_cs(cs->flush_data, 0);
 438     }
 439
 440     while (p_atomic_read(&bo->num_active_ioctls)) {
 441         sched_yield();
 442     }
 443
 444     if (microtiled == RADEON_LAYOUT_TILED)
 445         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE;
 446     else if (microtiled == RADEON_LAYOUT_SQUARETILED)
 447         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
 448
 449     if (macrotiled == RADEON_LAYOUT_TILED)
 450         args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
 451
 452     args.handle = bo->handle;
 453     args.pitch = pitch;
 454
 455     drmCommandWriteRead(bo->rws->fd,
 456                         DRM_RADEON_GEM_SET_TILING,
 457                         &args,
 458                         sizeof(args));
 459 }
 460
 461 static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle(
 462         struct pb_buffer *_buf)
 463 {
 464     /* return radeon_bo. */
 465     return (struct radeon_winsys_cs_handle*)get_radeon_bo(_buf);
 466 }
 467
 468 static unsigned get_pb_usage_from_create_flags(enum radeon_bo_domain domain)
 469 {
 470     unsigned res = 0;
 471
 472     if (domain & RADEON_DOMAIN_GTT)
 473         res |= RADEON_PB_USAGE_DOMAIN_GTT;
 474
 475     if (domain & RADEON_DOMAIN_VRAM)
 476         res |= RADEON_PB_USAGE_DOMAIN_VRAM;
 477
 478     return res;
 479 }
 480
 481 static struct pb_buffer *
 482 radeon_winsys_bo_create(struct radeon_winsys *rws,
 483                         unsigned size,
 484                         unsigned alignment,
 485                         unsigned bind,
 486                         enum radeon_bo_domain domain)
 487 {
 488     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 489     struct pb_desc desc;
 490     struct pb_manager *provider;
 491     struct pb_buffer *buffer;
 492
 493     memset(&desc, 0, sizeof(desc));
 494     desc.alignment = alignment;
 495     desc.usage = get_pb_usage_from_create_flags(domain);
 496
 497     /* Assign a buffer manager. */
 498     if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 499                 PIPE_BIND_CONSTANT_BUFFER))
 500         provider = ws->cman;
 501     else
 502         provider = ws->kman;
 503
 504     buffer = provider->create_buffer(provider, size, &desc);
 505     if (!buffer)
 506         return NULL;
 507
 508     return (struct pb_buffer*)buffer;
 509 }
 510
 511 static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
 512                                                            struct winsys_handle *whandle,
 513                                                            unsigned *stride,
 514                                                            unsigned *size)
 515 {
 516     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 517     struct radeon_bo *bo;
 518     struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
 519     struct drm_gem_open open_arg = {};
 520
 521     /* We must maintain a list of pairs <handle, bo>, so that we always return
 522      * the same BO for one particular handle. If we didn't do that and created
 523      * more than one BO for the same handle and then relocated them in a CS,
 524      * we would hit a deadlock in the kernel.
 525      *
 526      * The list of pairs is guarded by a mutex, of course. */
 527     pipe_mutex_lock(mgr->bo_handles_mutex);
 528
 529     /* First check if there already is an existing bo for the handle. */
 530     bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
 531     if (bo) {
 532         /* Increase the refcount. */
 533         struct pb_buffer *b = NULL;
 534         pb_reference(&b, &bo->base);
 535         goto done;
 536     }
 537
 538     /* There isn't, create a new one. */
 539     bo = CALLOC_STRUCT(radeon_bo);
 540     if (!bo) {
 541         goto fail;
 542     }
 543
 544     /* Open the BO. */
 545     open_arg.name = whandle->handle;
 546     if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
 547         FREE(bo);
 548         goto fail;
 549     }
 550     bo->handle = open_arg.handle;
 551     bo->size = open_arg.size;
 552     bo->name = whandle->handle;
 553
 554     /* Initialize it. */
 555     pipe_reference_init(&bo->base.base.reference, 1);
 556     bo->base.base.alignment = 0;
 557     bo->base.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
 558     bo->base.base.size = bo->size;
 559     bo->base.vtbl = &radeon_bo_vtbl;
 560     bo->mgr = mgr;
 561     bo->rws = mgr->rws;
 562     pipe_mutex_init(bo->map_mutex);
 563
 564     util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
 565
 566 done:
 567     pipe_mutex_unlock(mgr->bo_handles_mutex);
 568
 569     if (stride)
 570         *stride = whandle->stride;
 571     if (size)
 572         *size = bo->base.base.size;
 573
 574     return (struct pb_buffer*)bo;
 575
 576 fail:
 577     pipe_mutex_unlock(mgr->bo_handles_mutex);
 578     return NULL;
 579 }
 580
 581 static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer,
 582                                            unsigned stride,
 583                                            struct winsys_handle *whandle)
 584 {
 585     struct drm_gem_flink flink = {};
 586     struct radeon_bo *bo = get_radeon_bo(buffer);
 587
 588     if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 589         if (!bo->flinked) {
 590             flink.handle = bo->handle;
 591
 592             if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
 593                 return FALSE;
 594             }
 595
 596             bo->flinked = TRUE;
 597             bo->flink = flink.name;
 598         }
 599         whandle->handle = bo->flink;
 600     } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 601         whandle->handle = bo->handle;
 602     }
 603
 604     whandle->stride = stride;
 605     return TRUE;
 606 }
 607
 608 void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws)
 609 {
 610     ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle;
 611     ws->base.buffer_set_tiling = radeon_bo_set_tiling;
 612     ws->base.buffer_get_tiling = radeon_bo_get_tiling;
 613     ws->base.buffer_map = radeon_bo_map;
 614     ws->base.buffer_unmap = pb_unmap;
 615     ws->base.buffer_wait = radeon_bo_wait;
 616     ws->base.buffer_is_busy = radeon_bo_is_busy;
 617     ws->base.buffer_create = radeon_winsys_bo_create;
 618     ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
 619     ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;
 620 }