2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
27 #include "radeon_drm_cs.h"
29 #include "util/u_hash_table.h"
30 #include "util/u_memory.h"
31 #include "util/simple_list.h"
32 #include "os/os_thread.h"
33 #include "os/os_mman.h"
34 #include "os/os_time.h"
36 #include "state_tracker/drm_driver.h"
38 #include <sys/ioctl.h>
45 static inline struct radeon_bo
*radeon_bo(struct pb_buffer
*bo
)
47 return (struct radeon_bo
*)bo
;
50 struct radeon_bo_va_hole
{
51 struct list_head list
;
56 static bool radeon_bo_is_busy(struct radeon_bo
*bo
)
58 struct drm_radeon_gem_busy args
= {0};
60 args
.handle
= bo
->handle
;
61 return drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_BUSY
,
62 &args
, sizeof(args
)) != 0;
65 static void radeon_bo_wait_idle(struct radeon_bo
*bo
)
67 struct drm_radeon_gem_wait_idle args
= {0};
69 args
.handle
= bo
->handle
;
70 while (drmCommandWrite(bo
->rws
->fd
, DRM_RADEON_GEM_WAIT_IDLE
,
71 &args
, sizeof(args
)) == -EBUSY
);
74 static bool radeon_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
75 enum radeon_bo_usage usage
)
77 struct radeon_bo
*bo
= radeon_bo(_buf
);
80 /* No timeout. Just query. */
82 return !bo
->num_active_ioctls
&& !radeon_bo_is_busy(bo
);
84 abs_timeout
= os_time_get_absolute_timeout(timeout
);
86 /* Wait if any ioctl is being submitted with this buffer. */
87 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
90 /* Infinite timeout. */
91 if (abs_timeout
== PIPE_TIMEOUT_INFINITE
) {
92 radeon_bo_wait_idle(bo
);
96 /* Other timeouts need to be emulated with a loop. */
97 while (radeon_bo_is_busy(bo
)) {
98 if (os_time_get_nano() >= abs_timeout
)
106 static enum radeon_bo_domain
get_valid_domain(enum radeon_bo_domain domain
)
108 /* Zero domains the driver doesn't understand. */
109 domain
&= RADEON_DOMAIN_VRAM_GTT
;
111 /* If no domain is set, we must set something... */
113 domain
= RADEON_DOMAIN_VRAM_GTT
;
118 static enum radeon_bo_domain
radeon_bo_get_initial_domain(
119 struct pb_buffer
*buf
)
121 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
122 struct drm_radeon_gem_op args
;
124 if (bo
->rws
->info
.drm_minor
< 38)
125 return RADEON_DOMAIN_VRAM_GTT
;
127 memset(&args
, 0, sizeof(args
));
128 args
.handle
= bo
->handle
;
129 args
.op
= RADEON_GEM_OP_GET_INITIAL_DOMAIN
;
131 drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_OP
,
132 &args
, sizeof(args
));
134 /* GEM domains and winsys domains are defined the same. */
135 return get_valid_domain(args
.value
);
138 static uint64_t radeon_bomgr_find_va(struct radeon_drm_winsys
*rws
,
139 uint64_t size
, uint64_t alignment
)
141 struct radeon_bo_va_hole
*hole
, *n
;
142 uint64_t offset
= 0, waste
= 0;
144 /* All VM address space holes will implicitly start aligned to the
145 * size alignment, so we don't need to sanitize the alignment here
147 size
= align(size
, rws
->info
.gart_page_size
);
149 pipe_mutex_lock(rws
->bo_va_mutex
);
150 /* first look for a hole */
151 LIST_FOR_EACH_ENTRY_SAFE(hole
, n
, &rws
->va_holes
, list
) {
152 offset
= hole
->offset
;
153 waste
= offset
% alignment
;
154 waste
= waste
? alignment
- waste
: 0;
156 if (offset
>= (hole
->offset
+ hole
->size
)) {
159 if (!waste
&& hole
->size
== size
) {
160 offset
= hole
->offset
;
161 list_del(&hole
->list
);
163 pipe_mutex_unlock(rws
->bo_va_mutex
);
166 if ((hole
->size
- waste
) > size
) {
168 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
170 n
->offset
= hole
->offset
;
171 list_add(&n
->list
, &hole
->list
);
173 hole
->size
-= (size
+ waste
);
174 hole
->offset
+= size
+ waste
;
175 pipe_mutex_unlock(rws
->bo_va_mutex
);
178 if ((hole
->size
- waste
) == size
) {
180 pipe_mutex_unlock(rws
->bo_va_mutex
);
185 offset
= rws
->va_offset
;
186 waste
= offset
% alignment
;
187 waste
= waste
? alignment
- waste
: 0;
189 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
192 list_add(&n
->list
, &rws
->va_holes
);
195 rws
->va_offset
+= size
+ waste
;
196 pipe_mutex_unlock(rws
->bo_va_mutex
);
200 static void radeon_bomgr_free_va(struct radeon_drm_winsys
*rws
,
201 uint64_t va
, uint64_t size
)
203 struct radeon_bo_va_hole
*hole
;
205 size
= align(size
, rws
->info
.gart_page_size
);
207 pipe_mutex_lock(rws
->bo_va_mutex
);
208 if ((va
+ size
) == rws
->va_offset
) {
210 /* Delete uppermost hole if it reaches the new top */
211 if (!LIST_IS_EMPTY(&rws
->va_holes
)) {
212 hole
= container_of(rws
->va_holes
.next
, hole
, list
);
213 if ((hole
->offset
+ hole
->size
) == va
) {
214 rws
->va_offset
= hole
->offset
;
215 list_del(&hole
->list
);
220 struct radeon_bo_va_hole
*next
;
222 hole
= container_of(&rws
->va_holes
, hole
, list
);
223 LIST_FOR_EACH_ENTRY(next
, &rws
->va_holes
, list
) {
224 if (next
->offset
< va
)
229 if (&hole
->list
!= &rws
->va_holes
) {
230 /* Grow upper hole if it's adjacent */
231 if (hole
->offset
== (va
+ size
)) {
234 /* Merge lower hole if it's adjacent */
235 if (next
!= hole
&& &next
->list
!= &rws
->va_holes
&&
236 (next
->offset
+ next
->size
) == va
) {
237 next
->size
+= hole
->size
;
238 list_del(&hole
->list
);
245 /* Grow lower hole if it's adjacent */
246 if (next
!= hole
&& &next
->list
!= &rws
->va_holes
&&
247 (next
->offset
+ next
->size
) == va
) {
252 /* FIXME on allocation failure we just lose virtual address space
253 * maybe print a warning
255 next
= CALLOC_STRUCT(radeon_bo_va_hole
);
259 list_add(&next
->list
, &hole
->list
);
263 pipe_mutex_unlock(rws
->bo_va_mutex
);
266 void radeon_bo_destroy(struct pb_buffer
*_buf
)
268 struct radeon_bo
*bo
= radeon_bo(_buf
);
269 struct radeon_drm_winsys
*rws
= bo
->rws
;
270 struct drm_gem_close args
;
272 memset(&args
, 0, sizeof(args
));
274 pipe_mutex_lock(rws
->bo_handles_mutex
);
275 util_hash_table_remove(rws
->bo_handles
, (void*)(uintptr_t)bo
->handle
);
276 if (bo
->flink_name
) {
277 util_hash_table_remove(rws
->bo_names
,
278 (void*)(uintptr_t)bo
->flink_name
);
280 pipe_mutex_unlock(rws
->bo_handles_mutex
);
283 os_munmap(bo
->ptr
, bo
->base
.size
);
285 if (rws
->info
.has_virtual_memory
) {
286 if (rws
->va_unmap_working
) {
287 struct drm_radeon_gem_va va
;
289 va
.handle
= bo
->handle
;
291 va
.operation
= RADEON_VA_UNMAP
;
292 va
.flags
= RADEON_VM_PAGE_READABLE
|
293 RADEON_VM_PAGE_WRITEABLE
|
294 RADEON_VM_PAGE_SNOOPED
;
297 if (drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_VA
, &va
,
299 va
.operation
== RADEON_VA_RESULT_ERROR
) {
300 fprintf(stderr
, "radeon: Failed to deallocate virtual address for buffer:\n");
301 fprintf(stderr
, "radeon: size : %"PRIu64
" bytes\n", bo
->base
.size
);
302 fprintf(stderr
, "radeon: va : 0x%"PRIx64
"\n", bo
->va
);
306 radeon_bomgr_free_va(rws
, bo
->va
, bo
->base
.size
);
310 args
.handle
= bo
->handle
;
311 drmIoctl(rws
->fd
, DRM_IOCTL_GEM_CLOSE
, &args
);
313 pipe_mutex_destroy(bo
->map_mutex
);
315 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
316 rws
->allocated_vram
-= align(bo
->base
.size
, rws
->info
.gart_page_size
);
317 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
318 rws
->allocated_gtt
-= align(bo
->base
.size
, rws
->info
.gart_page_size
);
322 static void radeon_bo_destroy_or_cache(struct pb_buffer
*_buf
)
324 struct radeon_bo
*bo
= radeon_bo(_buf
);
326 if (bo
->use_reusable_pool
)
327 pb_cache_add_buffer(&bo
->cache_entry
);
329 radeon_bo_destroy(_buf
);
332 void *radeon_bo_do_map(struct radeon_bo
*bo
)
334 struct drm_radeon_gem_mmap args
= {0};
337 /* If the buffer is created from user memory, return the user pointer. */
341 /* Map the buffer. */
342 pipe_mutex_lock(bo
->map_mutex
);
343 /* Return the pointer if it's already mapped. */
346 pipe_mutex_unlock(bo
->map_mutex
);
349 args
.handle
= bo
->handle
;
351 args
.size
= (uint64_t)bo
->base
.size
;
352 if (drmCommandWriteRead(bo
->rws
->fd
,
356 pipe_mutex_unlock(bo
->map_mutex
);
357 fprintf(stderr
, "radeon: gem_mmap failed: %p 0x%08X\n",
362 ptr
= os_mmap(0, args
.size
, PROT_READ
|PROT_WRITE
, MAP_SHARED
,
363 bo
->rws
->fd
, args
.addr_ptr
);
364 if (ptr
== MAP_FAILED
) {
365 /* Clear the cache and try again. */
366 pb_cache_release_all_buffers(&bo
->rws
->bo_cache
);
368 ptr
= os_mmap(0, args
.size
, PROT_READ
|PROT_WRITE
, MAP_SHARED
,
369 bo
->rws
->fd
, args
.addr_ptr
);
370 if (ptr
== MAP_FAILED
) {
371 pipe_mutex_unlock(bo
->map_mutex
);
372 fprintf(stderr
, "radeon: mmap failed, errno: %i\n", errno
);
379 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
380 bo
->rws
->mapped_vram
+= bo
->base
.size
;
382 bo
->rws
->mapped_gtt
+= bo
->base
.size
;
384 pipe_mutex_unlock(bo
->map_mutex
);
388 static void *radeon_bo_map(struct pb_buffer
*buf
,
389 struct radeon_winsys_cs
*rcs
,
390 enum pipe_transfer_usage usage
)
392 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
393 struct radeon_drm_cs
*cs
= (struct radeon_drm_cs
*)rcs
;
395 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
396 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
397 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
398 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
399 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
402 * Since we are mapping for read, we don't need to wait
403 * if the GPU is using the buffer for read too
404 * (neither one is changing it).
406 * Only check whether the buffer is being used for write. */
407 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
408 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
412 if (!radeon_bo_wait((struct pb_buffer
*)bo
, 0,
413 RADEON_USAGE_WRITE
)) {
417 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
418 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
422 if (!radeon_bo_wait((struct pb_buffer
*)bo
, 0,
423 RADEON_USAGE_READWRITE
)) {
428 uint64_t time
= os_time_get_nano();
430 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
433 * Since we are mapping for read, we don't need to wait
434 * if the GPU is using the buffer for read too
435 * (neither one is changing it).
437 * Only check whether the buffer is being used for write. */
438 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
439 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
441 radeon_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
444 /* Mapping for write. */
446 if (radeon_bo_is_referenced_by_cs(cs
, bo
)) {
447 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
449 /* Try to avoid busy-waiting in radeon_bo_wait. */
450 if (p_atomic_read(&bo
->num_active_ioctls
))
451 radeon_drm_cs_sync_flush(rcs
);
455 radeon_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
456 RADEON_USAGE_READWRITE
);
459 bo
->rws
->buffer_wait_time
+= os_time_get_nano() - time
;
463 return radeon_bo_do_map(bo
);
466 static void radeon_bo_unmap(struct pb_buffer
*_buf
)
468 struct radeon_bo
*bo
= (struct radeon_bo
*)_buf
;
473 pipe_mutex_lock(bo
->map_mutex
);
475 pipe_mutex_unlock(bo
->map_mutex
);
476 return; /* it's not been mapped */
479 assert(bo
->map_count
);
480 if (--bo
->map_count
) {
481 pipe_mutex_unlock(bo
->map_mutex
);
482 return; /* it's been mapped multiple times */
485 os_munmap(bo
->ptr
, bo
->base
.size
);
488 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
489 bo
->rws
->mapped_vram
-= bo
->base
.size
;
491 bo
->rws
->mapped_gtt
-= bo
->base
.size
;
493 pipe_mutex_unlock(bo
->map_mutex
);
496 static const struct pb_vtbl radeon_bo_vtbl
= {
497 radeon_bo_destroy_or_cache
498 /* other functions are never called */
501 #ifndef RADEON_GEM_GTT_WC
502 #define RADEON_GEM_GTT_WC (1 << 2)
504 #ifndef RADEON_GEM_CPU_ACCESS
505 /* BO is expected to be accessed by the CPU */
506 #define RADEON_GEM_CPU_ACCESS (1 << 3)
508 #ifndef RADEON_GEM_NO_CPU_ACCESS
509 /* CPU access is not expected to work for this BO */
510 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
513 static struct radeon_bo
*radeon_create_bo(struct radeon_drm_winsys
*rws
,
514 unsigned size
, unsigned alignment
,
516 unsigned initial_domains
,
518 unsigned pb_cache_bucket
)
520 struct radeon_bo
*bo
;
521 struct drm_radeon_gem_create args
;
524 memset(&args
, 0, sizeof(args
));
526 assert(initial_domains
);
527 assert((initial_domains
&
528 ~(RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
)) == 0);
531 args
.alignment
= alignment
;
532 args
.initial_domain
= initial_domains
;
535 if (flags
& RADEON_FLAG_GTT_WC
)
536 args
.flags
|= RADEON_GEM_GTT_WC
;
537 if (flags
& RADEON_FLAG_CPU_ACCESS
)
538 args
.flags
|= RADEON_GEM_CPU_ACCESS
;
539 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
540 args
.flags
|= RADEON_GEM_NO_CPU_ACCESS
;
542 if (drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_CREATE
,
543 &args
, sizeof(args
))) {
544 fprintf(stderr
, "radeon: Failed to allocate a buffer:\n");
545 fprintf(stderr
, "radeon: size : %u bytes\n", size
);
546 fprintf(stderr
, "radeon: alignment : %u bytes\n", alignment
);
547 fprintf(stderr
, "radeon: domains : %u\n", args
.initial_domain
);
548 fprintf(stderr
, "radeon: flags : %u\n", args
.flags
);
552 bo
= CALLOC_STRUCT(radeon_bo
);
556 pipe_reference_init(&bo
->base
.reference
, 1);
557 bo
->base
.alignment
= alignment
;
558 bo
->base
.usage
= usage
;
559 bo
->base
.size
= size
;
560 bo
->base
.vtbl
= &radeon_bo_vtbl
;
562 bo
->handle
= args
.handle
;
564 bo
->initial_domain
= initial_domains
;
565 pipe_mutex_init(bo
->map_mutex
);
566 pb_cache_init_entry(&rws
->bo_cache
, &bo
->cache_entry
, &bo
->base
,
569 if (rws
->info
.has_virtual_memory
) {
570 struct drm_radeon_gem_va va
;
571 unsigned va_gap_size
;
573 va_gap_size
= rws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
574 bo
->va
= radeon_bomgr_find_va(rws
, size
+ va_gap_size
, alignment
);
576 va
.handle
= bo
->handle
;
578 va
.operation
= RADEON_VA_MAP
;
579 va
.flags
= RADEON_VM_PAGE_READABLE
|
580 RADEON_VM_PAGE_WRITEABLE
|
581 RADEON_VM_PAGE_SNOOPED
;
583 r
= drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
584 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
585 fprintf(stderr
, "radeon: Failed to allocate virtual address for buffer:\n");
586 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
587 fprintf(stderr
, "radeon: alignment : %d bytes\n", alignment
);
588 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
589 fprintf(stderr
, "radeon: va : 0x%016llx\n", (unsigned long long)bo
->va
);
590 radeon_bo_destroy(&bo
->base
);
593 pipe_mutex_lock(rws
->bo_handles_mutex
);
594 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
595 struct pb_buffer
*b
= &bo
->base
;
596 struct radeon_bo
*old_bo
=
597 util_hash_table_get(rws
->bo_vas
, (void*)(uintptr_t)va
.offset
);
599 pipe_mutex_unlock(rws
->bo_handles_mutex
);
600 pb_reference(&b
, &old_bo
->base
);
604 util_hash_table_set(rws
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
605 pipe_mutex_unlock(rws
->bo_handles_mutex
);
608 if (initial_domains
& RADEON_DOMAIN_VRAM
)
609 rws
->allocated_vram
+= align(size
, rws
->info
.gart_page_size
);
610 else if (initial_domains
& RADEON_DOMAIN_GTT
)
611 rws
->allocated_gtt
+= align(size
, rws
->info
.gart_page_size
);
616 bool radeon_bo_can_reclaim(struct pb_buffer
*_buf
)
618 struct radeon_bo
*bo
= radeon_bo(_buf
);
620 if (radeon_bo_is_referenced_by_any_cs(bo
))
623 return radeon_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
626 static unsigned eg_tile_split(unsigned tile_split
)
628 switch (tile_split
) {
629 case 0: tile_split
= 64; break;
630 case 1: tile_split
= 128; break;
631 case 2: tile_split
= 256; break;
632 case 3: tile_split
= 512; break;
634 case 4: tile_split
= 1024; break;
635 case 5: tile_split
= 2048; break;
636 case 6: tile_split
= 4096; break;
641 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
643 switch (eg_tile_split
) {
655 static void radeon_bo_get_metadata(struct pb_buffer
*_buf
,
656 struct radeon_bo_metadata
*md
)
658 struct radeon_bo
*bo
= radeon_bo(_buf
);
659 struct drm_radeon_gem_set_tiling args
;
661 memset(&args
, 0, sizeof(args
));
663 args
.handle
= bo
->handle
;
665 drmCommandWriteRead(bo
->rws
->fd
,
666 DRM_RADEON_GEM_GET_TILING
,
670 md
->microtile
= RADEON_LAYOUT_LINEAR
;
671 md
->macrotile
= RADEON_LAYOUT_LINEAR
;
672 if (args
.tiling_flags
& RADEON_TILING_MICRO
)
673 md
->microtile
= RADEON_LAYOUT_TILED
;
674 else if (args
.tiling_flags
& RADEON_TILING_MICRO_SQUARE
)
675 md
->microtile
= RADEON_LAYOUT_SQUARETILED
;
677 if (args
.tiling_flags
& RADEON_TILING_MACRO
)
678 md
->macrotile
= RADEON_LAYOUT_TILED
;
680 md
->bankw
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
681 md
->bankh
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
682 md
->tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
683 md
->mtilea
= (args
.tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
684 md
->tile_split
= eg_tile_split(md
->tile_split
);
685 md
->scanout
= bo
->rws
->gen
>= DRV_SI
&& !(args
.tiling_flags
& RADEON_TILING_R600_NO_SCANOUT
);
688 static void radeon_bo_set_metadata(struct pb_buffer
*_buf
,
689 struct radeon_bo_metadata
*md
)
691 struct radeon_bo
*bo
= radeon_bo(_buf
);
692 struct drm_radeon_gem_set_tiling args
;
694 memset(&args
, 0, sizeof(args
));
696 os_wait_until_zero(&bo
->num_active_ioctls
, PIPE_TIMEOUT_INFINITE
);
698 if (md
->microtile
== RADEON_LAYOUT_TILED
)
699 args
.tiling_flags
|= RADEON_TILING_MICRO
;
700 else if (md
->microtile
== RADEON_LAYOUT_SQUARETILED
)
701 args
.tiling_flags
|= RADEON_TILING_MICRO_SQUARE
;
703 if (md
->macrotile
== RADEON_LAYOUT_TILED
)
704 args
.tiling_flags
|= RADEON_TILING_MACRO
;
706 args
.tiling_flags
|= (md
->bankw
& RADEON_TILING_EG_BANKW_MASK
) <<
707 RADEON_TILING_EG_BANKW_SHIFT
;
708 args
.tiling_flags
|= (md
->bankh
& RADEON_TILING_EG_BANKH_MASK
) <<
709 RADEON_TILING_EG_BANKH_SHIFT
;
710 if (md
->tile_split
) {
711 args
.tiling_flags
|= (eg_tile_split_rev(md
->tile_split
) &
712 RADEON_TILING_EG_TILE_SPLIT_MASK
) <<
713 RADEON_TILING_EG_TILE_SPLIT_SHIFT
;
715 args
.tiling_flags
|= (md
->mtilea
& RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
) <<
716 RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
;
718 if (bo
->rws
->gen
>= DRV_SI
&& !md
->scanout
)
719 args
.tiling_flags
|= RADEON_TILING_R600_NO_SCANOUT
;
721 args
.handle
= bo
->handle
;
722 args
.pitch
= md
->stride
;
724 drmCommandWriteRead(bo
->rws
->fd
,
725 DRM_RADEON_GEM_SET_TILING
,
730 static struct pb_buffer
*
731 radeon_winsys_bo_create(struct radeon_winsys
*rws
,
734 enum radeon_bo_domain domain
,
735 enum radeon_bo_flag flags
)
737 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
738 struct radeon_bo
*bo
;
739 unsigned usage
= 0, pb_cache_bucket
;
741 /* Only 32-bit sizes are supported. */
745 /* Align size to page size. This is the minimum alignment for normal
746 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
747 * like constant/uniform buffers, can benefit from better and more reuse.
749 size
= align(size
, ws
->info
.gart_page_size
);
750 alignment
= align(alignment
, ws
->info
.gart_page_size
);
752 /* Only set one usage bit each for domains and flags, or the cache manager
753 * might consider different sets of domains / flags compatible
755 if (domain
== RADEON_DOMAIN_VRAM_GTT
)
758 usage
= (unsigned)domain
>> 1;
759 assert(flags
< sizeof(usage
) * 8 - 3);
760 usage
|= 1 << (flags
+ 3);
762 /* Determine the pb_cache bucket for minimizing pb_cache misses. */
764 if (size
<= 4096) /* small buffers */
765 pb_cache_bucket
+= 1;
766 if (domain
& RADEON_DOMAIN_VRAM
) /* VRAM or VRAM+GTT */
767 pb_cache_bucket
+= 2;
768 if (flags
== RADEON_FLAG_GTT_WC
) /* WC */
769 pb_cache_bucket
+= 4;
770 assert(pb_cache_bucket
< ARRAY_SIZE(ws
->bo_cache
.buckets
));
772 bo
= radeon_bo(pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
,
773 usage
, pb_cache_bucket
));
777 bo
= radeon_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
780 /* Clear the cache and try again. */
781 pb_cache_release_all_buffers(&ws
->bo_cache
);
782 bo
= radeon_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
788 bo
->use_reusable_pool
= true;
790 pipe_mutex_lock(ws
->bo_handles_mutex
);
791 util_hash_table_set(ws
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
792 pipe_mutex_unlock(ws
->bo_handles_mutex
);
797 static struct pb_buffer
*radeon_winsys_bo_from_ptr(struct radeon_winsys
*rws
,
798 void *pointer
, uint64_t size
)
800 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
801 struct drm_radeon_gem_userptr args
;
802 struct radeon_bo
*bo
;
805 bo
= CALLOC_STRUCT(radeon_bo
);
809 memset(&args
, 0, sizeof(args
));
810 args
.addr
= (uintptr_t)pointer
;
811 args
.size
= align(size
, ws
->info
.gart_page_size
);
812 args
.flags
= RADEON_GEM_USERPTR_ANONONLY
|
813 RADEON_GEM_USERPTR_VALIDATE
|
814 RADEON_GEM_USERPTR_REGISTER
;
815 if (drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_USERPTR
,
816 &args
, sizeof(args
))) {
821 pipe_mutex_lock(ws
->bo_handles_mutex
);
824 pipe_reference_init(&bo
->base
.reference
, 1);
825 bo
->handle
= args
.handle
;
826 bo
->base
.alignment
= 0;
827 bo
->base
.size
= size
;
828 bo
->base
.vtbl
= &radeon_bo_vtbl
;
830 bo
->user_ptr
= pointer
;
832 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
833 pipe_mutex_init(bo
->map_mutex
);
835 util_hash_table_set(ws
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
837 pipe_mutex_unlock(ws
->bo_handles_mutex
);
839 if (ws
->info
.has_virtual_memory
) {
840 struct drm_radeon_gem_va va
;
842 bo
->va
= radeon_bomgr_find_va(ws
, bo
->base
.size
, 1 << 20);
844 va
.handle
= bo
->handle
;
845 va
.operation
= RADEON_VA_MAP
;
848 va
.flags
= RADEON_VM_PAGE_READABLE
|
849 RADEON_VM_PAGE_WRITEABLE
|
850 RADEON_VM_PAGE_SNOOPED
;
852 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
853 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
854 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
855 radeon_bo_destroy(&bo
->base
);
858 pipe_mutex_lock(ws
->bo_handles_mutex
);
859 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
860 struct pb_buffer
*b
= &bo
->base
;
861 struct radeon_bo
*old_bo
=
862 util_hash_table_get(ws
->bo_vas
, (void*)(uintptr_t)va
.offset
);
864 pipe_mutex_unlock(ws
->bo_handles_mutex
);
865 pb_reference(&b
, &old_bo
->base
);
869 util_hash_table_set(ws
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
870 pipe_mutex_unlock(ws
->bo_handles_mutex
);
873 ws
->allocated_gtt
+= align(bo
->base
.size
, ws
->info
.gart_page_size
);
875 return (struct pb_buffer
*)bo
;
878 static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys
*rws
,
879 struct winsys_handle
*whandle
,
883 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
884 struct radeon_bo
*bo
;
889 if (!offset
&& whandle
->offset
!= 0) {
890 fprintf(stderr
, "attempt to import unsupported winsys offset %u\n",
895 /* We must maintain a list of pairs <handle, bo>, so that we always return
896 * the same BO for one particular handle. If we didn't do that and created
897 * more than one BO for the same handle and then relocated them in a CS,
898 * we would hit a deadlock in the kernel.
900 * The list of pairs is guarded by a mutex, of course. */
901 pipe_mutex_lock(ws
->bo_handles_mutex
);
903 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
904 /* First check if there already is an existing bo for the handle. */
905 bo
= util_hash_table_get(ws
->bo_names
, (void*)(uintptr_t)whandle
->handle
);
906 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
907 /* We must first get the GEM handle, as fds are unreliable keys */
908 r
= drmPrimeFDToHandle(ws
->fd
, whandle
->handle
, &handle
);
911 bo
= util_hash_table_get(ws
->bo_handles
, (void*)(uintptr_t)handle
);
913 /* Unknown handle type */
918 /* Increase the refcount. */
919 struct pb_buffer
*b
= NULL
;
920 pb_reference(&b
, &bo
->base
);
924 /* There isn't, create a new one. */
925 bo
= CALLOC_STRUCT(radeon_bo
);
930 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
931 struct drm_gem_open open_arg
= {};
932 memset(&open_arg
, 0, sizeof(open_arg
));
934 open_arg
.name
= whandle
->handle
;
935 if (drmIoctl(ws
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
)) {
939 handle
= open_arg
.handle
;
940 size
= open_arg
.size
;
941 bo
->flink_name
= whandle
->handle
;
942 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
943 size
= lseek(whandle
->handle
, 0, SEEK_END
);
945 * Could check errno to determine whether the kernel is new enough, but
946 * it doesn't really matter why this failed, just that it failed.
948 if (size
== (off_t
)-1) {
952 lseek(whandle
->handle
, 0, SEEK_SET
);
958 pipe_reference_init(&bo
->base
.reference
, 1);
959 bo
->base
.alignment
= 0;
960 bo
->base
.size
= (unsigned) size
;
961 bo
->base
.vtbl
= &radeon_bo_vtbl
;
964 pipe_mutex_init(bo
->map_mutex
);
967 util_hash_table_set(ws
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
969 util_hash_table_set(ws
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
972 pipe_mutex_unlock(ws
->bo_handles_mutex
);
975 *stride
= whandle
->stride
;
977 *offset
= whandle
->offset
;
979 if (ws
->info
.has_virtual_memory
&& !bo
->va
) {
980 struct drm_radeon_gem_va va
;
982 bo
->va
= radeon_bomgr_find_va(ws
, bo
->base
.size
, 1 << 20);
984 va
.handle
= bo
->handle
;
985 va
.operation
= RADEON_VA_MAP
;
988 va
.flags
= RADEON_VM_PAGE_READABLE
|
989 RADEON_VM_PAGE_WRITEABLE
|
990 RADEON_VM_PAGE_SNOOPED
;
992 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
993 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
994 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
995 radeon_bo_destroy(&bo
->base
);
998 pipe_mutex_lock(ws
->bo_handles_mutex
);
999 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
1000 struct pb_buffer
*b
= &bo
->base
;
1001 struct radeon_bo
*old_bo
=
1002 util_hash_table_get(ws
->bo_vas
, (void*)(uintptr_t)va
.offset
);
1004 pipe_mutex_unlock(ws
->bo_handles_mutex
);
1005 pb_reference(&b
, &old_bo
->base
);
1009 util_hash_table_set(ws
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
1010 pipe_mutex_unlock(ws
->bo_handles_mutex
);
1013 bo
->initial_domain
= radeon_bo_get_initial_domain((void*)bo
);
1015 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1016 ws
->allocated_vram
+= align(bo
->base
.size
, ws
->info
.gart_page_size
);
1017 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1018 ws
->allocated_gtt
+= align(bo
->base
.size
, ws
->info
.gart_page_size
);
1020 return (struct pb_buffer
*)bo
;
1023 pipe_mutex_unlock(ws
->bo_handles_mutex
);
1027 static bool radeon_winsys_bo_get_handle(struct pb_buffer
*buffer
,
1028 unsigned stride
, unsigned offset
,
1029 unsigned slice_size
,
1030 struct winsys_handle
*whandle
)
1032 struct drm_gem_flink flink
;
1033 struct radeon_bo
*bo
= radeon_bo(buffer
);
1034 struct radeon_drm_winsys
*ws
= bo
->rws
;
1036 memset(&flink
, 0, sizeof(flink
));
1038 bo
->use_reusable_pool
= false;
1040 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
1041 if (!bo
->flink_name
) {
1042 flink
.handle
= bo
->handle
;
1044 if (ioctl(ws
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
)) {
1048 bo
->flink_name
= flink
.name
;
1050 pipe_mutex_lock(ws
->bo_handles_mutex
);
1051 util_hash_table_set(ws
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
1052 pipe_mutex_unlock(ws
->bo_handles_mutex
);
1054 whandle
->handle
= bo
->flink_name
;
1055 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
1056 whandle
->handle
= bo
->handle
;
1057 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
1058 if (drmPrimeHandleToFD(ws
->fd
, bo
->handle
, DRM_CLOEXEC
, (int*)&whandle
->handle
))
1062 whandle
->stride
= stride
;
1063 whandle
->offset
= offset
;
1064 whandle
->offset
+= slice_size
* whandle
->layer
;
1069 static bool radeon_winsys_bo_is_user_ptr(struct pb_buffer
*buf
)
1071 return ((struct radeon_bo
*)buf
)->user_ptr
!= NULL
;
1074 static uint64_t radeon_winsys_bo_va(struct pb_buffer
*buf
)
1076 return ((struct radeon_bo
*)buf
)->va
;
1079 void radeon_drm_bo_init_functions(struct radeon_drm_winsys
*ws
)
1081 ws
->base
.buffer_set_metadata
= radeon_bo_set_metadata
;
1082 ws
->base
.buffer_get_metadata
= radeon_bo_get_metadata
;
1083 ws
->base
.buffer_map
= radeon_bo_map
;
1084 ws
->base
.buffer_unmap
= radeon_bo_unmap
;
1085 ws
->base
.buffer_wait
= radeon_bo_wait
;
1086 ws
->base
.buffer_create
= radeon_winsys_bo_create
;
1087 ws
->base
.buffer_from_handle
= radeon_winsys_bo_from_handle
;
1088 ws
->base
.buffer_from_ptr
= radeon_winsys_bo_from_ptr
;
1089 ws
->base
.buffer_is_user_ptr
= radeon_winsys_bo_is_user_ptr
;
1090 ws
->base
.buffer_get_handle
= radeon_winsys_bo_get_handle
;
1091 ws
->base
.buffer_get_virtual_address
= radeon_winsys_bo_va
;
1092 ws
->base
.buffer_get_initial_domain
= radeon_bo_get_initial_domain
;