src/gallium/winsys/radeon/drm/radeon_drm_bo.c

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 #define _FILE_OFFSET_BITS 64
  28 #include "radeon_drm_cs.h"
  29
  30 #include "util/u_hash_table.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_simple_list.h"
  33 #include "os/os_thread.h"
  34
  35 #include "state_tracker/drm_driver.h"
  36
  37 #include <sys/ioctl.h>
  38 #include <sys/mman.h>
  39 #include <xf86drm.h>
  40 #include <errno.h>
  41
  42 #define RADEON_BO_FLAGS_MACRO_TILE  1
  43 #define RADEON_BO_FLAGS_MICRO_TILE  2
  44 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
  45
  46 extern const struct pb_vtbl radeon_bo_vtbl;
  47
  48
  49 static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
  50 {
  51     assert(bo->vtbl == &radeon_bo_vtbl);
  52     return (struct radeon_bo *)bo;
  53 }
  54
  55 struct radeon_bomgr {
  56     /* Base class. */
  57     struct pb_manager base;
  58
  59     /* Winsys. */
  60     struct radeon_drm_winsys *rws;
  61
  62     /* List of buffer handles and its mutex. */
  63     struct util_hash_table *bo_handles;
  64     pipe_mutex bo_handles_mutex;
  65 };
  66
  67 static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
  68 {
  69     return (struct radeon_bomgr *)mgr;
  70 }
  71
  72 static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
  73 {
  74     struct radeon_bo *bo = NULL;
  75
  76     if (_buf->vtbl == &radeon_bo_vtbl) {
  77         bo = radeon_bo(_buf);
  78     } else {
  79         struct pb_buffer *base_buf;
  80         pb_size offset;
  81         pb_get_base_buffer(_buf, &base_buf, &offset);
  82
  83         if (base_buf->vtbl == &radeon_bo_vtbl)
  84             bo = radeon_bo(base_buf);
  85     }
  86
  87     return bo;
  88 }
  89
  90 static void radeon_bo_wait(struct r300_winsys_bo *_buf)
  91 {
  92     struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
  93     struct drm_radeon_gem_wait_idle args = {};
  94
  95     while (p_atomic_read(&bo->num_active_ioctls)) {
  96         sched_yield();
  97     }
  98
  99     args.handle = bo->handle;
 100     while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
 101                                &args, sizeof(args)) == -EBUSY);
 102 }
 103
 104 static boolean radeon_bo_is_busy(struct r300_winsys_bo *_buf)
 105 {
 106     struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
 107     struct drm_radeon_gem_busy args = {};
 108
 109     if (p_atomic_read(&bo->num_active_ioctls)) {
 110         return TRUE;
 111     }
 112
 113     args.handle = bo->handle;
 114     return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
 115                                &args, sizeof(args)) != 0;
 116 }
 117
 118 static void radeon_bo_destroy(struct pb_buffer *_buf)
 119 {
 120     struct radeon_bo *bo = radeon_bo(_buf);
 121     struct drm_gem_close args = {};
 122
 123     if (bo->name) {
 124         pipe_mutex_lock(bo->mgr->bo_handles_mutex);
 125         util_hash_table_remove(bo->mgr->bo_handles,
 126                                (void*)(uintptr_t)bo->name);
 127         pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
 128     }
 129
 130     if (bo->ptr)
 131         munmap(bo->ptr, bo->size);
 132
 133     /* Close object. */
 134     args.handle = bo->handle;
 135     drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
 136     pipe_mutex_destroy(bo->map_mutex);
 137     FREE(bo);
 138 }
 139
 140 static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage)
 141 {
 142     unsigned res = 0;
 143
 144     if (usage & PIPE_TRANSFER_DONTBLOCK)
 145         res |= PB_USAGE_DONTBLOCK;
 146
 147     if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
 148         res |= PB_USAGE_UNSYNCHRONIZED;
 149
 150     return res;
 151 }
 152
 153 static void *radeon_bo_map_internal(struct pb_buffer *_buf,
 154                                     unsigned flags, void *flush_ctx)
 155 {
 156     struct radeon_bo *bo = radeon_bo(_buf);
 157     struct radeon_drm_cs *cs = flush_ctx;
 158     struct drm_radeon_gem_mmap args = {};
 159     void *ptr;
 160
 161     /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
 162     if (!(flags & PB_USAGE_UNSYNCHRONIZED)) {
 163         /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
 164         if (flags & PB_USAGE_DONTBLOCK) {
 165             if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 166                 cs->flush_cs(cs->flush_data, R300_FLUSH_ASYNC);
 167                 return NULL;
 168             }
 169
 170             if (radeon_bo_is_busy((struct r300_winsys_bo*)bo)) {
 171                 return NULL;
 172             }
 173         } else {
 174             if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 175                 cs->flush_cs(cs->flush_data, 0);
 176             } else {
 177                 /* Try to avoid busy-waiting in radeon_bo_wait. */
 178                 if (p_atomic_read(&bo->num_active_ioctls))
 179                     radeon_drm_cs_sync_flush(cs);
 180             }
 181
 182             radeon_bo_wait((struct r300_winsys_bo*)bo);
 183         }
 184     }
 185
 186     /* Return the pointer if it's already mapped. */
 187     if (bo->ptr)
 188         return bo->ptr;
 189
 190     /* Map the buffer. */
 191     pipe_mutex_lock(bo->map_mutex);
 192     /* Return the pointer if it's already mapped (in case of a race). */
 193     if (bo->ptr) {
 194         pipe_mutex_unlock(bo->map_mutex);
 195         return bo->ptr;
 196     }
 197     args.handle = bo->handle;
 198     args.offset = 0;
 199     args.size = (uint64_t)bo->size;
 200     if (drmCommandWriteRead(bo->rws->fd,
 201                             DRM_RADEON_GEM_MMAP,
 202                             &args,
 203                             sizeof(args))) {
 204         pipe_mutex_unlock(bo->map_mutex);
 205         fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
 206                 bo, bo->handle);
 207         return NULL;
 208     }
 209
 210     ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
 211                bo->rws->fd, args.addr_ptr);
 212     if (ptr == MAP_FAILED) {
 213         pipe_mutex_unlock(bo->map_mutex);
 214         fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
 215         return NULL;
 216     }
 217     bo->ptr = ptr;
 218     pipe_mutex_unlock(bo->map_mutex);
 219
 220     return bo->ptr;
 221 }
 222
 223 static void radeon_bo_unmap_internal(struct pb_buffer *_buf)
 224 {
 225     /* NOP */
 226 }
 227
 228 static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
 229                                       struct pb_buffer **base_buf,
 230                                       unsigned *offset)
 231 {
 232     *base_buf = buf;
 233     *offset = 0;
 234 }
 235
 236 static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
 237                                           struct pb_validate *vl,
 238                                           unsigned flags)
 239 {
 240     /* Always pinned */
 241     return PIPE_OK;
 242 }
 243
 244 static void radeon_bo_fence(struct pb_buffer *buf,
 245                             struct pipe_fence_handle *fence)
 246 {
 247 }
 248
 249 const struct pb_vtbl radeon_bo_vtbl = {
 250     radeon_bo_destroy,
 251     radeon_bo_map_internal,
 252     radeon_bo_unmap_internal,
 253     radeon_bo_validate,
 254     radeon_bo_fence,
 255     radeon_bo_get_base_buffer,
 256 };
 257
 258 static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
 259                                                 pb_size size,
 260                                                 const struct pb_desc *desc)
 261 {
 262     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 263     struct radeon_drm_winsys *rws = mgr->rws;
 264     struct radeon_bo *bo;
 265     struct drm_radeon_gem_create args = {};
 266
 267     args.size = size;
 268     args.alignment = desc->alignment;
 269     args.initial_domain =
 270         (desc->usage & RADEON_PB_USAGE_DOMAIN_GTT  ?
 271          RADEON_GEM_DOMAIN_GTT  : 0) |
 272         (desc->usage & RADEON_PB_USAGE_DOMAIN_VRAM ?
 273          RADEON_GEM_DOMAIN_VRAM : 0);
 274
 275     if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
 276                             &args, sizeof(args))) {
 277         fprintf(stderr, "Failed to allocate :\n");
 278         fprintf(stderr, "   size      : %d bytes\n", size);
 279         fprintf(stderr, "   alignment : %d bytes\n", desc->alignment);
 280         fprintf(stderr, "   domains   : %d\n", args.initial_domain);
 281         return NULL;
 282     }
 283
 284     bo = CALLOC_STRUCT(radeon_bo);
 285     if (!bo)
 286         return NULL;
 287
 288     pipe_reference_init(&bo->base.base.reference, 1);
 289     bo->base.base.alignment = desc->alignment;
 290     bo->base.base.usage = desc->usage;
 291     bo->base.base.size = size;
 292     bo->base.vtbl = &radeon_bo_vtbl;
 293     bo->mgr = mgr;
 294     bo->rws = mgr->rws;
 295     bo->handle = args.handle;
 296     bo->size = size;
 297     pipe_mutex_init(bo->map_mutex);
 298
 299     return &bo->base;
 300 }
 301
 302 static void radeon_bomgr_flush(struct pb_manager *mgr)
 303 {
 304     /* NOP */
 305 }
 306
 307 /* This is for the cache bufmgr. */
 308 static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr,
 309                                            struct pb_buffer *_buf)
 310 {
 311    struct radeon_bo *bo = radeon_bo(_buf);
 312
 313    if (radeon_bo_is_referenced_by_any_cs(bo)) {
 314        return TRUE;
 315    }
 316
 317    if (radeon_bo_is_busy((struct r300_winsys_bo*)bo)) {
 318        return TRUE;
 319    }
 320
 321    return FALSE;
 322 }
 323
 324 static void radeon_bomgr_destroy(struct pb_manager *_mgr)
 325 {
 326     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 327     util_hash_table_destroy(mgr->bo_handles);
 328     pipe_mutex_destroy(mgr->bo_handles_mutex);
 329     FREE(mgr);
 330 }
 331
 332 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 333
 334 static unsigned handle_hash(void *key)
 335 {
 336     return PTR_TO_UINT(key);
 337 }
 338
 339 static int handle_compare(void *key1, void *key2)
 340 {
 341     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 342 }
 343
 344 struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
 345 {
 346     struct radeon_bomgr *mgr;
 347
 348     mgr = CALLOC_STRUCT(radeon_bomgr);
 349     if (!mgr)
 350         return NULL;
 351
 352     mgr->base.destroy = radeon_bomgr_destroy;
 353     mgr->base.create_buffer = radeon_bomgr_create_bo;
 354     mgr->base.flush = radeon_bomgr_flush;
 355     mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
 356
 357     mgr->rws = rws;
 358     mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 359     pipe_mutex_init(mgr->bo_handles_mutex);
 360     return &mgr->base;
 361 }
 362
 363 static void *radeon_bo_map(struct r300_winsys_bo *buf,
 364                            struct r300_winsys_cs *cs,
 365                            enum pipe_transfer_usage usage)
 366 {
 367     struct pb_buffer *_buf = pb_buffer(buf);
 368
 369     return pb_map(_buf, get_pb_usage_from_transfer_flags(usage), cs);
 370 }
 371
 372 static void radeon_bo_get_tiling(struct r300_winsys_bo *_buf,
 373                                  enum r300_buffer_tiling *microtiled,
 374                                  enum r300_buffer_tiling *macrotiled)
 375 {
 376     struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
 377     struct drm_radeon_gem_set_tiling args = {};
 378
 379     args.handle = bo->handle;
 380
 381     drmCommandWriteRead(bo->rws->fd,
 382                         DRM_RADEON_GEM_GET_TILING,
 383                         &args,
 384                         sizeof(args));
 385
 386     *microtiled = R300_BUFFER_LINEAR;
 387     *macrotiled = R300_BUFFER_LINEAR;
 388     if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE)
 389         *microtiled = R300_BUFFER_TILED;
 390
 391     if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE)
 392         *macrotiled = R300_BUFFER_TILED;
 393 }
 394
 395 static void radeon_bo_set_tiling(struct r300_winsys_bo *_buf,
 396                                  struct r300_winsys_cs *rcs,
 397                                  enum r300_buffer_tiling microtiled,
 398                                  enum r300_buffer_tiling macrotiled,
 399                                  uint32_t pitch)
 400 {
 401     struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
 402     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 403     struct drm_radeon_gem_set_tiling args = {};
 404
 405     /* Tiling determines how DRM treats the buffer data.
 406      * We must flush CS when changing it if the buffer is referenced. */
 407     if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
 408         cs->flush_cs(cs->flush_data, 0);
 409     }
 410
 411     while (p_atomic_read(&bo->num_active_ioctls)) {
 412         sched_yield();
 413     }
 414
 415     if (microtiled == R300_BUFFER_TILED)
 416         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE;
 417     else if (microtiled == R300_BUFFER_SQUARETILED)
 418         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
 419
 420     if (macrotiled == R300_BUFFER_TILED)
 421         args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
 422
 423     args.handle = bo->handle;
 424     args.pitch = pitch;
 425
 426     drmCommandWriteRead(bo->rws->fd,
 427                         DRM_RADEON_GEM_SET_TILING,
 428                         &args,
 429                         sizeof(args));
 430 }
 431
 432 static struct r300_winsys_cs_handle *radeon_drm_get_cs_handle(
 433         struct r300_winsys_bo *_buf)
 434 {
 435     /* return radeon_bo. */
 436     return (struct r300_winsys_cs_handle*)
 437             get_radeon_bo(pb_buffer(_buf));
 438 }
 439
 440 static unsigned get_pb_usage_from_create_flags(unsigned bind, unsigned usage,
 441                                                enum r300_buffer_domain domain)
 442 {
 443     unsigned res = 0;
 444
 445     if (domain & R300_DOMAIN_GTT)
 446         res |= RADEON_PB_USAGE_DOMAIN_GTT;
 447
 448     if (domain & R300_DOMAIN_VRAM)
 449         res |= RADEON_PB_USAGE_DOMAIN_VRAM;
 450
 451     return res;
 452 }
 453
 454 static struct r300_winsys_bo *
 455 radeon_winsys_bo_create(struct r300_winsys_screen *rws,
 456                         unsigned size,
 457                         unsigned alignment,
 458                         unsigned bind,
 459                         unsigned usage,
 460                         enum r300_buffer_domain domain)
 461 {
 462     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 463     struct pb_desc desc;
 464     struct pb_manager *provider;
 465     struct pb_buffer *buffer;
 466
 467     memset(&desc, 0, sizeof(desc));
 468     desc.alignment = alignment;
 469     desc.usage = get_pb_usage_from_create_flags(bind, usage, domain);
 470
 471     /* Assign a buffer manager. */
 472     if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
 473         provider = ws->cman;
 474     else
 475         provider = ws->kman;
 476
 477     buffer = provider->create_buffer(provider, size, &desc);
 478     if (!buffer)
 479         return NULL;
 480
 481     return (struct r300_winsys_bo*)buffer;
 482 }
 483
 484 static struct r300_winsys_bo *radeon_winsys_bo_from_handle(struct r300_winsys_screen *rws,
 485                                                            struct winsys_handle *whandle,
 486                                                            unsigned *stride,
 487                                                            unsigned *size)
 488 {
 489     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 490     struct radeon_bo *bo;
 491     struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
 492     struct drm_gem_open open_arg = {};
 493
 494     /* We must maintain a list of pairs <handle, bo>, so that we always return
 495      * the same BO for one particular handle. If we didn't do that and created
 496      * more than one BO for the same handle and then relocated them in a CS,
 497      * we would hit a deadlock in the kernel.
 498      *
 499      * The list of pairs is guarded by a mutex, of course. */
 500     pipe_mutex_lock(mgr->bo_handles_mutex);
 501
 502     /* First check if there already is an existing bo for the handle. */
 503     bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
 504     if (bo) {
 505         /* Increase the refcount. */
 506         struct pb_buffer *b = NULL;
 507         pb_reference(&b, &bo->base);
 508         goto done;
 509     }
 510
 511     /* There isn't, create a new one. */
 512     bo = CALLOC_STRUCT(radeon_bo);
 513     if (!bo) {
 514         goto fail;
 515     }
 516
 517     /* Open the BO. */
 518     open_arg.name = whandle->handle;
 519     if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
 520         FREE(bo);
 521         goto fail;
 522     }
 523     bo->handle = open_arg.handle;
 524     bo->size = open_arg.size;
 525     bo->name = whandle->handle;
 526
 527     /* Initialize it. */
 528     pipe_reference_init(&bo->base.base.reference, 1);
 529     bo->base.base.alignment = 0;
 530     bo->base.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
 531     bo->base.base.size = bo->size;
 532     bo->base.vtbl = &radeon_bo_vtbl;
 533     bo->mgr = mgr;
 534     bo->rws = mgr->rws;
 535     pipe_mutex_init(bo->map_mutex);
 536
 537     util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
 538
 539 done:
 540     pipe_mutex_unlock(mgr->bo_handles_mutex);
 541
 542     if (stride)
 543         *stride = whandle->stride;
 544     if (size)
 545         *size = bo->base.base.size;
 546
 547     return (struct r300_winsys_bo*)bo;
 548
 549 fail:
 550     pipe_mutex_unlock(mgr->bo_handles_mutex);
 551     return NULL;
 552 }
 553
 554 static boolean radeon_winsys_bo_get_handle(struct r300_winsys_bo *buffer,
 555                                            unsigned stride,
 556                                            struct winsys_handle *whandle)
 557 {
 558     struct drm_gem_flink flink = {};
 559     struct radeon_bo *bo = get_radeon_bo(pb_buffer(buffer));
 560
 561     if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 562         if (!bo->flinked) {
 563             flink.handle = bo->handle;
 564
 565             if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
 566                 return FALSE;
 567             }
 568
 569             bo->flinked = TRUE;
 570             bo->flink = flink.name;
 571         }
 572         whandle->handle = bo->flink;
 573     } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 574         whandle->handle = bo->handle;
 575     }
 576
 577     whandle->stride = stride;
 578     return TRUE;
 579 }
 580
 581 void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws)
 582 {
 583     ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle;
 584     ws->base.buffer_set_tiling = radeon_bo_set_tiling;
 585     ws->base.buffer_get_tiling = radeon_bo_get_tiling;
 586     ws->base.buffer_map = radeon_bo_map;
 587     ws->base.buffer_unmap = pb_unmap;
 588     ws->base.buffer_wait = radeon_bo_wait;
 589     ws->base.buffer_is_busy = radeon_bo_is_busy;
 590     ws->base.buffer_create = radeon_winsys_bo_create;
 591     ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
 592     ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;
 593 }