2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
27 #define _FILE_OFFSET_BITS 64
28 #include "radeon_drm_cs.h"
30 #include "util/u_hash_table.h"
31 #include "util/u_memory.h"
32 #include "util/u_simple_list.h"
33 #include "util/u_double_list.h"
34 #include "os/os_thread.h"
35 #include "os/os_mman.h"
37 #include "state_tracker/drm_driver.h"
39 #include <sys/ioctl.h>
44 * this are copy from radeon_drm, once an updated libdrm is released
45 * we should bump configure.ac requirement for it and remove the following
48 #define RADEON_BO_FLAGS_MACRO_TILE 1
49 #define RADEON_BO_FLAGS_MICRO_TILE 2
50 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
52 #ifndef DRM_RADEON_GEM_WAIT
53 #define DRM_RADEON_GEM_WAIT 0x2b
55 #define RADEON_GEM_NO_WAIT 0x1
56 #define RADEON_GEM_USAGE_READ 0x2
57 #define RADEON_GEM_USAGE_WRITE 0x4
59 struct drm_radeon_gem_wait
{
61 uint32_t flags
; /* one of RADEON_GEM_* */
68 #define RADEON_VA_MAP 1
69 #define RADEON_VA_UNMAP 2
71 #define RADEON_VA_RESULT_OK 0
72 #define RADEON_VA_RESULT_ERROR 1
73 #define RADEON_VA_RESULT_VA_EXIST 2
75 #define RADEON_VM_PAGE_VALID (1 << 0)
76 #define RADEON_VM_PAGE_READABLE (1 << 1)
77 #define RADEON_VM_PAGE_WRITEABLE (1 << 2)
78 #define RADEON_VM_PAGE_SYSTEM (1 << 3)
79 #define RADEON_VM_PAGE_SNOOPED (1 << 4)
81 struct drm_radeon_gem_va
{
89 #define DRM_RADEON_GEM_VA 0x2b
94 extern const struct pb_vtbl radeon_bo_vtbl
;
97 static INLINE
struct radeon_bo
*radeon_bo(struct pb_buffer
*bo
)
99 assert(bo
->vtbl
== &radeon_bo_vtbl
);
100 return (struct radeon_bo
*)bo
;
103 struct radeon_bo_va_hole
{
104 struct list_head list
;
109 struct radeon_bomgr
{
111 struct pb_manager base
;
114 struct radeon_drm_winsys
*rws
;
116 /* List of buffer handles and its mutex. */
117 struct util_hash_table
*bo_handles
;
118 pipe_mutex bo_handles_mutex
;
119 pipe_mutex bo_va_mutex
;
121 /* is virtual address supported */
124 struct list_head va_holes
;
127 static INLINE
struct radeon_bomgr
*radeon_bomgr(struct pb_manager
*mgr
)
129 return (struct radeon_bomgr
*)mgr
;
132 static struct radeon_bo
*get_radeon_bo(struct pb_buffer
*_buf
)
134 struct radeon_bo
*bo
= NULL
;
136 if (_buf
->vtbl
== &radeon_bo_vtbl
) {
137 bo
= radeon_bo(_buf
);
139 struct pb_buffer
*base_buf
;
141 pb_get_base_buffer(_buf
, &base_buf
, &offset
);
143 if (base_buf
->vtbl
== &radeon_bo_vtbl
)
144 bo
= radeon_bo(base_buf
);
150 static void radeon_bo_wait(struct pb_buffer
*_buf
, enum radeon_bo_usage usage
)
152 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
154 while (p_atomic_read(&bo
->num_active_ioctls
)) {
158 /* XXX use this when it's ready */
159 /*if (bo->rws->info.drm_minor >= 12) {
160 struct drm_radeon_gem_wait args = {};
161 args.handle = bo->handle;
163 while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
164 &args, sizeof(args)) == -EBUSY);
166 struct drm_radeon_gem_wait_idle args
;
167 memset(&args
, 0, sizeof(args
));
168 args
.handle
= bo
->handle
;
169 while (drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_WAIT_IDLE
,
170 &args
, sizeof(args
)) == -EBUSY
);
174 static boolean
radeon_bo_is_busy(struct pb_buffer
*_buf
,
175 enum radeon_bo_usage usage
)
177 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
179 if (p_atomic_read(&bo
->num_active_ioctls
)) {
183 /* XXX use this when it's ready */
184 /*if (bo->rws->info.drm_minor >= 12) {
185 struct drm_radeon_gem_wait args = {};
186 args.handle = bo->handle;
187 args.flags = usage | RADEON_GEM_NO_WAIT;
188 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
189 &args, sizeof(args)) != 0;
191 struct drm_radeon_gem_busy args
;
192 memset(&args
, 0, sizeof(args
));
193 args
.handle
= bo
->handle
;
194 return drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_BUSY
,
195 &args
, sizeof(args
)) != 0;
199 static uint64_t radeon_bomgr_find_va(struct radeon_bomgr
*mgr
, uint64_t size
, uint64_t alignment
)
201 struct radeon_bo_va_hole
*hole
, *n
;
202 uint64_t offset
= 0, waste
= 0;
204 pipe_mutex_lock(mgr
->bo_va_mutex
);
205 /* first look for a hole */
206 LIST_FOR_EACH_ENTRY_SAFE(hole
, n
, &mgr
->va_holes
, list
) {
207 offset
= hole
->offset
;
210 waste
= offset
% alignment
;
211 waste
= waste
? alignment
- waste
: 0;
214 if (offset
>= (hole
->offset
+ hole
->size
)) {
217 if (!waste
&& hole
->size
== size
) {
218 offset
= hole
->offset
;
219 list_del(&hole
->list
);
221 pipe_mutex_unlock(mgr
->bo_va_mutex
);
224 if ((hole
->size
- waste
) > size
) {
226 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
228 n
->offset
= hole
->offset
;
229 list_add(&n
->list
, &hole
->list
);
231 hole
->size
-= (size
+ waste
);
232 hole
->offset
+= size
+ waste
;
233 pipe_mutex_unlock(mgr
->bo_va_mutex
);
236 if ((hole
->size
- waste
) == size
) {
238 pipe_mutex_unlock(mgr
->bo_va_mutex
);
243 offset
= mgr
->va_offset
;
246 waste
= offset
% alignment
;
247 waste
= waste
? alignment
- waste
: 0;
250 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
253 list_add(&n
->list
, &mgr
->va_holes
);
256 mgr
->va_offset
+= size
+ waste
;
257 pipe_mutex_unlock(mgr
->bo_va_mutex
);
261 static void radeon_bomgr_force_va(struct radeon_bomgr
*mgr
, uint64_t va
, uint64_t size
)
263 pipe_mutex_lock(mgr
->bo_va_mutex
);
264 if (va
>= mgr
->va_offset
) {
265 if (va
> mgr
->va_offset
) {
266 struct radeon_bo_va_hole
*hole
;
267 hole
= CALLOC_STRUCT(radeon_bo_va_hole
);
269 hole
->size
= va
- mgr
->va_offset
;
270 hole
->offset
= mgr
->va_offset
;
271 list_add(&hole
->list
, &mgr
->va_holes
);
274 mgr
->va_offset
= va
+ size
;
276 struct radeon_bo_va_hole
*hole
, *n
;
277 uint64_t hole_end
, va_end
;
279 /* Prune/free all holes that fall into the range
281 LIST_FOR_EACH_ENTRY_SAFE(hole
, n
, &mgr
->va_holes
, list
) {
282 hole_end
= hole
->offset
+ hole
->size
;
284 if (hole
->offset
>= va_end
|| hole_end
<= va
)
286 if (hole
->offset
>= va
&& hole_end
<= va_end
) {
287 list_del(&hole
->list
);
291 if (hole
->offset
>= va
)
292 hole
->offset
= va_end
;
295 hole
->size
= hole_end
- hole
->offset
;
298 pipe_mutex_unlock(mgr
->bo_va_mutex
);
301 static void radeon_bomgr_free_va(struct radeon_bomgr
*mgr
, uint64_t va
, uint64_t size
)
303 struct radeon_bo_va_hole
*hole
;
305 pipe_mutex_lock(mgr
->bo_va_mutex
);
306 if ((va
+ size
) == mgr
->va_offset
) {
308 /* Delete uppermost hole if it reaches the new top */
309 if (!LIST_IS_EMPTY(&mgr
->va_holes
)) {
310 hole
= container_of(mgr
->va_holes
.next
, hole
, list
);
311 if ((hole
->offset
+ hole
->size
) == va
) {
312 mgr
->va_offset
= hole
->offset
;
313 list_del(&hole
->list
);
318 struct radeon_bo_va_hole
*next
;
320 hole
= container_of(&mgr
->va_holes
, hole
, list
);
321 LIST_FOR_EACH_ENTRY(next
, &mgr
->va_holes
, list
) {
322 if (next
->offset
< va
)
327 if (&hole
->list
!= &mgr
->va_holes
) {
328 /* Grow upper hole if it's adjacent */
329 if (hole
->offset
== (va
+ size
)) {
332 /* Merge lower hole if it's adjacent */
333 if (next
!= hole
&& &next
->list
!= &mgr
->va_holes
&&
334 (next
->offset
+ next
->size
) == va
) {
335 next
->size
+= hole
->size
;
336 list_del(&hole
->list
);
343 /* Grow lower hole if it's adjacent */
344 if (next
!= hole
&& &next
->list
!= &mgr
->va_holes
&&
345 (next
->offset
+ next
->size
) == va
) {
350 /* FIXME on allocation failure we just lose virtual address space
351 * maybe print a warning
353 next
= CALLOC_STRUCT(radeon_bo_va_hole
);
357 list_add(&next
->list
, &hole
->list
);
361 pipe_mutex_unlock(mgr
->bo_va_mutex
);
364 static void radeon_bo_destroy(struct pb_buffer
*_buf
)
366 struct radeon_bo
*bo
= radeon_bo(_buf
);
367 struct radeon_bomgr
*mgr
= bo
->mgr
;
368 struct drm_gem_close args
;
370 memset(&args
, 0, sizeof(args
));
373 pipe_mutex_lock(bo
->mgr
->bo_handles_mutex
);
374 util_hash_table_remove(bo
->mgr
->bo_handles
,
375 (void*)(uintptr_t)bo
->name
);
376 pipe_mutex_unlock(bo
->mgr
->bo_handles_mutex
);
380 os_munmap(bo
->ptr
, bo
->base
.size
);
383 args
.handle
= bo
->handle
;
384 drmIoctl(bo
->rws
->fd
, DRM_IOCTL_GEM_CLOSE
, &args
);
387 radeon_bomgr_free_va(mgr
, bo
->va
, bo
->va_size
);
390 pipe_mutex_destroy(bo
->map_mutex
);
394 static void *radeon_bo_map(struct radeon_winsys_cs_handle
*buf
,
395 struct radeon_winsys_cs
*rcs
,
396 enum pipe_transfer_usage usage
)
398 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
399 struct radeon_drm_cs
*cs
= (struct radeon_drm_cs
*)rcs
;
400 struct drm_radeon_gem_mmap args
= {0};
403 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
404 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
405 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
406 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
407 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
410 * Since we are mapping for read, we don't need to wait
411 * if the GPU is using the buffer for read too
412 * (neither one is changing it).
414 * Only check whether the buffer is being used for write. */
415 if (radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
416 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
);
420 if (radeon_bo_is_busy((struct pb_buffer
*)bo
,
421 RADEON_USAGE_WRITE
)) {
425 if (radeon_bo_is_referenced_by_cs(cs
, bo
)) {
426 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
);
430 if (radeon_bo_is_busy((struct pb_buffer
*)bo
,
431 RADEON_USAGE_READWRITE
)) {
436 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
439 * Since we are mapping for read, we don't need to wait
440 * if the GPU is using the buffer for read too
441 * (neither one is changing it).
443 * Only check whether the buffer is being used for write. */
444 if (radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
445 cs
->flush_cs(cs
->flush_data
, 0);
447 radeon_bo_wait((struct pb_buffer
*)bo
,
450 /* Mapping for write. */
451 if (radeon_bo_is_referenced_by_cs(cs
, bo
)) {
452 cs
->flush_cs(cs
->flush_data
, 0);
454 /* Try to avoid busy-waiting in radeon_bo_wait. */
455 if (p_atomic_read(&bo
->num_active_ioctls
))
456 radeon_drm_cs_sync_flush(rcs
);
459 radeon_bo_wait((struct pb_buffer
*)bo
, RADEON_USAGE_READWRITE
);
464 /* Return the pointer if it's already mapped. */
468 /* Map the buffer. */
469 pipe_mutex_lock(bo
->map_mutex
);
470 /* Return the pointer if it's already mapped (in case of a race). */
472 pipe_mutex_unlock(bo
->map_mutex
);
475 args
.handle
= bo
->handle
;
477 args
.size
= (uint64_t)bo
->base
.size
;
478 if (drmCommandWriteRead(bo
->rws
->fd
,
482 pipe_mutex_unlock(bo
->map_mutex
);
483 fprintf(stderr
, "radeon: gem_mmap failed: %p 0x%08X\n",
488 ptr
= os_mmap(0, args
.size
, PROT_READ
|PROT_WRITE
, MAP_SHARED
,
489 bo
->rws
->fd
, args
.addr_ptr
);
490 if (ptr
== MAP_FAILED
) {
491 pipe_mutex_unlock(bo
->map_mutex
);
492 fprintf(stderr
, "radeon: mmap failed, errno: %i\n", errno
);
496 pipe_mutex_unlock(bo
->map_mutex
);
501 static void radeon_bo_unmap(struct radeon_winsys_cs_handle
*_buf
)
506 static void radeon_bo_get_base_buffer(struct pb_buffer
*buf
,
507 struct pb_buffer
**base_buf
,
514 static enum pipe_error
radeon_bo_validate(struct pb_buffer
*_buf
,
515 struct pb_validate
*vl
,
522 static void radeon_bo_fence(struct pb_buffer
*buf
,
523 struct pipe_fence_handle
*fence
)
527 const struct pb_vtbl radeon_bo_vtbl
= {
529 NULL
, /* never called */
530 NULL
, /* never called */
533 radeon_bo_get_base_buffer
,
536 static struct pb_buffer
*radeon_bomgr_create_bo(struct pb_manager
*_mgr
,
538 const struct pb_desc
*desc
)
540 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
541 struct radeon_drm_winsys
*rws
= mgr
->rws
;
542 struct radeon_bo
*bo
;
543 struct drm_radeon_gem_create args
;
544 struct radeon_bo_desc
*rdesc
= (struct radeon_bo_desc
*)desc
;
547 memset(&args
, 0, sizeof(args
));
549 assert(rdesc
->initial_domains
);
550 assert((rdesc
->initial_domains
&
551 ~(RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
)) == 0);
554 args
.alignment
= desc
->alignment
;
555 args
.initial_domain
= rdesc
->initial_domains
;
557 if (drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_CREATE
,
558 &args
, sizeof(args
))) {
559 fprintf(stderr
, "radeon: Failed to allocate a buffer:\n");
560 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
561 fprintf(stderr
, "radeon: alignment : %d bytes\n", desc
->alignment
);
562 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
566 bo
= CALLOC_STRUCT(radeon_bo
);
570 pipe_reference_init(&bo
->base
.reference
, 1);
571 bo
->base
.alignment
= desc
->alignment
;
572 bo
->base
.usage
= desc
->usage
;
573 bo
->base
.size
= size
;
574 bo
->base
.vtbl
= &radeon_bo_vtbl
;
577 bo
->handle
= args
.handle
;
579 pipe_mutex_init(bo
->map_mutex
);
582 struct drm_radeon_gem_va va
;
584 bo
->va_size
= align(size
, 4096);
585 bo
->va
= radeon_bomgr_find_va(mgr
, bo
->va_size
, desc
->alignment
);
587 va
.handle
= bo
->handle
;
589 va
.operation
= RADEON_VA_MAP
;
590 va
.flags
= RADEON_VM_PAGE_READABLE
|
591 RADEON_VM_PAGE_WRITEABLE
|
592 RADEON_VM_PAGE_SNOOPED
;
594 r
= drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
595 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
596 fprintf(stderr
, "radeon: Failed to allocate virtual address for buffer:\n");
597 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
598 fprintf(stderr
, "radeon: alignment : %d bytes\n", desc
->alignment
);
599 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
600 fprintf(stderr
, "radeon: va : 0x%016llx\n", (unsigned long long)bo
->va
);
601 radeon_bo_destroy(&bo
->base
);
604 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
605 radeon_bomgr_free_va(mgr
, bo
->va
, bo
->va_size
);
607 radeon_bomgr_force_va(mgr
, bo
->va
, bo
->va_size
);
614 static void radeon_bomgr_flush(struct pb_manager
*mgr
)
619 /* This is for the cache bufmgr. */
620 static boolean
radeon_bomgr_is_buffer_busy(struct pb_manager
*_mgr
,
621 struct pb_buffer
*_buf
)
623 struct radeon_bo
*bo
= radeon_bo(_buf
);
625 if (radeon_bo_is_referenced_by_any_cs(bo
)) {
629 if (radeon_bo_is_busy((struct pb_buffer
*)bo
, RADEON_USAGE_READWRITE
)) {
636 static void radeon_bomgr_destroy(struct pb_manager
*_mgr
)
638 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
639 util_hash_table_destroy(mgr
->bo_handles
);
640 pipe_mutex_destroy(mgr
->bo_handles_mutex
);
641 pipe_mutex_destroy(mgr
->bo_va_mutex
);
645 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
647 static unsigned handle_hash(void *key
)
649 return PTR_TO_UINT(key
);
652 static int handle_compare(void *key1
, void *key2
)
654 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
657 struct pb_manager
*radeon_bomgr_create(struct radeon_drm_winsys
*rws
)
659 struct radeon_bomgr
*mgr
;
661 mgr
= CALLOC_STRUCT(radeon_bomgr
);
665 mgr
->base
.destroy
= radeon_bomgr_destroy
;
666 mgr
->base
.create_buffer
= radeon_bomgr_create_bo
;
667 mgr
->base
.flush
= radeon_bomgr_flush
;
668 mgr
->base
.is_buffer_busy
= radeon_bomgr_is_buffer_busy
;
671 mgr
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
672 pipe_mutex_init(mgr
->bo_handles_mutex
);
673 pipe_mutex_init(mgr
->bo_va_mutex
);
675 mgr
->va
= rws
->info
.r600_virtual_address
;
676 mgr
->va_offset
= rws
->info
.r600_va_start
;
677 list_inithead(&mgr
->va_holes
);
682 static unsigned eg_tile_split(unsigned tile_split
)
684 switch (tile_split
) {
685 case 0: tile_split
= 64; break;
686 case 1: tile_split
= 128; break;
687 case 2: tile_split
= 256; break;
688 case 3: tile_split
= 512; break;
690 case 4: tile_split
= 1024; break;
691 case 5: tile_split
= 2048; break;
692 case 6: tile_split
= 4096; break;
697 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
699 switch (eg_tile_split
) {
711 static void radeon_bo_get_tiling(struct pb_buffer
*_buf
,
712 enum radeon_bo_layout
*microtiled
,
713 enum radeon_bo_layout
*macrotiled
,
714 unsigned *bankw
, unsigned *bankh
,
715 unsigned *tile_split
,
716 unsigned *stencil_tile_split
,
719 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
720 struct drm_radeon_gem_set_tiling args
;
722 memset(&args
, 0, sizeof(args
));
724 args
.handle
= bo
->handle
;
726 drmCommandWriteRead(bo
->rws
->fd
,
727 DRM_RADEON_GEM_GET_TILING
,
731 *microtiled
= RADEON_LAYOUT_LINEAR
;
732 *macrotiled
= RADEON_LAYOUT_LINEAR
;
733 if (args
.tiling_flags
& RADEON_BO_FLAGS_MICRO_TILE
)
734 *microtiled
= RADEON_LAYOUT_TILED
;
736 if (args
.tiling_flags
& RADEON_BO_FLAGS_MACRO_TILE
)
737 *macrotiled
= RADEON_LAYOUT_TILED
;
738 if (bankw
&& tile_split
&& stencil_tile_split
&& mtilea
&& tile_split
) {
739 *bankw
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
740 *bankh
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
741 *tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
742 *stencil_tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
;
743 *mtilea
= (args
.tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
744 *tile_split
= eg_tile_split(*tile_split
);
748 static void radeon_bo_set_tiling(struct pb_buffer
*_buf
,
749 struct radeon_winsys_cs
*rcs
,
750 enum radeon_bo_layout microtiled
,
751 enum radeon_bo_layout macrotiled
,
752 unsigned bankw
, unsigned bankh
,
754 unsigned stencil_tile_split
,
758 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
759 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
760 struct drm_radeon_gem_set_tiling args
;
762 memset(&args
, 0, sizeof(args
));
764 /* Tiling determines how DRM treats the buffer data.
765 * We must flush CS when changing it if the buffer is referenced. */
766 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
767 cs
->flush_cs(cs
->flush_data
, 0);
770 while (p_atomic_read(&bo
->num_active_ioctls
)) {
774 if (microtiled
== RADEON_LAYOUT_TILED
)
775 args
.tiling_flags
|= RADEON_BO_FLAGS_MICRO_TILE
;
776 else if (microtiled
== RADEON_LAYOUT_SQUARETILED
)
777 args
.tiling_flags
|= RADEON_BO_FLAGS_MICRO_TILE_SQUARE
;
779 if (macrotiled
== RADEON_LAYOUT_TILED
)
780 args
.tiling_flags
|= RADEON_BO_FLAGS_MACRO_TILE
;
782 args
.tiling_flags
|= (bankw
& RADEON_TILING_EG_BANKW_MASK
) <<
783 RADEON_TILING_EG_BANKW_SHIFT
;
784 args
.tiling_flags
|= (bankh
& RADEON_TILING_EG_BANKH_MASK
) <<
785 RADEON_TILING_EG_BANKH_SHIFT
;
787 args
.tiling_flags
|= (eg_tile_split_rev(tile_split
) &
788 RADEON_TILING_EG_TILE_SPLIT_MASK
) <<
789 RADEON_TILING_EG_TILE_SPLIT_SHIFT
;
791 args
.tiling_flags
|= (stencil_tile_split
&
792 RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
) <<
793 RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
;
794 args
.tiling_flags
|= (mtilea
& RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
) <<
795 RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
;
797 args
.handle
= bo
->handle
;
800 drmCommandWriteRead(bo
->rws
->fd
,
801 DRM_RADEON_GEM_SET_TILING
,
806 static struct radeon_winsys_cs_handle
*radeon_drm_get_cs_handle(struct pb_buffer
*_buf
)
808 /* return radeon_bo. */
809 return (struct radeon_winsys_cs_handle
*)get_radeon_bo(_buf
);
812 static struct pb_buffer
*
813 radeon_winsys_bo_create(struct radeon_winsys
*rws
,
816 boolean use_reusable_pool
,
817 enum radeon_bo_domain domain
)
819 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
820 struct radeon_bo_desc desc
;
821 struct pb_manager
*provider
;
822 struct pb_buffer
*buffer
;
824 memset(&desc
, 0, sizeof(desc
));
825 desc
.base
.alignment
= alignment
;
827 /* Additional criteria for the cache manager. */
828 desc
.base
.usage
= domain
;
829 desc
.initial_domains
= domain
;
831 /* Assign a buffer manager. */
832 if (use_reusable_pool
)
837 buffer
= provider
->create_buffer(provider
, size
, &desc
.base
);
841 return (struct pb_buffer
*)buffer
;
844 static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys
*rws
,
845 struct winsys_handle
*whandle
,
848 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
849 struct radeon_bo
*bo
;
850 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
851 struct drm_gem_open open_arg
= {};
854 memset(&open_arg
, 0, sizeof(open_arg
));
856 /* We must maintain a list of pairs <handle, bo>, so that we always return
857 * the same BO for one particular handle. If we didn't do that and created
858 * more than one BO for the same handle and then relocated them in a CS,
859 * we would hit a deadlock in the kernel.
861 * The list of pairs is guarded by a mutex, of course. */
862 pipe_mutex_lock(mgr
->bo_handles_mutex
);
864 /* First check if there already is an existing bo for the handle. */
865 bo
= util_hash_table_get(mgr
->bo_handles
, (void*)(uintptr_t)whandle
->handle
);
867 /* Increase the refcount. */
868 struct pb_buffer
*b
= NULL
;
869 pb_reference(&b
, &bo
->base
);
873 /* There isn't, create a new one. */
874 bo
= CALLOC_STRUCT(radeon_bo
);
880 open_arg
.name
= whandle
->handle
;
881 if (drmIoctl(ws
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
)) {
885 bo
->handle
= open_arg
.handle
;
886 bo
->name
= whandle
->handle
;
889 pipe_reference_init(&bo
->base
.reference
, 1);
890 bo
->base
.alignment
= 0;
891 bo
->base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
892 bo
->base
.size
= open_arg
.size
;
893 bo
->base
.vtbl
= &radeon_bo_vtbl
;
897 pipe_mutex_init(bo
->map_mutex
);
899 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)whandle
->handle
, bo
);
902 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
905 *stride
= whandle
->stride
;
907 if (mgr
->va
&& !bo
->va
) {
908 struct drm_radeon_gem_va va
;
910 bo
->va_size
= ((bo
->base
.size
+ 4095) & ~4095);
911 bo
->va
= radeon_bomgr_find_va(mgr
, bo
->va_size
, 1 << 20);
913 va
.handle
= bo
->handle
;
914 va
.operation
= RADEON_VA_MAP
;
917 va
.flags
= RADEON_VM_PAGE_READABLE
|
918 RADEON_VM_PAGE_WRITEABLE
|
919 RADEON_VM_PAGE_SNOOPED
;
921 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
922 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
923 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
924 radeon_bo_destroy(&bo
->base
);
927 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
928 radeon_bomgr_free_va(mgr
, bo
->va
, bo
->va_size
);
930 radeon_bomgr_force_va(mgr
, bo
->va
, bo
->va_size
);
934 return (struct pb_buffer
*)bo
;
937 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
941 static boolean
radeon_winsys_bo_get_handle(struct pb_buffer
*buffer
,
943 struct winsys_handle
*whandle
)
945 struct drm_gem_flink flink
;
946 struct radeon_bo
*bo
= get_radeon_bo(buffer
);
948 memset(&flink
, 0, sizeof(flink
));
950 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
952 flink
.handle
= bo
->handle
;
954 if (ioctl(bo
->rws
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
)) {
959 bo
->flink
= flink
.name
;
961 whandle
->handle
= bo
->flink
;
962 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
963 whandle
->handle
= bo
->handle
;
966 pipe_mutex_lock(bo
->mgr
->bo_handles_mutex
);
967 util_hash_table_set(bo
->mgr
->bo_handles
, (void*)(uintptr_t)whandle
->handle
, bo
);
968 pipe_mutex_unlock(bo
->mgr
->bo_handles_mutex
);
970 whandle
->stride
= stride
;
974 static uint64_t radeon_winsys_bo_va(struct radeon_winsys_cs_handle
*buf
)
976 return ((struct radeon_bo
*)buf
)->va
;
979 void radeon_bomgr_init_functions(struct radeon_drm_winsys
*ws
)
981 ws
->base
.buffer_get_cs_handle
= radeon_drm_get_cs_handle
;
982 ws
->base
.buffer_set_tiling
= radeon_bo_set_tiling
;
983 ws
->base
.buffer_get_tiling
= radeon_bo_get_tiling
;
984 ws
->base
.buffer_map
= radeon_bo_map
;
985 ws
->base
.buffer_unmap
= radeon_bo_unmap
;
986 ws
->base
.buffer_wait
= radeon_bo_wait
;
987 ws
->base
.buffer_is_busy
= radeon_bo_is_busy
;
988 ws
->base
.buffer_create
= radeon_winsys_bo_create
;
989 ws
->base
.buffer_from_handle
= radeon_winsys_bo_from_handle
;
990 ws
->base
.buffer_get_handle
= radeon_winsys_bo_get_handle
;
991 ws
->base
.buffer_get_virtual_address
= radeon_winsys_bo_va
;