2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
27 #include "radeon_drm_cs.h"
29 #include "util/u_hash_table.h"
30 #include "util/u_memory.h"
31 #include "util/simple_list.h"
32 #include "util/u_double_list.h"
33 #include "os/os_thread.h"
34 #include "os/os_mman.h"
35 #include "os/os_time.h"
37 #include "state_tracker/drm_driver.h"
39 #include <sys/ioctl.h>
45 extern const struct pb_vtbl radeon_bo_vtbl
;
47 static INLINE
struct radeon_bo
*radeon_bo(struct pb_buffer
*bo
)
49 assert(bo
->vtbl
== &radeon_bo_vtbl
);
50 return (struct radeon_bo
*)bo
;
53 struct radeon_bo_va_hole
{
54 struct list_head list
;
61 struct pb_manager base
;
64 struct radeon_drm_winsys
*rws
;
66 /* List of buffer GEM names. Protected by bo_handles_mutex. */
67 struct util_hash_table
*bo_names
;
68 /* List of buffer handles. Protectded by bo_handles_mutex. */
69 struct util_hash_table
*bo_handles
;
70 /* List of buffer virtual memory ranges. Protectded by bo_handles_mutex. */
71 struct util_hash_table
*bo_vas
;
72 pipe_mutex bo_handles_mutex
;
73 pipe_mutex bo_va_mutex
;
75 /* is virtual address supported */
78 struct list_head va_holes
;
81 static INLINE
struct radeon_bomgr
*radeon_bomgr(struct pb_manager
*mgr
)
83 return (struct radeon_bomgr
*)mgr
;
86 static struct radeon_bo
*get_radeon_bo(struct pb_buffer
*_buf
)
88 struct radeon_bo
*bo
= NULL
;
90 if (_buf
->vtbl
== &radeon_bo_vtbl
) {
93 struct pb_buffer
*base_buf
;
95 pb_get_base_buffer(_buf
, &base_buf
, &offset
);
97 if (base_buf
->vtbl
== &radeon_bo_vtbl
)
98 bo
= radeon_bo(base_buf
);
104 static void radeon_bo_wait(struct pb_buffer
*_buf
, enum radeon_bo_usage usage
)
106 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
107 struct drm_radeon_gem_wait_idle args
= {0};
109 while (p_atomic_read(&bo
->num_active_ioctls
)) {
113 args
.handle
= bo
->handle
;
114 while (drmCommandWrite(bo
->rws
->fd
, DRM_RADEON_GEM_WAIT_IDLE
,
115 &args
, sizeof(args
)) == -EBUSY
);
118 static boolean
radeon_bo_is_busy(struct pb_buffer
*_buf
,
119 enum radeon_bo_usage usage
)
121 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
122 struct drm_radeon_gem_busy args
= {0};
124 if (p_atomic_read(&bo
->num_active_ioctls
)) {
128 args
.handle
= bo
->handle
;
129 return drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_BUSY
,
130 &args
, sizeof(args
)) != 0;
133 static enum radeon_bo_domain
get_valid_domain(enum radeon_bo_domain domain
)
135 /* Zero domains the driver doesn't understand. */
136 domain
&= RADEON_DOMAIN_VRAM_GTT
;
138 /* If no domain is set, we must set something... */
140 domain
= RADEON_DOMAIN_VRAM_GTT
;
145 static enum radeon_bo_domain
radeon_bo_get_initial_domain(
146 struct radeon_winsys_cs_handle
*buf
)
148 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
149 struct drm_radeon_gem_op args
;
151 if (bo
->rws
->info
.drm_minor
< 38)
152 return RADEON_DOMAIN_VRAM_GTT
;
154 memset(&args
, 0, sizeof(args
));
155 args
.handle
= bo
->handle
;
156 args
.op
= RADEON_GEM_OP_GET_INITIAL_DOMAIN
;
158 drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_OP
,
159 &args
, sizeof(args
));
161 /* GEM domains and winsys domains are defined the same. */
162 return get_valid_domain(args
.value
);
165 static uint64_t radeon_bomgr_find_va(struct radeon_bomgr
*mgr
, uint64_t size
, uint64_t alignment
)
167 struct radeon_bo_va_hole
*hole
, *n
;
168 uint64_t offset
= 0, waste
= 0;
170 alignment
= MAX2(alignment
, 4096);
171 size
= align(size
, 4096);
173 pipe_mutex_lock(mgr
->bo_va_mutex
);
174 /* first look for a hole */
175 LIST_FOR_EACH_ENTRY_SAFE(hole
, n
, &mgr
->va_holes
, list
) {
176 offset
= hole
->offset
;
177 waste
= offset
% alignment
;
178 waste
= waste
? alignment
- waste
: 0;
180 if (offset
>= (hole
->offset
+ hole
->size
)) {
183 if (!waste
&& hole
->size
== size
) {
184 offset
= hole
->offset
;
185 list_del(&hole
->list
);
187 pipe_mutex_unlock(mgr
->bo_va_mutex
);
190 if ((hole
->size
- waste
) > size
) {
192 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
194 n
->offset
= hole
->offset
;
195 list_add(&n
->list
, &hole
->list
);
197 hole
->size
-= (size
+ waste
);
198 hole
->offset
+= size
+ waste
;
199 pipe_mutex_unlock(mgr
->bo_va_mutex
);
202 if ((hole
->size
- waste
) == size
) {
204 pipe_mutex_unlock(mgr
->bo_va_mutex
);
209 offset
= mgr
->va_offset
;
210 waste
= offset
% alignment
;
211 waste
= waste
? alignment
- waste
: 0;
213 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
216 list_add(&n
->list
, &mgr
->va_holes
);
219 mgr
->va_offset
+= size
+ waste
;
220 pipe_mutex_unlock(mgr
->bo_va_mutex
);
224 static void radeon_bomgr_free_va(struct radeon_bomgr
*mgr
, uint64_t va
, uint64_t size
)
226 struct radeon_bo_va_hole
*hole
;
228 size
= align(size
, 4096);
230 pipe_mutex_lock(mgr
->bo_va_mutex
);
231 if ((va
+ size
) == mgr
->va_offset
) {
233 /* Delete uppermost hole if it reaches the new top */
234 if (!LIST_IS_EMPTY(&mgr
->va_holes
)) {
235 hole
= container_of(mgr
->va_holes
.next
, hole
, list
);
236 if ((hole
->offset
+ hole
->size
) == va
) {
237 mgr
->va_offset
= hole
->offset
;
238 list_del(&hole
->list
);
243 struct radeon_bo_va_hole
*next
;
245 hole
= container_of(&mgr
->va_holes
, hole
, list
);
246 LIST_FOR_EACH_ENTRY(next
, &mgr
->va_holes
, list
) {
247 if (next
->offset
< va
)
252 if (&hole
->list
!= &mgr
->va_holes
) {
253 /* Grow upper hole if it's adjacent */
254 if (hole
->offset
== (va
+ size
)) {
257 /* Merge lower hole if it's adjacent */
258 if (next
!= hole
&& &next
->list
!= &mgr
->va_holes
&&
259 (next
->offset
+ next
->size
) == va
) {
260 next
->size
+= hole
->size
;
261 list_del(&hole
->list
);
268 /* Grow lower hole if it's adjacent */
269 if (next
!= hole
&& &next
->list
!= &mgr
->va_holes
&&
270 (next
->offset
+ next
->size
) == va
) {
275 /* FIXME on allocation failure we just lose virtual address space
276 * maybe print a warning
278 next
= CALLOC_STRUCT(radeon_bo_va_hole
);
282 list_add(&next
->list
, &hole
->list
);
286 pipe_mutex_unlock(mgr
->bo_va_mutex
);
289 static void radeon_bo_destroy(struct pb_buffer
*_buf
)
291 struct radeon_bo
*bo
= radeon_bo(_buf
);
292 struct radeon_bomgr
*mgr
= bo
->mgr
;
293 struct drm_gem_close args
;
295 memset(&args
, 0, sizeof(args
));
297 pipe_mutex_lock(bo
->mgr
->bo_handles_mutex
);
298 util_hash_table_remove(bo
->mgr
->bo_handles
, (void*)(uintptr_t)bo
->handle
);
299 if (bo
->flink_name
) {
300 util_hash_table_remove(bo
->mgr
->bo_names
,
301 (void*)(uintptr_t)bo
->flink_name
);
303 pipe_mutex_unlock(bo
->mgr
->bo_handles_mutex
);
306 os_munmap(bo
->ptr
, bo
->base
.size
);
309 args
.handle
= bo
->handle
;
310 drmIoctl(bo
->rws
->fd
, DRM_IOCTL_GEM_CLOSE
, &args
);
313 radeon_bomgr_free_va(mgr
, bo
->va
, bo
->base
.size
);
316 pipe_mutex_destroy(bo
->map_mutex
);
318 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
319 bo
->rws
->allocated_vram
-= align(bo
->base
.size
, 4096);
320 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
321 bo
->rws
->allocated_gtt
-= align(bo
->base
.size
, 4096);
325 void *radeon_bo_do_map(struct radeon_bo
*bo
)
327 struct drm_radeon_gem_mmap args
= {0};
330 /* Return the pointer if it's already mapped. */
334 /* Map the buffer. */
335 pipe_mutex_lock(bo
->map_mutex
);
336 /* Return the pointer if it's already mapped (in case of a race). */
338 pipe_mutex_unlock(bo
->map_mutex
);
341 args
.handle
= bo
->handle
;
343 args
.size
= (uint64_t)bo
->base
.size
;
344 if (drmCommandWriteRead(bo
->rws
->fd
,
348 pipe_mutex_unlock(bo
->map_mutex
);
349 fprintf(stderr
, "radeon: gem_mmap failed: %p 0x%08X\n",
354 ptr
= os_mmap(0, args
.size
, PROT_READ
|PROT_WRITE
, MAP_SHARED
,
355 bo
->rws
->fd
, args
.addr_ptr
);
356 if (ptr
== MAP_FAILED
) {
357 pipe_mutex_unlock(bo
->map_mutex
);
358 fprintf(stderr
, "radeon: mmap failed, errno: %i\n", errno
);
362 pipe_mutex_unlock(bo
->map_mutex
);
367 static void *radeon_bo_map(struct radeon_winsys_cs_handle
*buf
,
368 struct radeon_winsys_cs
*rcs
,
369 enum pipe_transfer_usage usage
)
371 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
372 struct radeon_drm_cs
*cs
= (struct radeon_drm_cs
*)rcs
;
374 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
375 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
376 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
377 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
378 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
381 * Since we are mapping for read, we don't need to wait
382 * if the GPU is using the buffer for read too
383 * (neither one is changing it).
385 * Only check whether the buffer is being used for write. */
386 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
387 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
391 if (radeon_bo_is_busy((struct pb_buffer
*)bo
,
392 RADEON_USAGE_WRITE
)) {
396 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
397 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
401 if (radeon_bo_is_busy((struct pb_buffer
*)bo
,
402 RADEON_USAGE_READWRITE
)) {
407 uint64_t time
= os_time_get_nano();
409 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
412 * Since we are mapping for read, we don't need to wait
413 * if the GPU is using the buffer for read too
414 * (neither one is changing it).
416 * Only check whether the buffer is being used for write. */
417 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
418 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
420 radeon_bo_wait((struct pb_buffer
*)bo
,
423 /* Mapping for write. */
425 if (radeon_bo_is_referenced_by_cs(cs
, bo
)) {
426 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
428 /* Try to avoid busy-waiting in radeon_bo_wait. */
429 if (p_atomic_read(&bo
->num_active_ioctls
))
430 radeon_drm_cs_sync_flush(rcs
);
434 radeon_bo_wait((struct pb_buffer
*)bo
, RADEON_USAGE_READWRITE
);
437 bo
->mgr
->rws
->buffer_wait_time
+= os_time_get_nano() - time
;
441 return radeon_bo_do_map(bo
);
444 static void radeon_bo_unmap(struct radeon_winsys_cs_handle
*_buf
)
449 static void radeon_bo_get_base_buffer(struct pb_buffer
*buf
,
450 struct pb_buffer
**base_buf
,
457 static enum pipe_error
radeon_bo_validate(struct pb_buffer
*_buf
,
458 struct pb_validate
*vl
,
465 static void radeon_bo_fence(struct pb_buffer
*buf
,
466 struct pipe_fence_handle
*fence
)
470 const struct pb_vtbl radeon_bo_vtbl
= {
472 NULL
, /* never called */
473 NULL
, /* never called */
476 radeon_bo_get_base_buffer
,
479 #ifndef RADEON_GEM_GTT_WC
480 #define RADEON_GEM_GTT_WC (1 << 2)
482 #ifndef RADEON_GEM_CPU_ACCESS
483 /* BO is expected to be accessed by the CPU */
484 #define RADEON_GEM_CPU_ACCESS (1 << 3)
486 #ifndef RADEON_GEM_NO_CPU_ACCESS
487 /* CPU access is not expected to work for this BO */
488 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
491 static struct pb_buffer
*radeon_bomgr_create_bo(struct pb_manager
*_mgr
,
493 const struct pb_desc
*desc
)
495 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
496 struct radeon_drm_winsys
*rws
= mgr
->rws
;
497 struct radeon_bo
*bo
;
498 struct drm_radeon_gem_create args
;
499 struct radeon_bo_desc
*rdesc
= (struct radeon_bo_desc
*)desc
;
502 memset(&args
, 0, sizeof(args
));
504 assert(rdesc
->initial_domains
);
505 assert((rdesc
->initial_domains
&
506 ~(RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
)) == 0);
509 args
.alignment
= desc
->alignment
;
510 args
.initial_domain
= rdesc
->initial_domains
;
513 if (rdesc
->flags
& RADEON_FLAG_GTT_WC
)
514 args
.flags
|= RADEON_GEM_GTT_WC
;
515 if (rdesc
->flags
& RADEON_FLAG_CPU_ACCESS
)
516 args
.flags
|= RADEON_GEM_CPU_ACCESS
;
517 if (rdesc
->flags
& RADEON_FLAG_NO_CPU_ACCESS
)
518 args
.flags
|= RADEON_GEM_NO_CPU_ACCESS
;
520 if (drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_CREATE
,
521 &args
, sizeof(args
))) {
522 fprintf(stderr
, "radeon: Failed to allocate a buffer:\n");
523 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
524 fprintf(stderr
, "radeon: alignment : %d bytes\n", desc
->alignment
);
525 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
526 fprintf(stderr
, "radeon: flags : %d\n", args
.flags
);
530 bo
= CALLOC_STRUCT(radeon_bo
);
534 pipe_reference_init(&bo
->base
.reference
, 1);
535 bo
->base
.alignment
= desc
->alignment
;
536 bo
->base
.usage
= desc
->usage
;
537 bo
->base
.size
= size
;
538 bo
->base
.vtbl
= &radeon_bo_vtbl
;
541 bo
->handle
= args
.handle
;
543 bo
->initial_domain
= rdesc
->initial_domains
;
544 pipe_mutex_init(bo
->map_mutex
);
547 struct drm_radeon_gem_va va
;
549 bo
->va
= radeon_bomgr_find_va(mgr
, size
, desc
->alignment
);
551 va
.handle
= bo
->handle
;
553 va
.operation
= RADEON_VA_MAP
;
554 va
.flags
= RADEON_VM_PAGE_READABLE
|
555 RADEON_VM_PAGE_WRITEABLE
|
556 RADEON_VM_PAGE_SNOOPED
;
558 r
= drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
559 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
560 fprintf(stderr
, "radeon: Failed to allocate virtual address for buffer:\n");
561 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
562 fprintf(stderr
, "radeon: alignment : %d bytes\n", desc
->alignment
);
563 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
564 fprintf(stderr
, "radeon: va : 0x%016llx\n", (unsigned long long)bo
->va
);
565 radeon_bo_destroy(&bo
->base
);
568 pipe_mutex_lock(mgr
->bo_handles_mutex
);
569 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
570 struct pb_buffer
*b
= &bo
->base
;
571 struct radeon_bo
*old_bo
=
572 util_hash_table_get(mgr
->bo_vas
, (void*)(uintptr_t)va
.offset
);
574 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
575 pb_reference(&b
, &old_bo
->base
);
579 util_hash_table_set(mgr
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
580 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
583 if (rdesc
->initial_domains
& RADEON_DOMAIN_VRAM
)
584 rws
->allocated_vram
+= align(size
, 4096);
585 else if (rdesc
->initial_domains
& RADEON_DOMAIN_GTT
)
586 rws
->allocated_gtt
+= align(size
, 4096);
591 static void radeon_bomgr_flush(struct pb_manager
*mgr
)
596 /* This is for the cache bufmgr. */
597 static boolean
radeon_bomgr_is_buffer_busy(struct pb_manager
*_mgr
,
598 struct pb_buffer
*_buf
)
600 struct radeon_bo
*bo
= radeon_bo(_buf
);
602 if (radeon_bo_is_referenced_by_any_cs(bo
)) {
606 if (radeon_bo_is_busy((struct pb_buffer
*)bo
, RADEON_USAGE_READWRITE
)) {
613 static void radeon_bomgr_destroy(struct pb_manager
*_mgr
)
615 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
616 util_hash_table_destroy(mgr
->bo_names
);
617 util_hash_table_destroy(mgr
->bo_handles
);
618 util_hash_table_destroy(mgr
->bo_vas
);
619 pipe_mutex_destroy(mgr
->bo_handles_mutex
);
620 pipe_mutex_destroy(mgr
->bo_va_mutex
);
624 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
626 static unsigned handle_hash(void *key
)
628 return PTR_TO_UINT(key
);
631 static int handle_compare(void *key1
, void *key2
)
633 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
636 struct pb_manager
*radeon_bomgr_create(struct radeon_drm_winsys
*rws
)
638 struct radeon_bomgr
*mgr
;
640 mgr
= CALLOC_STRUCT(radeon_bomgr
);
644 mgr
->base
.destroy
= radeon_bomgr_destroy
;
645 mgr
->base
.create_buffer
= radeon_bomgr_create_bo
;
646 mgr
->base
.flush
= radeon_bomgr_flush
;
647 mgr
->base
.is_buffer_busy
= radeon_bomgr_is_buffer_busy
;
650 mgr
->bo_names
= util_hash_table_create(handle_hash
, handle_compare
);
651 mgr
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
652 mgr
->bo_vas
= util_hash_table_create(handle_hash
, handle_compare
);
653 pipe_mutex_init(mgr
->bo_handles_mutex
);
654 pipe_mutex_init(mgr
->bo_va_mutex
);
656 mgr
->va
= rws
->info
.r600_virtual_address
;
657 mgr
->va_offset
= rws
->va_start
;
658 list_inithead(&mgr
->va_holes
);
663 static unsigned eg_tile_split(unsigned tile_split
)
665 switch (tile_split
) {
666 case 0: tile_split
= 64; break;
667 case 1: tile_split
= 128; break;
668 case 2: tile_split
= 256; break;
669 case 3: tile_split
= 512; break;
671 case 4: tile_split
= 1024; break;
672 case 5: tile_split
= 2048; break;
673 case 6: tile_split
= 4096; break;
678 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
680 switch (eg_tile_split
) {
692 static void radeon_bo_get_tiling(struct pb_buffer
*_buf
,
693 enum radeon_bo_layout
*microtiled
,
694 enum radeon_bo_layout
*macrotiled
,
695 unsigned *bankw
, unsigned *bankh
,
696 unsigned *tile_split
,
697 unsigned *stencil_tile_split
,
701 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
702 struct drm_radeon_gem_set_tiling args
;
704 memset(&args
, 0, sizeof(args
));
706 args
.handle
= bo
->handle
;
708 drmCommandWriteRead(bo
->rws
->fd
,
709 DRM_RADEON_GEM_GET_TILING
,
713 *microtiled
= RADEON_LAYOUT_LINEAR
;
714 *macrotiled
= RADEON_LAYOUT_LINEAR
;
715 if (args
.tiling_flags
& RADEON_TILING_MICRO
)
716 *microtiled
= RADEON_LAYOUT_TILED
;
717 else if (args
.tiling_flags
& RADEON_TILING_MICRO_SQUARE
)
718 *microtiled
= RADEON_LAYOUT_SQUARETILED
;
720 if (args
.tiling_flags
& RADEON_TILING_MACRO
)
721 *macrotiled
= RADEON_LAYOUT_TILED
;
722 if (bankw
&& tile_split
&& stencil_tile_split
&& mtilea
&& tile_split
) {
723 *bankw
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
724 *bankh
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
725 *tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
726 *stencil_tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
;
727 *mtilea
= (args
.tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
728 *tile_split
= eg_tile_split(*tile_split
);
731 *scanout
= bo
->rws
->gen
>= DRV_SI
&& !(args
.tiling_flags
& RADEON_TILING_R600_NO_SCANOUT
);
734 static void radeon_bo_set_tiling(struct pb_buffer
*_buf
,
735 struct radeon_winsys_cs
*rcs
,
736 enum radeon_bo_layout microtiled
,
737 enum radeon_bo_layout macrotiled
,
738 unsigned bankw
, unsigned bankh
,
740 unsigned stencil_tile_split
,
745 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
746 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
747 struct drm_radeon_gem_set_tiling args
;
749 memset(&args
, 0, sizeof(args
));
751 /* Tiling determines how DRM treats the buffer data.
752 * We must flush CS when changing it if the buffer is referenced. */
753 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
754 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
757 while (p_atomic_read(&bo
->num_active_ioctls
)) {
761 if (microtiled
== RADEON_LAYOUT_TILED
)
762 args
.tiling_flags
|= RADEON_TILING_MICRO
;
763 else if (microtiled
== RADEON_LAYOUT_SQUARETILED
)
764 args
.tiling_flags
|= RADEON_TILING_MICRO_SQUARE
;
766 if (macrotiled
== RADEON_LAYOUT_TILED
)
767 args
.tiling_flags
|= RADEON_TILING_MACRO
;
769 args
.tiling_flags
|= (bankw
& RADEON_TILING_EG_BANKW_MASK
) <<
770 RADEON_TILING_EG_BANKW_SHIFT
;
771 args
.tiling_flags
|= (bankh
& RADEON_TILING_EG_BANKH_MASK
) <<
772 RADEON_TILING_EG_BANKH_SHIFT
;
774 args
.tiling_flags
|= (eg_tile_split_rev(tile_split
) &
775 RADEON_TILING_EG_TILE_SPLIT_MASK
) <<
776 RADEON_TILING_EG_TILE_SPLIT_SHIFT
;
778 args
.tiling_flags
|= (stencil_tile_split
&
779 RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
) <<
780 RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
;
781 args
.tiling_flags
|= (mtilea
& RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
) <<
782 RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
;
784 if (bo
->rws
->gen
>= DRV_SI
&& !scanout
)
785 args
.tiling_flags
|= RADEON_TILING_R600_NO_SCANOUT
;
787 args
.handle
= bo
->handle
;
790 drmCommandWriteRead(bo
->rws
->fd
,
791 DRM_RADEON_GEM_SET_TILING
,
796 static struct radeon_winsys_cs_handle
*radeon_drm_get_cs_handle(struct pb_buffer
*_buf
)
798 /* return radeon_bo. */
799 return (struct radeon_winsys_cs_handle
*)get_radeon_bo(_buf
);
802 static struct pb_buffer
*
803 radeon_winsys_bo_create(struct radeon_winsys
*rws
,
806 boolean use_reusable_pool
,
807 enum radeon_bo_domain domain
,
808 enum radeon_bo_flag flags
)
810 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
811 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
812 struct radeon_bo_desc desc
;
813 struct pb_manager
*provider
;
814 struct pb_buffer
*buffer
;
816 memset(&desc
, 0, sizeof(desc
));
817 desc
.base
.alignment
= alignment
;
819 /* Only set one usage bit each for domains and flags, or the cache manager
820 * might consider different sets of domains / flags compatible
822 if (domain
== RADEON_DOMAIN_VRAM_GTT
)
823 desc
.base
.usage
= 1 << 2;
825 desc
.base
.usage
= domain
>> 1;
826 assert(flags
< sizeof(desc
.base
.usage
) * 8 - 3);
827 desc
.base
.usage
|= 1 << (flags
+ 3);
829 desc
.initial_domains
= domain
;
832 /* Assign a buffer manager. */
833 if (use_reusable_pool
)
838 buffer
= provider
->create_buffer(provider
, size
, &desc
.base
);
842 pipe_mutex_lock(mgr
->bo_handles_mutex
);
843 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)get_radeon_bo(buffer
)->handle
, buffer
);
844 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
846 return (struct pb_buffer
*)buffer
;
849 static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys
*rws
,
850 struct winsys_handle
*whandle
,
853 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
854 struct radeon_bo
*bo
;
855 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
860 /* We must maintain a list of pairs <handle, bo>, so that we always return
861 * the same BO for one particular handle. If we didn't do that and created
862 * more than one BO for the same handle and then relocated them in a CS,
863 * we would hit a deadlock in the kernel.
865 * The list of pairs is guarded by a mutex, of course. */
866 pipe_mutex_lock(mgr
->bo_handles_mutex
);
868 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
869 /* First check if there already is an existing bo for the handle. */
870 bo
= util_hash_table_get(mgr
->bo_names
, (void*)(uintptr_t)whandle
->handle
);
871 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
872 /* We must first get the GEM handle, as fds are unreliable keys */
873 r
= drmPrimeFDToHandle(ws
->fd
, whandle
->handle
, &handle
);
876 bo
= util_hash_table_get(mgr
->bo_handles
, (void*)(uintptr_t)handle
);
878 /* Unknown handle type */
883 /* Increase the refcount. */
884 struct pb_buffer
*b
= NULL
;
885 pb_reference(&b
, &bo
->base
);
889 /* There isn't, create a new one. */
890 bo
= CALLOC_STRUCT(radeon_bo
);
895 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
896 struct drm_gem_open open_arg
= {};
897 memset(&open_arg
, 0, sizeof(open_arg
));
899 open_arg
.name
= whandle
->handle
;
900 if (drmIoctl(ws
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
)) {
904 handle
= open_arg
.handle
;
905 size
= open_arg
.size
;
906 bo
->flink_name
= whandle
->handle
;
907 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
908 size
= lseek(whandle
->handle
, 0, SEEK_END
);
910 * Could check errno to determine whether the kernel is new enough, but
911 * it doesn't really matter why this failed, just that it failed.
913 if (size
== (off_t
)-1) {
917 lseek(whandle
->handle
, 0, SEEK_SET
);
923 pipe_reference_init(&bo
->base
.reference
, 1);
924 bo
->base
.alignment
= 0;
925 bo
->base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
926 bo
->base
.size
= (unsigned) size
;
927 bo
->base
.vtbl
= &radeon_bo_vtbl
;
931 pipe_mutex_init(bo
->map_mutex
);
934 util_hash_table_set(mgr
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
936 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
939 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
942 *stride
= whandle
->stride
;
944 if (mgr
->va
&& !bo
->va
) {
945 struct drm_radeon_gem_va va
;
947 bo
->va
= radeon_bomgr_find_va(mgr
, bo
->base
.size
, 1 << 20);
949 va
.handle
= bo
->handle
;
950 va
.operation
= RADEON_VA_MAP
;
953 va
.flags
= RADEON_VM_PAGE_READABLE
|
954 RADEON_VM_PAGE_WRITEABLE
|
955 RADEON_VM_PAGE_SNOOPED
;
957 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
958 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
959 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
960 radeon_bo_destroy(&bo
->base
);
963 pipe_mutex_lock(mgr
->bo_handles_mutex
);
964 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
965 struct pb_buffer
*b
= &bo
->base
;
966 struct radeon_bo
*old_bo
=
967 util_hash_table_get(mgr
->bo_vas
, (void*)(uintptr_t)va
.offset
);
969 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
970 pb_reference(&b
, &old_bo
->base
);
974 util_hash_table_set(mgr
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
975 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
978 bo
->initial_domain
= radeon_bo_get_initial_domain((void*)bo
);
980 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
981 ws
->allocated_vram
+= align(bo
->base
.size
, 4096);
982 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
983 ws
->allocated_gtt
+= align(bo
->base
.size
, 4096);
985 return (struct pb_buffer
*)bo
;
988 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
992 static boolean
radeon_winsys_bo_get_handle(struct pb_buffer
*buffer
,
994 struct winsys_handle
*whandle
)
996 struct drm_gem_flink flink
;
997 struct radeon_bo
*bo
= get_radeon_bo(buffer
);
999 memset(&flink
, 0, sizeof(flink
));
1001 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
1002 if (!bo
->flink_name
) {
1003 flink
.handle
= bo
->handle
;
1005 if (ioctl(bo
->rws
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
)) {
1009 bo
->flink_name
= flink
.name
;
1011 pipe_mutex_lock(bo
->mgr
->bo_handles_mutex
);
1012 util_hash_table_set(bo
->mgr
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
1013 pipe_mutex_unlock(bo
->mgr
->bo_handles_mutex
);
1015 whandle
->handle
= bo
->flink_name
;
1016 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
1017 whandle
->handle
= bo
->handle
;
1018 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
1019 if (drmPrimeHandleToFD(bo
->rws
->fd
, bo
->handle
, DRM_CLOEXEC
, (int*)&whandle
->handle
))
1023 whandle
->stride
= stride
;
1027 static uint64_t radeon_winsys_bo_va(struct radeon_winsys_cs_handle
*buf
)
1029 return ((struct radeon_bo
*)buf
)->va
;
1032 void radeon_bomgr_init_functions(struct radeon_drm_winsys
*ws
)
1034 ws
->base
.buffer_get_cs_handle
= radeon_drm_get_cs_handle
;
1035 ws
->base
.buffer_set_tiling
= radeon_bo_set_tiling
;
1036 ws
->base
.buffer_get_tiling
= radeon_bo_get_tiling
;
1037 ws
->base
.buffer_map
= radeon_bo_map
;
1038 ws
->base
.buffer_unmap
= radeon_bo_unmap
;
1039 ws
->base
.buffer_wait
= radeon_bo_wait
;
1040 ws
->base
.buffer_is_busy
= radeon_bo_is_busy
;
1041 ws
->base
.buffer_create
= radeon_winsys_bo_create
;
1042 ws
->base
.buffer_from_handle
= radeon_winsys_bo_from_handle
;
1043 ws
->base
.buffer_get_handle
= radeon_winsys_bo_get_handle
;
1044 ws
->base
.buffer_get_virtual_address
= radeon_winsys_bo_va
;
1045 ws
->base
.buffer_get_initial_domain
= radeon_bo_get_initial_domain
;