2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
27 #include "radeon_drm_cs.h"
29 #include "util/u_hash_table.h"
30 #include "util/u_memory.h"
31 #include "util/simple_list.h"
32 #include "util/list.h"
33 #include "os/os_thread.h"
34 #include "os/os_mman.h"
35 #include "os/os_time.h"
37 #include "state_tracker/drm_driver.h"
39 #include <sys/ioctl.h>
45 static const struct pb_vtbl radeon_bo_vtbl
;
47 static inline struct radeon_bo
*radeon_bo(struct pb_buffer
*bo
)
49 assert(bo
->vtbl
== &radeon_bo_vtbl
);
50 return (struct radeon_bo
*)bo
;
53 struct radeon_bo_va_hole
{
54 struct list_head list
;
61 struct pb_manager base
;
64 struct radeon_drm_winsys
*rws
;
66 /* List of buffer GEM names. Protected by bo_handles_mutex. */
67 struct util_hash_table
*bo_names
;
68 /* List of buffer handles. Protectded by bo_handles_mutex. */
69 struct util_hash_table
*bo_handles
;
70 /* List of buffer virtual memory ranges. Protectded by bo_handles_mutex. */
71 struct util_hash_table
*bo_vas
;
72 pipe_mutex bo_handles_mutex
;
73 pipe_mutex bo_va_mutex
;
75 /* is virtual address supported */
78 struct list_head va_holes
;
81 static inline struct radeon_bomgr
*radeon_bomgr(struct pb_manager
*mgr
)
83 return (struct radeon_bomgr
*)mgr
;
86 static struct radeon_bo
*get_radeon_bo(struct pb_buffer
*_buf
)
88 struct radeon_bo
*bo
= NULL
;
90 if (_buf
->vtbl
== &radeon_bo_vtbl
) {
93 struct pb_buffer
*base_buf
;
95 pb_get_base_buffer(_buf
, &base_buf
, &offset
);
97 if (base_buf
->vtbl
== &radeon_bo_vtbl
)
98 bo
= radeon_bo(base_buf
);
104 static bool radeon_bo_is_busy(struct radeon_bo
*bo
)
106 struct drm_radeon_gem_busy args
= {0};
108 args
.handle
= bo
->handle
;
109 return drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_BUSY
,
110 &args
, sizeof(args
)) != 0;
113 static void radeon_bo_wait_idle(struct radeon_bo
*bo
)
115 struct drm_radeon_gem_wait_idle args
= {0};
117 args
.handle
= bo
->handle
;
118 while (drmCommandWrite(bo
->rws
->fd
, DRM_RADEON_GEM_WAIT_IDLE
,
119 &args
, sizeof(args
)) == -EBUSY
);
122 static bool radeon_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
123 enum radeon_bo_usage usage
)
125 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
128 /* No timeout. Just query. */
130 return !bo
->num_active_ioctls
&& !radeon_bo_is_busy(bo
);
132 abs_timeout
= os_time_get_absolute_timeout(timeout
);
134 /* Wait if any ioctl is being submitted with this buffer. */
135 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
138 /* Infinite timeout. */
139 if (abs_timeout
== PIPE_TIMEOUT_INFINITE
) {
140 radeon_bo_wait_idle(bo
);
144 /* Other timeouts need to be emulated with a loop. */
145 while (radeon_bo_is_busy(bo
)) {
146 if (os_time_get_nano() >= abs_timeout
)
154 static enum radeon_bo_domain
get_valid_domain(enum radeon_bo_domain domain
)
156 /* Zero domains the driver doesn't understand. */
157 domain
&= RADEON_DOMAIN_VRAM_GTT
;
159 /* If no domain is set, we must set something... */
161 domain
= RADEON_DOMAIN_VRAM_GTT
;
166 static enum radeon_bo_domain
radeon_bo_get_initial_domain(
167 struct radeon_winsys_cs_handle
*buf
)
169 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
170 struct drm_radeon_gem_op args
;
172 if (bo
->rws
->info
.drm_minor
< 38)
173 return RADEON_DOMAIN_VRAM_GTT
;
175 memset(&args
, 0, sizeof(args
));
176 args
.handle
= bo
->handle
;
177 args
.op
= RADEON_GEM_OP_GET_INITIAL_DOMAIN
;
179 drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_OP
,
180 &args
, sizeof(args
));
182 /* GEM domains and winsys domains are defined the same. */
183 return get_valid_domain(args
.value
);
186 static uint64_t radeon_bomgr_find_va(struct radeon_bomgr
*mgr
, uint64_t size
, uint64_t alignment
)
188 struct radeon_bo_va_hole
*hole
, *n
;
189 uint64_t offset
= 0, waste
= 0;
191 alignment
= MAX2(alignment
, 4096);
192 size
= align(size
, 4096);
194 pipe_mutex_lock(mgr
->bo_va_mutex
);
195 /* first look for a hole */
196 LIST_FOR_EACH_ENTRY_SAFE(hole
, n
, &mgr
->va_holes
, list
) {
197 offset
= hole
->offset
;
198 waste
= offset
% alignment
;
199 waste
= waste
? alignment
- waste
: 0;
201 if (offset
>= (hole
->offset
+ hole
->size
)) {
204 if (!waste
&& hole
->size
== size
) {
205 offset
= hole
->offset
;
206 list_del(&hole
->list
);
208 pipe_mutex_unlock(mgr
->bo_va_mutex
);
211 if ((hole
->size
- waste
) > size
) {
213 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
215 n
->offset
= hole
->offset
;
216 list_add(&n
->list
, &hole
->list
);
218 hole
->size
-= (size
+ waste
);
219 hole
->offset
+= size
+ waste
;
220 pipe_mutex_unlock(mgr
->bo_va_mutex
);
223 if ((hole
->size
- waste
) == size
) {
225 pipe_mutex_unlock(mgr
->bo_va_mutex
);
230 offset
= mgr
->va_offset
;
231 waste
= offset
% alignment
;
232 waste
= waste
? alignment
- waste
: 0;
234 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
237 list_add(&n
->list
, &mgr
->va_holes
);
240 mgr
->va_offset
+= size
+ waste
;
241 pipe_mutex_unlock(mgr
->bo_va_mutex
);
245 static void radeon_bomgr_free_va(struct radeon_bomgr
*mgr
, uint64_t va
, uint64_t size
)
247 struct radeon_bo_va_hole
*hole
;
249 size
= align(size
, 4096);
251 pipe_mutex_lock(mgr
->bo_va_mutex
);
252 if ((va
+ size
) == mgr
->va_offset
) {
254 /* Delete uppermost hole if it reaches the new top */
255 if (!LIST_IS_EMPTY(&mgr
->va_holes
)) {
256 hole
= container_of(mgr
->va_holes
.next
, hole
, list
);
257 if ((hole
->offset
+ hole
->size
) == va
) {
258 mgr
->va_offset
= hole
->offset
;
259 list_del(&hole
->list
);
264 struct radeon_bo_va_hole
*next
;
266 hole
= container_of(&mgr
->va_holes
, hole
, list
);
267 LIST_FOR_EACH_ENTRY(next
, &mgr
->va_holes
, list
) {
268 if (next
->offset
< va
)
273 if (&hole
->list
!= &mgr
->va_holes
) {
274 /* Grow upper hole if it's adjacent */
275 if (hole
->offset
== (va
+ size
)) {
278 /* Merge lower hole if it's adjacent */
279 if (next
!= hole
&& &next
->list
!= &mgr
->va_holes
&&
280 (next
->offset
+ next
->size
) == va
) {
281 next
->size
+= hole
->size
;
282 list_del(&hole
->list
);
289 /* Grow lower hole if it's adjacent */
290 if (next
!= hole
&& &next
->list
!= &mgr
->va_holes
&&
291 (next
->offset
+ next
->size
) == va
) {
296 /* FIXME on allocation failure we just lose virtual address space
297 * maybe print a warning
299 next
= CALLOC_STRUCT(radeon_bo_va_hole
);
303 list_add(&next
->list
, &hole
->list
);
307 pipe_mutex_unlock(mgr
->bo_va_mutex
);
310 static void radeon_bo_destroy(struct pb_buffer
*_buf
)
312 struct radeon_bo
*bo
= radeon_bo(_buf
);
313 struct radeon_bomgr
*mgr
= bo
->mgr
;
314 struct drm_gem_close args
;
316 memset(&args
, 0, sizeof(args
));
318 pipe_mutex_lock(bo
->mgr
->bo_handles_mutex
);
319 util_hash_table_remove(bo
->mgr
->bo_handles
, (void*)(uintptr_t)bo
->handle
);
320 if (bo
->flink_name
) {
321 util_hash_table_remove(bo
->mgr
->bo_names
,
322 (void*)(uintptr_t)bo
->flink_name
);
324 pipe_mutex_unlock(bo
->mgr
->bo_handles_mutex
);
327 os_munmap(bo
->ptr
, bo
->base
.size
);
330 if (bo
->rws
->va_unmap_working
) {
331 struct drm_radeon_gem_va va
;
333 va
.handle
= bo
->handle
;
335 va
.operation
= RADEON_VA_UNMAP
;
336 va
.flags
= RADEON_VM_PAGE_READABLE
|
337 RADEON_VM_PAGE_WRITEABLE
|
338 RADEON_VM_PAGE_SNOOPED
;
341 if (drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_VA
, &va
,
343 va
.operation
== RADEON_VA_RESULT_ERROR
) {
344 fprintf(stderr
, "radeon: Failed to deallocate virtual address for buffer:\n");
345 fprintf(stderr
, "radeon: size : %d bytes\n", bo
->base
.size
);
346 fprintf(stderr
, "radeon: va : 0x%016llx\n", (unsigned long long)bo
->va
);
350 radeon_bomgr_free_va(mgr
, bo
->va
, bo
->base
.size
);
354 args
.handle
= bo
->handle
;
355 drmIoctl(bo
->rws
->fd
, DRM_IOCTL_GEM_CLOSE
, &args
);
357 pipe_mutex_destroy(bo
->map_mutex
);
359 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
360 bo
->rws
->allocated_vram
-= align(bo
->base
.size
, 4096);
361 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
362 bo
->rws
->allocated_gtt
-= align(bo
->base
.size
, 4096);
366 void *radeon_bo_do_map(struct radeon_bo
*bo
)
368 struct drm_radeon_gem_mmap args
= {0};
371 /* If the buffer is created from user memory, return the user pointer. */
375 /* Map the buffer. */
376 pipe_mutex_lock(bo
->map_mutex
);
377 /* Return the pointer if it's already mapped. */
380 pipe_mutex_unlock(bo
->map_mutex
);
383 args
.handle
= bo
->handle
;
385 args
.size
= (uint64_t)bo
->base
.size
;
386 if (drmCommandWriteRead(bo
->rws
->fd
,
390 pipe_mutex_unlock(bo
->map_mutex
);
391 fprintf(stderr
, "radeon: gem_mmap failed: %p 0x%08X\n",
396 ptr
= os_mmap(0, args
.size
, PROT_READ
|PROT_WRITE
, MAP_SHARED
,
397 bo
->rws
->fd
, args
.addr_ptr
);
398 if (ptr
== MAP_FAILED
) {
399 pipe_mutex_unlock(bo
->map_mutex
);
400 fprintf(stderr
, "radeon: mmap failed, errno: %i\n", errno
);
405 pipe_mutex_unlock(bo
->map_mutex
);
410 static void *radeon_bo_map(struct radeon_winsys_cs_handle
*buf
,
411 struct radeon_winsys_cs
*rcs
,
412 enum pipe_transfer_usage usage
)
414 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
415 struct radeon_drm_cs
*cs
= (struct radeon_drm_cs
*)rcs
;
417 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
418 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
419 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
420 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
421 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
424 * Since we are mapping for read, we don't need to wait
425 * if the GPU is using the buffer for read too
426 * (neither one is changing it).
428 * Only check whether the buffer is being used for write. */
429 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
430 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
434 if (!radeon_bo_wait((struct pb_buffer
*)bo
, 0,
435 RADEON_USAGE_WRITE
)) {
439 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
440 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
444 if (!radeon_bo_wait((struct pb_buffer
*)bo
, 0,
445 RADEON_USAGE_READWRITE
)) {
450 uint64_t time
= os_time_get_nano();
452 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
455 * Since we are mapping for read, we don't need to wait
456 * if the GPU is using the buffer for read too
457 * (neither one is changing it).
459 * Only check whether the buffer is being used for write. */
460 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
461 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
463 radeon_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
466 /* Mapping for write. */
468 if (radeon_bo_is_referenced_by_cs(cs
, bo
)) {
469 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
471 /* Try to avoid busy-waiting in radeon_bo_wait. */
472 if (p_atomic_read(&bo
->num_active_ioctls
))
473 radeon_drm_cs_sync_flush(rcs
);
477 radeon_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
478 RADEON_USAGE_READWRITE
);
481 bo
->mgr
->rws
->buffer_wait_time
+= os_time_get_nano() - time
;
485 return radeon_bo_do_map(bo
);
488 static void radeon_bo_unmap(struct radeon_winsys_cs_handle
*_buf
)
490 struct radeon_bo
*bo
= (struct radeon_bo
*)_buf
;
495 pipe_mutex_lock(bo
->map_mutex
);
497 pipe_mutex_unlock(bo
->map_mutex
);
498 return; /* it's not been mapped */
501 assert(bo
->map_count
);
502 if (--bo
->map_count
) {
503 pipe_mutex_unlock(bo
->map_mutex
);
504 return; /* it's been mapped multiple times */
507 os_munmap(bo
->ptr
, bo
->base
.size
);
509 pipe_mutex_unlock(bo
->map_mutex
);
512 static void radeon_bo_get_base_buffer(struct pb_buffer
*buf
,
513 struct pb_buffer
**base_buf
,
520 static enum pipe_error
radeon_bo_validate(struct pb_buffer
*_buf
,
521 struct pb_validate
*vl
,
528 static void radeon_bo_fence(struct pb_buffer
*buf
,
529 struct pipe_fence_handle
*fence
)
533 static const struct pb_vtbl radeon_bo_vtbl
= {
535 NULL
, /* never called */
536 NULL
, /* never called */
539 radeon_bo_get_base_buffer
,
542 #ifndef RADEON_GEM_GTT_WC
543 #define RADEON_GEM_GTT_WC (1 << 2)
545 #ifndef RADEON_GEM_CPU_ACCESS
546 /* BO is expected to be accessed by the CPU */
547 #define RADEON_GEM_CPU_ACCESS (1 << 3)
549 #ifndef RADEON_GEM_NO_CPU_ACCESS
550 /* CPU access is not expected to work for this BO */
551 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
554 static struct pb_buffer
*radeon_bomgr_create_bo(struct pb_manager
*_mgr
,
556 const struct pb_desc
*desc
)
558 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
559 struct radeon_drm_winsys
*rws
= mgr
->rws
;
560 struct radeon_bo
*bo
;
561 struct drm_radeon_gem_create args
;
562 struct radeon_bo_desc
*rdesc
= (struct radeon_bo_desc
*)desc
;
565 memset(&args
, 0, sizeof(args
));
567 assert(rdesc
->initial_domains
);
568 assert((rdesc
->initial_domains
&
569 ~(RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
)) == 0);
572 args
.alignment
= desc
->alignment
;
573 args
.initial_domain
= rdesc
->initial_domains
;
576 if (rdesc
->flags
& RADEON_FLAG_GTT_WC
)
577 args
.flags
|= RADEON_GEM_GTT_WC
;
578 if (rdesc
->flags
& RADEON_FLAG_CPU_ACCESS
)
579 args
.flags
|= RADEON_GEM_CPU_ACCESS
;
580 if (rdesc
->flags
& RADEON_FLAG_NO_CPU_ACCESS
)
581 args
.flags
|= RADEON_GEM_NO_CPU_ACCESS
;
583 if (drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_CREATE
,
584 &args
, sizeof(args
))) {
585 fprintf(stderr
, "radeon: Failed to allocate a buffer:\n");
586 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
587 fprintf(stderr
, "radeon: alignment : %d bytes\n", desc
->alignment
);
588 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
589 fprintf(stderr
, "radeon: flags : %d\n", args
.flags
);
593 bo
= CALLOC_STRUCT(radeon_bo
);
597 pipe_reference_init(&bo
->base
.reference
, 1);
598 bo
->base
.alignment
= desc
->alignment
;
599 bo
->base
.usage
= desc
->usage
;
600 bo
->base
.size
= size
;
601 bo
->base
.vtbl
= &radeon_bo_vtbl
;
604 bo
->handle
= args
.handle
;
606 bo
->initial_domain
= rdesc
->initial_domains
;
607 pipe_mutex_init(bo
->map_mutex
);
610 struct drm_radeon_gem_va va
;
612 bo
->va
= radeon_bomgr_find_va(mgr
, size
, desc
->alignment
);
614 va
.handle
= bo
->handle
;
616 va
.operation
= RADEON_VA_MAP
;
617 va
.flags
= RADEON_VM_PAGE_READABLE
|
618 RADEON_VM_PAGE_WRITEABLE
|
619 RADEON_VM_PAGE_SNOOPED
;
621 r
= drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
622 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
623 fprintf(stderr
, "radeon: Failed to allocate virtual address for buffer:\n");
624 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
625 fprintf(stderr
, "radeon: alignment : %d bytes\n", desc
->alignment
);
626 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
627 fprintf(stderr
, "radeon: va : 0x%016llx\n", (unsigned long long)bo
->va
);
628 radeon_bo_destroy(&bo
->base
);
631 pipe_mutex_lock(mgr
->bo_handles_mutex
);
632 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
633 struct pb_buffer
*b
= &bo
->base
;
634 struct radeon_bo
*old_bo
=
635 util_hash_table_get(mgr
->bo_vas
, (void*)(uintptr_t)va
.offset
);
637 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
638 pb_reference(&b
, &old_bo
->base
);
642 util_hash_table_set(mgr
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
643 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
646 if (rdesc
->initial_domains
& RADEON_DOMAIN_VRAM
)
647 rws
->allocated_vram
+= align(size
, 4096);
648 else if (rdesc
->initial_domains
& RADEON_DOMAIN_GTT
)
649 rws
->allocated_gtt
+= align(size
, 4096);
654 static void radeon_bomgr_flush(struct pb_manager
*mgr
)
659 /* This is for the cache bufmgr. */
660 static boolean
radeon_bomgr_is_buffer_busy(struct pb_manager
*_mgr
,
661 struct pb_buffer
*_buf
)
663 struct radeon_bo
*bo
= radeon_bo(_buf
);
665 if (radeon_bo_is_referenced_by_any_cs(bo
)) {
669 if (!radeon_bo_wait((struct pb_buffer
*)bo
, 0, RADEON_USAGE_READWRITE
)) {
676 static void radeon_bomgr_destroy(struct pb_manager
*_mgr
)
678 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
679 util_hash_table_destroy(mgr
->bo_names
);
680 util_hash_table_destroy(mgr
->bo_handles
);
681 util_hash_table_destroy(mgr
->bo_vas
);
682 pipe_mutex_destroy(mgr
->bo_handles_mutex
);
683 pipe_mutex_destroy(mgr
->bo_va_mutex
);
687 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
689 static unsigned handle_hash(void *key
)
691 return PTR_TO_UINT(key
);
694 static int handle_compare(void *key1
, void *key2
)
696 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
699 struct pb_manager
*radeon_bomgr_create(struct radeon_drm_winsys
*rws
)
701 struct radeon_bomgr
*mgr
;
703 mgr
= CALLOC_STRUCT(radeon_bomgr
);
707 mgr
->base
.destroy
= radeon_bomgr_destroy
;
708 mgr
->base
.create_buffer
= radeon_bomgr_create_bo
;
709 mgr
->base
.flush
= radeon_bomgr_flush
;
710 mgr
->base
.is_buffer_busy
= radeon_bomgr_is_buffer_busy
;
713 mgr
->bo_names
= util_hash_table_create(handle_hash
, handle_compare
);
714 mgr
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
715 mgr
->bo_vas
= util_hash_table_create(handle_hash
, handle_compare
);
716 pipe_mutex_init(mgr
->bo_handles_mutex
);
717 pipe_mutex_init(mgr
->bo_va_mutex
);
719 mgr
->va
= rws
->info
.r600_virtual_address
;
720 mgr
->va_offset
= rws
->va_start
;
721 list_inithead(&mgr
->va_holes
);
726 static unsigned eg_tile_split(unsigned tile_split
)
728 switch (tile_split
) {
729 case 0: tile_split
= 64; break;
730 case 1: tile_split
= 128; break;
731 case 2: tile_split
= 256; break;
732 case 3: tile_split
= 512; break;
734 case 4: tile_split
= 1024; break;
735 case 5: tile_split
= 2048; break;
736 case 6: tile_split
= 4096; break;
741 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
743 switch (eg_tile_split
) {
755 static void radeon_bo_get_tiling(struct pb_buffer
*_buf
,
756 enum radeon_bo_layout
*microtiled
,
757 enum radeon_bo_layout
*macrotiled
,
758 unsigned *bankw
, unsigned *bankh
,
759 unsigned *tile_split
,
760 unsigned *stencil_tile_split
,
764 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
765 struct drm_radeon_gem_set_tiling args
;
767 memset(&args
, 0, sizeof(args
));
769 args
.handle
= bo
->handle
;
771 drmCommandWriteRead(bo
->rws
->fd
,
772 DRM_RADEON_GEM_GET_TILING
,
776 *microtiled
= RADEON_LAYOUT_LINEAR
;
777 *macrotiled
= RADEON_LAYOUT_LINEAR
;
778 if (args
.tiling_flags
& RADEON_TILING_MICRO
)
779 *microtiled
= RADEON_LAYOUT_TILED
;
780 else if (args
.tiling_flags
& RADEON_TILING_MICRO_SQUARE
)
781 *microtiled
= RADEON_LAYOUT_SQUARETILED
;
783 if (args
.tiling_flags
& RADEON_TILING_MACRO
)
784 *macrotiled
= RADEON_LAYOUT_TILED
;
785 if (bankw
&& tile_split
&& stencil_tile_split
&& mtilea
&& tile_split
) {
786 *bankw
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
787 *bankh
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
788 *tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
789 *stencil_tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
;
790 *mtilea
= (args
.tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
791 *tile_split
= eg_tile_split(*tile_split
);
794 *scanout
= bo
->rws
->gen
>= DRV_SI
&& !(args
.tiling_flags
& RADEON_TILING_R600_NO_SCANOUT
);
797 static void radeon_bo_set_tiling(struct pb_buffer
*_buf
,
798 struct radeon_winsys_cs
*rcs
,
799 enum radeon_bo_layout microtiled
,
800 enum radeon_bo_layout macrotiled
,
801 unsigned pipe_config
,
802 unsigned bankw
, unsigned bankh
,
804 unsigned stencil_tile_split
,
805 unsigned mtilea
, unsigned num_banks
,
809 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
810 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
811 struct drm_radeon_gem_set_tiling args
;
813 memset(&args
, 0, sizeof(args
));
815 /* Tiling determines how DRM treats the buffer data.
816 * We must flush CS when changing it if the buffer is referenced. */
817 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
818 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
821 os_wait_until_zero(&bo
->num_active_ioctls
, PIPE_TIMEOUT_INFINITE
);
823 if (microtiled
== RADEON_LAYOUT_TILED
)
824 args
.tiling_flags
|= RADEON_TILING_MICRO
;
825 else if (microtiled
== RADEON_LAYOUT_SQUARETILED
)
826 args
.tiling_flags
|= RADEON_TILING_MICRO_SQUARE
;
828 if (macrotiled
== RADEON_LAYOUT_TILED
)
829 args
.tiling_flags
|= RADEON_TILING_MACRO
;
831 args
.tiling_flags
|= (bankw
& RADEON_TILING_EG_BANKW_MASK
) <<
832 RADEON_TILING_EG_BANKW_SHIFT
;
833 args
.tiling_flags
|= (bankh
& RADEON_TILING_EG_BANKH_MASK
) <<
834 RADEON_TILING_EG_BANKH_SHIFT
;
836 args
.tiling_flags
|= (eg_tile_split_rev(tile_split
) &
837 RADEON_TILING_EG_TILE_SPLIT_MASK
) <<
838 RADEON_TILING_EG_TILE_SPLIT_SHIFT
;
840 args
.tiling_flags
|= (stencil_tile_split
&
841 RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
) <<
842 RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
;
843 args
.tiling_flags
|= (mtilea
& RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
) <<
844 RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
;
846 if (bo
->rws
->gen
>= DRV_SI
&& !scanout
)
847 args
.tiling_flags
|= RADEON_TILING_R600_NO_SCANOUT
;
849 args
.handle
= bo
->handle
;
852 drmCommandWriteRead(bo
->rws
->fd
,
853 DRM_RADEON_GEM_SET_TILING
,
858 static struct radeon_winsys_cs_handle
*radeon_drm_get_cs_handle(struct pb_buffer
*_buf
)
860 /* return radeon_bo. */
861 return (struct radeon_winsys_cs_handle
*)get_radeon_bo(_buf
);
864 static struct pb_buffer
*
865 radeon_winsys_bo_create(struct radeon_winsys
*rws
,
868 boolean use_reusable_pool
,
869 enum radeon_bo_domain domain
,
870 enum radeon_bo_flag flags
)
872 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
873 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
874 struct radeon_bo_desc desc
;
875 struct pb_manager
*provider
;
876 struct pb_buffer
*buffer
;
878 memset(&desc
, 0, sizeof(desc
));
879 desc
.base
.alignment
= alignment
;
881 /* Align size to page size. This is the minimum alignment for normal
882 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
883 * like constant/uniform buffers, can benefit from better and more reuse.
885 size
= align(size
, 4096);
887 /* Only set one usage bit each for domains and flags, or the cache manager
888 * might consider different sets of domains / flags compatible
890 if (domain
== RADEON_DOMAIN_VRAM_GTT
)
891 desc
.base
.usage
= 1 << 2;
893 desc
.base
.usage
= domain
>> 1;
894 assert(flags
< sizeof(desc
.base
.usage
) * 8 - 3);
895 desc
.base
.usage
|= 1 << (flags
+ 3);
897 desc
.initial_domains
= domain
;
900 /* Assign a buffer manager. */
901 if (use_reusable_pool
)
906 buffer
= provider
->create_buffer(provider
, size
, &desc
.base
);
910 pipe_mutex_lock(mgr
->bo_handles_mutex
);
911 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)get_radeon_bo(buffer
)->handle
, buffer
);
912 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
914 return (struct pb_buffer
*)buffer
;
917 static struct pb_buffer
*radeon_winsys_bo_from_ptr(struct radeon_winsys
*rws
,
918 void *pointer
, unsigned size
)
920 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
921 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
922 struct drm_radeon_gem_userptr args
;
923 struct radeon_bo
*bo
;
926 bo
= CALLOC_STRUCT(radeon_bo
);
930 memset(&args
, 0, sizeof(args
));
931 args
.addr
= (uintptr_t)pointer
;
932 args
.size
= align(size
, sysconf(_SC_PAGE_SIZE
));
933 args
.flags
= RADEON_GEM_USERPTR_ANONONLY
|
934 RADEON_GEM_USERPTR_VALIDATE
|
935 RADEON_GEM_USERPTR_REGISTER
;
936 if (drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_USERPTR
,
937 &args
, sizeof(args
))) {
942 pipe_mutex_lock(mgr
->bo_handles_mutex
);
945 pipe_reference_init(&bo
->base
.reference
, 1);
946 bo
->handle
= args
.handle
;
947 bo
->base
.alignment
= 0;
948 bo
->base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
949 bo
->base
.size
= size
;
950 bo
->base
.vtbl
= &radeon_bo_vtbl
;
953 bo
->user_ptr
= pointer
;
955 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
956 pipe_mutex_init(bo
->map_mutex
);
958 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
960 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
963 struct drm_radeon_gem_va va
;
965 bo
->va
= radeon_bomgr_find_va(mgr
, bo
->base
.size
, 1 << 20);
967 va
.handle
= bo
->handle
;
968 va
.operation
= RADEON_VA_MAP
;
971 va
.flags
= RADEON_VM_PAGE_READABLE
|
972 RADEON_VM_PAGE_WRITEABLE
|
973 RADEON_VM_PAGE_SNOOPED
;
975 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
976 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
977 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
978 radeon_bo_destroy(&bo
->base
);
981 pipe_mutex_lock(mgr
->bo_handles_mutex
);
982 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
983 struct pb_buffer
*b
= &bo
->base
;
984 struct radeon_bo
*old_bo
=
985 util_hash_table_get(mgr
->bo_vas
, (void*)(uintptr_t)va
.offset
);
987 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
988 pb_reference(&b
, &old_bo
->base
);
992 util_hash_table_set(mgr
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
993 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
996 ws
->allocated_gtt
+= align(bo
->base
.size
, 4096);
998 return (struct pb_buffer
*)bo
;
1001 static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys
*rws
,
1002 struct winsys_handle
*whandle
,
1005 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
1006 struct radeon_bo
*bo
;
1007 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
1012 /* We must maintain a list of pairs <handle, bo>, so that we always return
1013 * the same BO for one particular handle. If we didn't do that and created
1014 * more than one BO for the same handle and then relocated them in a CS,
1015 * we would hit a deadlock in the kernel.
1017 * The list of pairs is guarded by a mutex, of course. */
1018 pipe_mutex_lock(mgr
->bo_handles_mutex
);
1020 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
1021 /* First check if there already is an existing bo for the handle. */
1022 bo
= util_hash_table_get(mgr
->bo_names
, (void*)(uintptr_t)whandle
->handle
);
1023 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
1024 /* We must first get the GEM handle, as fds are unreliable keys */
1025 r
= drmPrimeFDToHandle(ws
->fd
, whandle
->handle
, &handle
);
1028 bo
= util_hash_table_get(mgr
->bo_handles
, (void*)(uintptr_t)handle
);
1030 /* Unknown handle type */
1035 /* Increase the refcount. */
1036 struct pb_buffer
*b
= NULL
;
1037 pb_reference(&b
, &bo
->base
);
1041 /* There isn't, create a new one. */
1042 bo
= CALLOC_STRUCT(radeon_bo
);
1047 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
1048 struct drm_gem_open open_arg
= {};
1049 memset(&open_arg
, 0, sizeof(open_arg
));
1051 open_arg
.name
= whandle
->handle
;
1052 if (drmIoctl(ws
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
)) {
1056 handle
= open_arg
.handle
;
1057 size
= open_arg
.size
;
1058 bo
->flink_name
= whandle
->handle
;
1059 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
1060 size
= lseek(whandle
->handle
, 0, SEEK_END
);
1062 * Could check errno to determine whether the kernel is new enough, but
1063 * it doesn't really matter why this failed, just that it failed.
1065 if (size
== (off_t
)-1) {
1069 lseek(whandle
->handle
, 0, SEEK_SET
);
1072 bo
->handle
= handle
;
1074 /* Initialize it. */
1075 pipe_reference_init(&bo
->base
.reference
, 1);
1076 bo
->base
.alignment
= 0;
1077 bo
->base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
1078 bo
->base
.size
= (unsigned) size
;
1079 bo
->base
.vtbl
= &radeon_bo_vtbl
;
1083 pipe_mutex_init(bo
->map_mutex
);
1086 util_hash_table_set(mgr
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
1088 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
1091 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
1094 *stride
= whandle
->stride
;
1096 if (mgr
->va
&& !bo
->va
) {
1097 struct drm_radeon_gem_va va
;
1099 bo
->va
= radeon_bomgr_find_va(mgr
, bo
->base
.size
, 1 << 20);
1101 va
.handle
= bo
->handle
;
1102 va
.operation
= RADEON_VA_MAP
;
1105 va
.flags
= RADEON_VM_PAGE_READABLE
|
1106 RADEON_VM_PAGE_WRITEABLE
|
1107 RADEON_VM_PAGE_SNOOPED
;
1109 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
1110 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
1111 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
1112 radeon_bo_destroy(&bo
->base
);
1115 pipe_mutex_lock(mgr
->bo_handles_mutex
);
1116 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
1117 struct pb_buffer
*b
= &bo
->base
;
1118 struct radeon_bo
*old_bo
=
1119 util_hash_table_get(mgr
->bo_vas
, (void*)(uintptr_t)va
.offset
);
1121 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
1122 pb_reference(&b
, &old_bo
->base
);
1126 util_hash_table_set(mgr
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
1127 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
1130 bo
->initial_domain
= radeon_bo_get_initial_domain((void*)bo
);
1132 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1133 ws
->allocated_vram
+= align(bo
->base
.size
, 4096);
1134 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1135 ws
->allocated_gtt
+= align(bo
->base
.size
, 4096);
1137 return (struct pb_buffer
*)bo
;
1140 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
1144 static boolean
radeon_winsys_bo_get_handle(struct pb_buffer
*buffer
,
1146 struct winsys_handle
*whandle
)
1148 struct drm_gem_flink flink
;
1149 struct radeon_bo
*bo
= get_radeon_bo(buffer
);
1151 memset(&flink
, 0, sizeof(flink
));
1153 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
1154 if (!bo
->flink_name
) {
1155 flink
.handle
= bo
->handle
;
1157 if (ioctl(bo
->rws
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
)) {
1161 bo
->flink_name
= flink
.name
;
1163 pipe_mutex_lock(bo
->mgr
->bo_handles_mutex
);
1164 util_hash_table_set(bo
->mgr
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
1165 pipe_mutex_unlock(bo
->mgr
->bo_handles_mutex
);
1167 whandle
->handle
= bo
->flink_name
;
1168 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
1169 whandle
->handle
= bo
->handle
;
1170 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
1171 if (drmPrimeHandleToFD(bo
->rws
->fd
, bo
->handle
, DRM_CLOEXEC
, (int*)&whandle
->handle
))
1175 whandle
->stride
= stride
;
1179 static uint64_t radeon_winsys_bo_va(struct radeon_winsys_cs_handle
*buf
)
1181 return ((struct radeon_bo
*)buf
)->va
;
1184 void radeon_bomgr_init_functions(struct radeon_drm_winsys
*ws
)
1186 ws
->base
.buffer_get_cs_handle
= radeon_drm_get_cs_handle
;
1187 ws
->base
.buffer_set_tiling
= radeon_bo_set_tiling
;
1188 ws
->base
.buffer_get_tiling
= radeon_bo_get_tiling
;
1189 ws
->base
.buffer_map
= radeon_bo_map
;
1190 ws
->base
.buffer_unmap
= radeon_bo_unmap
;
1191 ws
->base
.buffer_wait
= radeon_bo_wait
;
1192 ws
->base
.buffer_create
= radeon_winsys_bo_create
;
1193 ws
->base
.buffer_from_handle
= radeon_winsys_bo_from_handle
;
1194 ws
->base
.buffer_from_ptr
= radeon_winsys_bo_from_ptr
;
1195 ws
->base
.buffer_get_handle
= radeon_winsys_bo_get_handle
;
1196 ws
->base
.buffer_get_virtual_address
= radeon_winsys_bo_va
;
1197 ws
->base
.buffer_get_initial_domain
= radeon_bo_get_initial_domain
;