src/gallium/winsys/radeon/drm/radeon_drm_bo.c

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 #define _FILE_OFFSET_BITS 64
  28 #include "radeon_drm_cs.h"
  29
  30 #include "util/u_hash_table.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_simple_list.h"
  33 #include "os/os_thread.h"
  34 #include "os/os_mman.h"
  35
  36 #include "state_tracker/drm_driver.h"
  37
  38 #include <sys/ioctl.h>
  39 #include <xf86drm.h>
  40 #include <errno.h>
  41
  42 #define RADEON_BO_FLAGS_MACRO_TILE  1
  43 #define RADEON_BO_FLAGS_MICRO_TILE  2
  44 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
  45
  46 #ifndef DRM_RADEON_GEM_WAIT
  47 #define DRM_RADEON_GEM_WAIT             0x2b
  48
  49 #define RADEON_GEM_NO_WAIT      0x1
  50 #define RADEON_GEM_USAGE_READ   0x2
  51 #define RADEON_GEM_USAGE_WRITE  0x4
  52
  53 struct drm_radeon_gem_wait {
  54         uint32_t        handle;
  55         uint32_t        flags;  /* one of RADEON_GEM_* */
  56 };
  57
  58 #endif
  59
  60
  61 extern const struct pb_vtbl radeon_bo_vtbl;
  62
  63
  64 static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
  65 {
  66     assert(bo->vtbl == &radeon_bo_vtbl);
  67     return (struct radeon_bo *)bo;
  68 }
  69
  70 struct radeon_bomgr {
  71     /* Base class. */
  72     struct pb_manager base;
  73
  74     /* Winsys. */
  75     struct radeon_drm_winsys *rws;
  76
  77     /* List of buffer handles and its mutex. */
  78     struct util_hash_table *bo_handles;
  79     pipe_mutex bo_handles_mutex;
  80 };
  81
  82 static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
  83 {
  84     return (struct radeon_bomgr *)mgr;
  85 }
  86
  87 static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
  88 {
  89     struct radeon_bo *bo = NULL;
  90
  91     if (_buf->vtbl == &radeon_bo_vtbl) {
  92         bo = radeon_bo(_buf);
  93     } else {
  94         struct pb_buffer *base_buf;
  95         pb_size offset;
  96         pb_get_base_buffer(_buf, &base_buf, &offset);
  97
  98         if (base_buf->vtbl == &radeon_bo_vtbl)
  99             bo = radeon_bo(base_buf);
 100     }
 101
 102     return bo;
 103 }
 104
 105 static void radeon_bo_wait(struct pb_buffer *_buf, enum radeon_bo_usage usage)
 106 {
 107     struct radeon_bo *bo = get_radeon_bo(_buf);
 108
 109     while (p_atomic_read(&bo->num_active_ioctls)) {
 110         sched_yield();
 111     }
 112
 113     /* XXX use this when it's ready */
 114     /*if (bo->rws->info.drm_minor >= 12) {
 115         struct drm_radeon_gem_wait args = {};
 116         args.handle = bo->handle;
 117         args.flags = usage;
 118         while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
 119                                    &args, sizeof(args)) == -EBUSY);
 120     } else*/ {
 121         struct drm_radeon_gem_wait_idle args = {};
 122         args.handle = bo->handle;
 123         while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
 124                                    &args, sizeof(args)) == -EBUSY);
 125     }
 126 }
 127
 128 static boolean radeon_bo_is_busy(struct pb_buffer *_buf,
 129                                  enum radeon_bo_usage usage)
 130 {
 131     struct radeon_bo *bo = get_radeon_bo(_buf);
 132
 133     if (p_atomic_read(&bo->num_active_ioctls)) {
 134         return TRUE;
 135     }
 136
 137     /* XXX use this when it's ready */
 138     /*if (bo->rws->info.drm_minor >= 12) {
 139         struct drm_radeon_gem_wait args = {};
 140         args.handle = bo->handle;
 141         args.flags = usage | RADEON_GEM_NO_WAIT;
 142         return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
 143                                    &args, sizeof(args)) != 0;
 144     } else*/ {
 145         struct drm_radeon_gem_busy args = {};
 146         args.handle = bo->handle;
 147         return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
 148                                    &args, sizeof(args)) != 0;
 149     }
 150 }
 151
 152 static void radeon_bo_destroy(struct pb_buffer *_buf)
 153 {
 154     struct radeon_bo *bo = radeon_bo(_buf);
 155     struct drm_gem_close args = {};
 156
 157     if (bo->name) {
 158         pipe_mutex_lock(bo->mgr->bo_handles_mutex);
 159         util_hash_table_remove(bo->mgr->bo_handles,
 160                                (void*)(uintptr_t)bo->name);
 161         pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
 162     }
 163
 164     if (bo->ptr)
 165         os_munmap(bo->ptr, bo->base.size);
 166
 167     /* Close object. */
 168     args.handle = bo->handle;
 169     drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
 170     pipe_mutex_destroy(bo->map_mutex);
 171     FREE(bo);
 172 }
 173
 174 static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage)
 175 {
 176     unsigned res = 0;
 177
 178     if (usage & PIPE_TRANSFER_WRITE)
 179         res |= PB_USAGE_CPU_WRITE;
 180
 181     if (usage & PIPE_TRANSFER_DONTBLOCK)
 182         res |= PB_USAGE_DONTBLOCK;
 183
 184     if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
 185         res |= PB_USAGE_UNSYNCHRONIZED;
 186
 187     return res;
 188 }
 189
 190 static void *radeon_bo_map_internal(struct pb_buffer *_buf,
 191                                     unsigned flags, void *flush_ctx)
 192 {
 193     struct radeon_bo *bo = radeon_bo(_buf);
 194     struct radeon_drm_cs *cs = flush_ctx;
 195     struct drm_radeon_gem_mmap args = {};
 196     void *ptr;
 197
 198     /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
 199     if (!(flags & PB_USAGE_UNSYNCHRONIZED)) {
 200         /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
 201         if (flags & PB_USAGE_DONTBLOCK) {
 202             if (!(flags & PB_USAGE_CPU_WRITE)) {
 203                 /* Mapping for read.
 204                  *
 205                  * Since we are mapping for read, we don't need to wait
 206                  * if the GPU is using the buffer for read too
 207                  * (neither one is changing it).
 208                  *
 209                  * Only check whether the buffer is being used for write. */
 210                 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
 211                     cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
 212                     return NULL;
 213                 }
 214
 215                 if (radeon_bo_is_busy((struct pb_buffer*)bo,
 216                                       RADEON_USAGE_WRITE)) {
 217                     return NULL;
 218                 }
 219             } else {
 220                 if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 221                     cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
 222                     return NULL;
 223                 }
 224
 225                 if (radeon_bo_is_busy((struct pb_buffer*)bo,
 226                                       RADEON_USAGE_READWRITE)) {
 227                     return NULL;
 228                 }
 229             }
 230         } else {
 231             if (!(flags & PB_USAGE_CPU_WRITE)) {
 232                 /* Mapping for read.
 233                  *
 234                  * Since we are mapping for read, we don't need to wait
 235                  * if the GPU is using the buffer for read too
 236                  * (neither one is changing it).
 237                  *
 238                  * Only check whether the buffer is being used for write. */
 239                 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
 240                     cs->flush_cs(cs->flush_data, 0);
 241                 }
 242                 radeon_bo_wait((struct pb_buffer*)bo,
 243                                RADEON_USAGE_WRITE);
 244             } else {
 245                 /* Mapping for write. */
 246                 if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 247                     cs->flush_cs(cs->flush_data, 0);
 248                 } else {
 249                     /* Try to avoid busy-waiting in radeon_bo_wait. */
 250                     if (p_atomic_read(&bo->num_active_ioctls))
 251                         radeon_drm_cs_sync_flush(cs);
 252                 }
 253
 254                 radeon_bo_wait((struct pb_buffer*)bo, RADEON_USAGE_READWRITE);
 255             }
 256         }
 257     }
 258
 259     /* Return the pointer if it's already mapped. */
 260     if (bo->ptr)
 261         return bo->ptr;
 262
 263     /* Map the buffer. */
 264     pipe_mutex_lock(bo->map_mutex);
 265     /* Return the pointer if it's already mapped (in case of a race). */
 266     if (bo->ptr) {
 267         pipe_mutex_unlock(bo->map_mutex);
 268         return bo->ptr;
 269     }
 270     args.handle = bo->handle;
 271     args.offset = 0;
 272     args.size = (uint64_t)bo->base.size;
 273     if (drmCommandWriteRead(bo->rws->fd,
 274                             DRM_RADEON_GEM_MMAP,
 275                             &args,
 276                             sizeof(args))) {
 277         pipe_mutex_unlock(bo->map_mutex);
 278         fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
 279                 bo, bo->handle);
 280         return NULL;
 281     }
 282
 283     ptr = os_mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
 284                bo->rws->fd, args.addr_ptr);
 285     if (ptr == MAP_FAILED) {
 286         pipe_mutex_unlock(bo->map_mutex);
 287         fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
 288         return NULL;
 289     }
 290     bo->ptr = ptr;
 291     pipe_mutex_unlock(bo->map_mutex);
 292
 293     return bo->ptr;
 294 }
 295
 296 static void radeon_bo_unmap_internal(struct pb_buffer *_buf)
 297 {
 298     /* NOP */
 299 }
 300
 301 static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
 302                                       struct pb_buffer **base_buf,
 303                                       unsigned *offset)
 304 {
 305     *base_buf = buf;
 306     *offset = 0;
 307 }
 308
 309 static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
 310                                           struct pb_validate *vl,
 311                                           unsigned flags)
 312 {
 313     /* Always pinned */
 314     return PIPE_OK;
 315 }
 316
 317 static void radeon_bo_fence(struct pb_buffer *buf,
 318                             struct pipe_fence_handle *fence)
 319 {
 320 }
 321
 322 const struct pb_vtbl radeon_bo_vtbl = {
 323     radeon_bo_destroy,
 324     radeon_bo_map_internal,
 325     radeon_bo_unmap_internal,
 326     radeon_bo_validate,
 327     radeon_bo_fence,
 328     radeon_bo_get_base_buffer,
 329 };
 330
 331 static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
 332                                                 pb_size size,
 333                                                 const struct pb_desc *desc)
 334 {
 335     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 336     struct radeon_drm_winsys *rws = mgr->rws;
 337     struct radeon_bo *bo;
 338     struct drm_radeon_gem_create args = {};
 339     struct radeon_bo_desc *rdesc = (struct radeon_bo_desc*)desc;
 340
 341     assert(rdesc->initial_domains && rdesc->reloc_domains);
 342     assert((rdesc->initial_domains &
 343             ~(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == 0);
 344     assert((rdesc->reloc_domains &
 345             ~(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == 0);
 346
 347     args.size = size;
 348     args.alignment = desc->alignment;
 349     args.initial_domain = rdesc->initial_domains;
 350
 351     if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
 352                             &args, sizeof(args))) {
 353         fprintf(stderr, "radeon: Failed to allocate a buffer:\n");
 354         fprintf(stderr, "radeon:    size      : %d bytes\n", size);
 355         fprintf(stderr, "radeon:    alignment : %d bytes\n", desc->alignment);
 356         fprintf(stderr, "radeon:    domains   : %d\n", args.initial_domain);
 357         return NULL;
 358     }
 359
 360     bo = CALLOC_STRUCT(radeon_bo);
 361     if (!bo)
 362         return NULL;
 363
 364     pipe_reference_init(&bo->base.reference, 1);
 365     bo->base.alignment = desc->alignment;
 366     bo->base.usage = desc->usage;
 367     bo->base.size = size;
 368     bo->base.vtbl = &radeon_bo_vtbl;
 369     bo->mgr = mgr;
 370     bo->rws = mgr->rws;
 371     bo->handle = args.handle;
 372     bo->reloc_domains = rdesc->reloc_domains;
 373     pipe_mutex_init(bo->map_mutex);
 374
 375     return &bo->base;
 376 }
 377
 378 static void radeon_bomgr_flush(struct pb_manager *mgr)
 379 {
 380     /* NOP */
 381 }
 382
 383 /* This is for the cache bufmgr. */
 384 static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr,
 385                                            struct pb_buffer *_buf)
 386 {
 387    struct radeon_bo *bo = radeon_bo(_buf);
 388
 389    if (radeon_bo_is_referenced_by_any_cs(bo)) {
 390        return TRUE;
 391    }
 392
 393    if (radeon_bo_is_busy((struct pb_buffer*)bo, RADEON_USAGE_READWRITE)) {
 394        return TRUE;
 395    }
 396
 397    return FALSE;
 398 }
 399
 400 static void radeon_bomgr_destroy(struct pb_manager *_mgr)
 401 {
 402     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 403     util_hash_table_destroy(mgr->bo_handles);
 404     pipe_mutex_destroy(mgr->bo_handles_mutex);
 405     FREE(mgr);
 406 }
 407
 408 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 409
 410 static unsigned handle_hash(void *key)
 411 {
 412     return PTR_TO_UINT(key);
 413 }
 414
 415 static int handle_compare(void *key1, void *key2)
 416 {
 417     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 418 }
 419
 420 struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
 421 {
 422     struct radeon_bomgr *mgr;
 423
 424     mgr = CALLOC_STRUCT(radeon_bomgr);
 425     if (!mgr)
 426         return NULL;
 427
 428     mgr->base.destroy = radeon_bomgr_destroy;
 429     mgr->base.create_buffer = radeon_bomgr_create_bo;
 430     mgr->base.flush = radeon_bomgr_flush;
 431     mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
 432
 433     mgr->rws = rws;
 434     mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 435     pipe_mutex_init(mgr->bo_handles_mutex);
 436     return &mgr->base;
 437 }
 438
 439 static void *radeon_bo_map(struct pb_buffer *buf,
 440                            struct radeon_winsys_cs *cs,
 441                            enum pipe_transfer_usage usage)
 442 {
 443     return pb_map(buf, get_pb_usage_from_transfer_flags(usage), cs);
 444 }
 445
 446 static void radeon_bo_get_tiling(struct pb_buffer *_buf,
 447                                  enum radeon_bo_layout *microtiled,
 448                                  enum radeon_bo_layout *macrotiled)
 449 {
 450     struct radeon_bo *bo = get_radeon_bo(_buf);
 451     struct drm_radeon_gem_set_tiling args = {};
 452
 453     args.handle = bo->handle;
 454
 455     drmCommandWriteRead(bo->rws->fd,
 456                         DRM_RADEON_GEM_GET_TILING,
 457                         &args,
 458                         sizeof(args));
 459
 460     *microtiled = RADEON_LAYOUT_LINEAR;
 461     *macrotiled = RADEON_LAYOUT_LINEAR;
 462     if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE)
 463         *microtiled = RADEON_LAYOUT_TILED;
 464
 465     if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE)
 466         *macrotiled = RADEON_LAYOUT_TILED;
 467 }
 468
 469 static void radeon_bo_set_tiling(struct pb_buffer *_buf,
 470                                  struct radeon_winsys_cs *rcs,
 471                                  enum radeon_bo_layout microtiled,
 472                                  enum radeon_bo_layout macrotiled,
 473                                  uint32_t pitch)
 474 {
 475     struct radeon_bo *bo = get_radeon_bo(_buf);
 476     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 477     struct drm_radeon_gem_set_tiling args = {};
 478
 479     /* Tiling determines how DRM treats the buffer data.
 480      * We must flush CS when changing it if the buffer is referenced. */
 481     if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
 482         cs->flush_cs(cs->flush_data, 0);
 483     }
 484
 485     while (p_atomic_read(&bo->num_active_ioctls)) {
 486         sched_yield();
 487     }
 488
 489     if (microtiled == RADEON_LAYOUT_TILED)
 490         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE;
 491     else if (microtiled == RADEON_LAYOUT_SQUARETILED)
 492         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
 493
 494     if (macrotiled == RADEON_LAYOUT_TILED)
 495         args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
 496
 497     args.handle = bo->handle;
 498     args.pitch = pitch;
 499
 500     drmCommandWriteRead(bo->rws->fd,
 501                         DRM_RADEON_GEM_SET_TILING,
 502                         &args,
 503                         sizeof(args));
 504 }
 505
 506 static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle(
 507         struct pb_buffer *_buf)
 508 {
 509     /* return radeon_bo. */
 510     return (struct radeon_winsys_cs_handle*)get_radeon_bo(_buf);
 511 }
 512
 513 static struct pb_buffer *
 514 radeon_winsys_bo_create(struct radeon_winsys *rws,
 515                         unsigned size,
 516                         unsigned alignment,
 517                         unsigned bind, unsigned usage)
 518 {
 519     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 520     struct radeon_bo_desc desc;
 521     struct pb_manager *provider;
 522     struct pb_buffer *buffer;
 523
 524     memset(&desc, 0, sizeof(desc));
 525     desc.base.alignment = alignment;
 526
 527     /* Determine the memory domains. */
 528     switch (usage) {
 529     case PIPE_USAGE_STAGING:
 530     case PIPE_USAGE_STREAM:
 531     case PIPE_USAGE_DYNAMIC:
 532             desc.initial_domains = RADEON_GEM_DOMAIN_GTT;
 533             desc.reloc_domains = RADEON_GEM_DOMAIN_GTT;
 534             break;
 535     case PIPE_USAGE_IMMUTABLE:
 536     case PIPE_USAGE_STATIC:
 537             desc.initial_domains = RADEON_GEM_DOMAIN_VRAM;
 538             desc.reloc_domains = RADEON_GEM_DOMAIN_VRAM;
 539             break;
 540     default:
 541             if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 542                         PIPE_BIND_CONSTANT_BUFFER)) {
 543                 desc.initial_domains = RADEON_GEM_DOMAIN_GTT;
 544             } else {
 545                 desc.initial_domains = RADEON_GEM_DOMAIN_VRAM;
 546             }
 547             desc.reloc_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
 548     }
 549
 550     /* Additional criteria for the cache manager. */
 551     desc.base.usage = desc.initial_domains;
 552
 553     /* Assign a buffer manager. */
 554     if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 555                 PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_CUSTOM))
 556         provider = ws->cman;
 557     else
 558         provider = ws->kman;
 559
 560     buffer = provider->create_buffer(provider, size, &desc.base);
 561     if (!buffer)
 562         return NULL;
 563
 564     return (struct pb_buffer*)buffer;
 565 }
 566
 567 static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
 568                                                       struct winsys_handle *whandle,
 569                                                       unsigned *stride)
 570 {
 571     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 572     struct radeon_bo *bo;
 573     struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
 574     struct drm_gem_open open_arg = {};
 575
 576     /* We must maintain a list of pairs <handle, bo>, so that we always return
 577      * the same BO for one particular handle. If we didn't do that and created
 578      * more than one BO for the same handle and then relocated them in a CS,
 579      * we would hit a deadlock in the kernel.
 580      *
 581      * The list of pairs is guarded by a mutex, of course. */
 582     pipe_mutex_lock(mgr->bo_handles_mutex);
 583
 584     /* First check if there already is an existing bo for the handle. */
 585     bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
 586     if (bo) {
 587         /* Increase the refcount. */
 588         struct pb_buffer *b = NULL;
 589         pb_reference(&b, &bo->base);
 590         goto done;
 591     }
 592
 593     /* There isn't, create a new one. */
 594     bo = CALLOC_STRUCT(radeon_bo);
 595     if (!bo) {
 596         goto fail;
 597     }
 598
 599     /* Open the BO. */
 600     open_arg.name = whandle->handle;
 601     if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
 602         FREE(bo);
 603         goto fail;
 604     }
 605     bo->handle = open_arg.handle;
 606     bo->name = whandle->handle;
 607     bo->reloc_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
 608
 609     /* Initialize it. */
 610     pipe_reference_init(&bo->base.reference, 1);
 611     bo->base.alignment = 0;
 612     bo->base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
 613     bo->base.size = open_arg.size;
 614     bo->base.vtbl = &radeon_bo_vtbl;
 615     bo->mgr = mgr;
 616     bo->rws = mgr->rws;
 617     pipe_mutex_init(bo->map_mutex);
 618
 619     util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
 620
 621 done:
 622     pipe_mutex_unlock(mgr->bo_handles_mutex);
 623
 624     if (stride)
 625         *stride = whandle->stride;
 626
 627     return (struct pb_buffer*)bo;
 628
 629 fail:
 630     pipe_mutex_unlock(mgr->bo_handles_mutex);
 631     return NULL;
 632 }
 633
 634 static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer,
 635                                            unsigned stride,
 636                                            struct winsys_handle *whandle)
 637 {
 638     struct drm_gem_flink flink = {};
 639     struct radeon_bo *bo = get_radeon_bo(buffer);
 640
 641     if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 642         if (!bo->flinked) {
 643             flink.handle = bo->handle;
 644
 645             if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
 646                 return FALSE;
 647             }
 648
 649             bo->flinked = TRUE;
 650             bo->flink = flink.name;
 651         }
 652         whandle->handle = bo->flink;
 653     } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 654         whandle->handle = bo->handle;
 655     }
 656
 657     whandle->stride = stride;
 658     return TRUE;
 659 }
 660
 661 void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws)
 662 {
 663     ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle;
 664     ws->base.buffer_set_tiling = radeon_bo_set_tiling;
 665     ws->base.buffer_get_tiling = radeon_bo_get_tiling;
 666     ws->base.buffer_map = radeon_bo_map;
 667     ws->base.buffer_unmap = pb_unmap;
 668     ws->base.buffer_wait = radeon_bo_wait;
 669     ws->base.buffer_is_busy = radeon_bo_is_busy;
 670     ws->base.buffer_create = radeon_winsys_bo_create;
 671     ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
 672     ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;
 673 }