2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Marek Olšák <maraeo@gmail.com>
31 * Based on work from libdrm_radeon by:
32 * Aapo Tahkola <aet@rasterburn.org>
33 * Nicolai Haehnle <prefect_@gmx.net>
34 * Jérôme Glisse <glisse@freedesktop.org>
38 This file replaces libdrm's radeon_cs_gem with our own implemention.
39 It's optimized specifically for Radeon DRM.
40 Adding buffers and space checking are faster and simpler than their
41 counterparts in libdrm (the time complexity of all the functions
42 is O(1) in nearly all scenarios, thanks to hashing).
46 cs_add_buffer(cs, buf, read_domain, write_domain) adds a new relocation and
47 also adds the size of 'buf' to the used_gart and used_vram winsys variables
48 based on the domains, which are simply or'd for the accounting purposes.
49 The adding is skipped if the reloc is already present in the list, but it
50 accounts any newly-referenced domains.
52 cs_validate is then called, which just checks:
53 used_vram/gart < vram/gart_size * 0.8
54 The 0.8 number allows for some memory fragmentation. If the validation
55 fails, the pipe driver flushes CS and tries do the validation again,
56 i.e. it validates only that one operation. If it fails again, it drops
57 the operation on the floor and prints some nasty message to stderr.
58 (done in the pipe driver)
60 cs_write_reloc(cs, buf) just writes a reloc that has been added using
61 cs_add_buffer. The read_domain and write_domain parameters have been removed,
62 because we already specify them in cs_add_buffer.
65 #include "radeon_drm_cs.h"
67 #include "util/u_memory.h"
68 #include "os/os_time.h"
76 #define RELOC_DWORDS (sizeof(struct drm_radeon_cs_reloc) / sizeof(uint32_t))
78 static struct pipe_fence_handle
*
79 radeon_cs_create_fence(struct radeon_winsys_cs
*rcs
);
80 static void radeon_fence_reference(struct pipe_fence_handle
**dst
,
81 struct pipe_fence_handle
*src
);
83 static struct radeon_winsys_ctx
*radeon_drm_ctx_create(struct radeon_winsys
*ws
)
85 /* No context support here. Just return the winsys pointer
86 * as the "context". */
87 return (struct radeon_winsys_ctx
*)ws
;
90 static void radeon_drm_ctx_destroy(struct radeon_winsys_ctx
*ctx
)
92 /* No context support here. */
95 static bool radeon_init_cs_context(struct radeon_cs_context
*csc
,
96 struct radeon_drm_winsys
*ws
)
102 csc
->relocs_bo
= (struct radeon_bo_item
*)
103 CALLOC(1, csc
->nrelocs
* sizeof(csc
->relocs_bo
[0]));
104 if (!csc
->relocs_bo
) {
108 csc
->relocs
= (struct drm_radeon_cs_reloc
*)
109 CALLOC(1, csc
->nrelocs
* sizeof(struct drm_radeon_cs_reloc
));
111 FREE(csc
->relocs_bo
);
115 csc
->chunks
[0].chunk_id
= RADEON_CHUNK_ID_IB
;
116 csc
->chunks
[0].length_dw
= 0;
117 csc
->chunks
[0].chunk_data
= (uint64_t)(uintptr_t)csc
->buf
;
118 csc
->chunks
[1].chunk_id
= RADEON_CHUNK_ID_RELOCS
;
119 csc
->chunks
[1].length_dw
= 0;
120 csc
->chunks
[1].chunk_data
= (uint64_t)(uintptr_t)csc
->relocs
;
121 csc
->chunks
[2].chunk_id
= RADEON_CHUNK_ID_FLAGS
;
122 csc
->chunks
[2].length_dw
= 2;
123 csc
->chunks
[2].chunk_data
= (uint64_t)(uintptr_t)&csc
->flags
;
125 csc
->chunk_array
[0] = (uint64_t)(uintptr_t)&csc
->chunks
[0];
126 csc
->chunk_array
[1] = (uint64_t)(uintptr_t)&csc
->chunks
[1];
127 csc
->chunk_array
[2] = (uint64_t)(uintptr_t)&csc
->chunks
[2];
129 csc
->cs
.chunks
= (uint64_t)(uintptr_t)csc
->chunk_array
;
131 for (i
= 0; i
< ARRAY_SIZE(csc
->reloc_indices_hashlist
); i
++) {
132 csc
->reloc_indices_hashlist
[i
] = -1;
137 static void radeon_cs_context_cleanup(struct radeon_cs_context
*csc
)
141 for (i
= 0; i
< csc
->crelocs
; i
++) {
142 p_atomic_dec(&csc
->relocs_bo
[i
].bo
->num_cs_references
);
143 radeon_bo_reference(&csc
->relocs_bo
[i
].bo
, NULL
);
147 csc
->validated_crelocs
= 0;
148 csc
->chunks
[0].length_dw
= 0;
149 csc
->chunks
[1].length_dw
= 0;
151 for (i
= 0; i
< ARRAY_SIZE(csc
->reloc_indices_hashlist
); i
++) {
152 csc
->reloc_indices_hashlist
[i
] = -1;
156 static void radeon_destroy_cs_context(struct radeon_cs_context
*csc
)
158 radeon_cs_context_cleanup(csc
);
159 FREE(csc
->relocs_bo
);
164 static struct radeon_winsys_cs
*
165 radeon_drm_cs_create(struct radeon_winsys_ctx
*ctx
,
166 enum ring_type ring_type
,
167 void (*flush
)(void *ctx
, unsigned flags
,
168 struct pipe_fence_handle
**fence
),
171 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)ctx
;
172 struct radeon_drm_cs
*cs
;
174 cs
= CALLOC_STRUCT(radeon_drm_cs
);
178 util_queue_fence_init(&cs
->flush_completed
);
181 cs
->flush_cs
= flush
;
182 cs
->flush_data
= flush_ctx
;
184 if (!radeon_init_cs_context(&cs
->csc1
, cs
->ws
)) {
188 if (!radeon_init_cs_context(&cs
->csc2
, cs
->ws
)) {
189 radeon_destroy_cs_context(&cs
->csc1
);
194 /* Set the first command buffer as current. */
197 cs
->base
.current
.buf
= cs
->csc
->buf
;
198 cs
->base
.current
.max_dw
= ARRAY_SIZE(cs
->csc
->buf
);
199 cs
->ring_type
= ring_type
;
201 p_atomic_inc(&ws
->num_cs
);
205 #define OUT_CS(cs, value) (cs)->current.buf[(cs)->current.cdw++] = (value)
207 static inline void update_reloc(struct drm_radeon_cs_reloc
*reloc
,
208 enum radeon_bo_domain rd
,
209 enum radeon_bo_domain wd
,
211 enum radeon_bo_domain
*added_domains
)
213 *added_domains
= (rd
| wd
) & ~(reloc
->read_domains
| reloc
->write_domain
);
215 reloc
->read_domains
|= rd
;
216 reloc
->write_domain
|= wd
;
217 reloc
->flags
= MAX2(reloc
->flags
, priority
);
220 int radeon_lookup_buffer(struct radeon_cs_context
*csc
, struct radeon_bo
*bo
)
222 unsigned hash
= bo
->handle
& (ARRAY_SIZE(csc
->reloc_indices_hashlist
)-1);
223 int i
= csc
->reloc_indices_hashlist
[hash
];
225 /* not found or found */
226 if (i
== -1 || csc
->relocs_bo
[i
].bo
== bo
)
229 /* Hash collision, look for the BO in the list of relocs linearly. */
230 for (i
= csc
->crelocs
- 1; i
>= 0; i
--) {
231 if (csc
->relocs_bo
[i
].bo
== bo
) {
232 /* Put this reloc in the hash list.
233 * This will prevent additional hash collisions if there are
234 * several consecutive lookup_buffer calls for the same buffer.
236 * Example: Assuming buffers A,B,C collide in the hash list,
237 * the following sequence of relocs:
238 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
239 * will collide here: ^ and here: ^,
240 * meaning that we should get very few collisions in the end. */
241 csc
->reloc_indices_hashlist
[hash
] = i
;
248 static unsigned radeon_add_buffer(struct radeon_drm_cs
*cs
,
249 struct radeon_bo
*bo
,
250 enum radeon_bo_usage usage
,
251 enum radeon_bo_domain domains
,
253 enum radeon_bo_domain
*added_domains
)
255 struct radeon_cs_context
*csc
= cs
->csc
;
256 struct drm_radeon_cs_reloc
*reloc
;
257 unsigned hash
= bo
->handle
& (ARRAY_SIZE(csc
->reloc_indices_hashlist
)-1);
258 enum radeon_bo_domain rd
= usage
& RADEON_USAGE_READ
? domains
: 0;
259 enum radeon_bo_domain wd
= usage
& RADEON_USAGE_WRITE
? domains
: 0;
262 assert(priority
< 64);
265 i
= radeon_lookup_buffer(csc
, bo
);
268 reloc
= &csc
->relocs
[i
];
269 update_reloc(reloc
, rd
, wd
, priority
/ 4, added_domains
);
270 csc
->relocs_bo
[i
].priority_usage
|= 1llu << priority
;
272 /* For async DMA, every add_buffer call must add a buffer to the list
273 * no matter how many duplicates there are. This is due to the fact
274 * the DMA CS checker doesn't use NOP packets for offset patching,
275 * but always uses the i-th buffer from the list to patch the i-th
276 * offset. If there are N offsets in a DMA CS, there must also be N
277 * buffers in the relocation list.
279 * This doesn't have to be done if virtual memory is enabled,
280 * because there is no offset patching with virtual memory.
282 if (cs
->ring_type
!= RING_DMA
|| cs
->ws
->info
.has_virtual_memory
) {
287 /* New relocation, check if the backing array is large enough. */
288 if (csc
->crelocs
>= csc
->nrelocs
) {
292 size
= csc
->nrelocs
* sizeof(csc
->relocs_bo
[0]);
293 csc
->relocs_bo
= realloc(csc
->relocs_bo
, size
);
295 size
= csc
->nrelocs
* sizeof(struct drm_radeon_cs_reloc
);
296 csc
->relocs
= realloc(csc
->relocs
, size
);
298 csc
->chunks
[1].chunk_data
= (uint64_t)(uintptr_t)csc
->relocs
;
301 /* Initialize the new relocation. */
302 csc
->relocs_bo
[csc
->crelocs
].bo
= NULL
;
303 csc
->relocs_bo
[csc
->crelocs
].priority_usage
= 1llu << priority
;
304 radeon_bo_reference(&csc
->relocs_bo
[csc
->crelocs
].bo
, bo
);
305 p_atomic_inc(&bo
->num_cs_references
);
306 reloc
= &csc
->relocs
[csc
->crelocs
];
307 reloc
->handle
= bo
->handle
;
308 reloc
->read_domains
= rd
;
309 reloc
->write_domain
= wd
;
310 reloc
->flags
= priority
/ 4;
312 csc
->reloc_indices_hashlist
[hash
] = csc
->crelocs
;
314 csc
->chunks
[1].length_dw
+= RELOC_DWORDS
;
316 *added_domains
= rd
| wd
;
317 return csc
->crelocs
++;
320 static unsigned radeon_drm_cs_add_buffer(struct radeon_winsys_cs
*rcs
,
321 struct pb_buffer
*buf
,
322 enum radeon_bo_usage usage
,
323 enum radeon_bo_domain domains
,
324 enum radeon_bo_priority priority
)
326 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
327 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
328 enum radeon_bo_domain added_domains
;
329 unsigned index
= radeon_add_buffer(cs
, bo
, usage
, domains
, priority
,
332 if (added_domains
& RADEON_DOMAIN_VRAM
)
333 cs
->base
.used_vram
+= bo
->base
.size
;
334 else if (added_domains
& RADEON_DOMAIN_GTT
)
335 cs
->base
.used_gart
+= bo
->base
.size
;
340 static int radeon_drm_cs_lookup_buffer(struct radeon_winsys_cs
*rcs
,
341 struct pb_buffer
*buf
)
343 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
345 return radeon_lookup_buffer(cs
->csc
, (struct radeon_bo
*)buf
);
348 static bool radeon_drm_cs_validate(struct radeon_winsys_cs
*rcs
)
350 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
352 cs
->base
.used_gart
< cs
->ws
->info
.gart_size
* 0.8 &&
353 cs
->base
.used_vram
< cs
->ws
->info
.vram_size
* 0.8;
356 cs
->csc
->validated_crelocs
= cs
->csc
->crelocs
;
358 /* Remove lately-added buffers. The validation failed with them
359 * and the CS is about to be flushed because of that. Keep only
360 * the already-validated buffers. */
363 for (i
= cs
->csc
->validated_crelocs
; i
< cs
->csc
->crelocs
; i
++) {
364 p_atomic_dec(&cs
->csc
->relocs_bo
[i
].bo
->num_cs_references
);
365 radeon_bo_reference(&cs
->csc
->relocs_bo
[i
].bo
, NULL
);
367 cs
->csc
->crelocs
= cs
->csc
->validated_crelocs
;
369 /* Flush if there are any relocs. Clean up otherwise. */
370 if (cs
->csc
->crelocs
) {
371 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
373 radeon_cs_context_cleanup(cs
->csc
);
374 cs
->base
.used_vram
= 0;
375 cs
->base
.used_gart
= 0;
377 assert(cs
->base
.current
.cdw
== 0);
378 if (cs
->base
.current
.cdw
!= 0) {
379 fprintf(stderr
, "radeon: Unexpected error in %s.\n", __func__
);
386 static bool radeon_drm_cs_check_space(struct radeon_winsys_cs
*rcs
, unsigned dw
)
388 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
389 return rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
;
392 static bool radeon_drm_cs_memory_below_limit(struct radeon_winsys_cs
*rcs
, uint64_t vram
, uint64_t gtt
)
394 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
396 vram
+= cs
->base
.used_vram
;
397 gtt
+= cs
->base
.used_gart
;
399 /* Anything that goes above the VRAM size should go to GTT. */
400 if (vram
> cs
->ws
->info
.vram_size
)
401 gtt
+= vram
- cs
->ws
->info
.vram_size
;
403 /* Now we just need to check if we have enough GTT. */
404 return gtt
< cs
->ws
->info
.gart_size
* 0.7;
407 static uint64_t radeon_drm_cs_query_memory_usage(struct radeon_winsys_cs
*rcs
)
409 return rcs
->used_vram
+ rcs
->used_gart
;
412 static unsigned radeon_drm_cs_get_buffer_list(struct radeon_winsys_cs
*rcs
,
413 struct radeon_bo_list_item
*list
)
415 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
419 for (i
= 0; i
< cs
->csc
->crelocs
; i
++) {
420 list
[i
].bo_size
= cs
->csc
->relocs_bo
[i
].bo
->base
.size
;
421 list
[i
].vm_address
= cs
->csc
->relocs_bo
[i
].bo
->va
;
422 list
[i
].priority_usage
= cs
->csc
->relocs_bo
[i
].priority_usage
;
425 return cs
->csc
->crelocs
;
428 void radeon_drm_cs_emit_ioctl_oneshot(void *job
, int thread_index
)
430 struct radeon_cs_context
*csc
= ((struct radeon_drm_cs
*)job
)->cst
;
434 r
= drmCommandWriteRead(csc
->fd
, DRM_RADEON_CS
,
435 &csc
->cs
, sizeof(struct drm_radeon_cs
));
438 fprintf(stderr
, "radeon: Not enough memory for command submission.\n");
439 else if (debug_get_bool_option("RADEON_DUMP_CS", false)) {
442 fprintf(stderr
, "radeon: The kernel rejected CS, dumping...\n");
443 for (i
= 0; i
< csc
->chunks
[0].length_dw
; i
++) {
444 fprintf(stderr
, "0x%08X\n", csc
->buf
[i
]);
447 fprintf(stderr
, "radeon: The kernel rejected CS, "
448 "see dmesg for more information (%i).\n", r
);
452 for (i
= 0; i
< csc
->crelocs
; i
++)
453 p_atomic_dec(&csc
->relocs_bo
[i
].bo
->num_active_ioctls
);
455 radeon_cs_context_cleanup(csc
);
459 * Make sure previous submission of this cs are completed
461 void radeon_drm_cs_sync_flush(struct radeon_winsys_cs
*rcs
)
463 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
465 /* Wait for any pending ioctl of this CS to complete. */
466 if (util_queue_is_initialized(&cs
->ws
->cs_queue
))
467 util_queue_job_wait(&cs
->flush_completed
);
470 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
472 static int radeon_drm_cs_flush(struct radeon_winsys_cs
*rcs
,
474 struct pipe_fence_handle
**fence
)
476 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
477 struct radeon_cs_context
*tmp
;
479 switch (cs
->ring_type
) {
481 /* pad DMA ring to 8 DWs */
482 if (cs
->ws
->info
.chip_class
<= SI
) {
483 while (rcs
->current
.cdw
& 7)
484 OUT_CS(&cs
->base
, 0xf0000000); /* NOP packet */
486 while (rcs
->current
.cdw
& 7)
487 OUT_CS(&cs
->base
, 0x00000000); /* NOP packet */
491 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements
492 * r6xx, requires at least 4 dw alignment to avoid a hw bug.
494 if (cs
->ws
->info
.gfx_ib_pad_with_type2
) {
495 while (rcs
->current
.cdw
& 7)
496 OUT_CS(&cs
->base
, 0x80000000); /* type2 nop packet */
498 while (rcs
->current
.cdw
& 7)
499 OUT_CS(&cs
->base
, 0xffff1000); /* type3 nop packet */
503 while (rcs
->current
.cdw
& 15)
504 OUT_CS(&cs
->base
, 0x80000000); /* type2 nop packet */
510 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
511 fprintf(stderr
, "radeon: command stream overflowed\n");
515 radeon_fence_reference(fence
, NULL
);
516 *fence
= radeon_cs_create_fence(rcs
);
519 radeon_drm_cs_sync_flush(rcs
);
521 /* Swap command streams. */
526 /* If the CS is not empty or overflowed, emit it in a separate thread. */
527 if (cs
->base
.current
.cdw
&& cs
->base
.current
.cdw
<= cs
->base
.current
.max_dw
&& !debug_get_option_noop()) {
530 crelocs
= cs
->cst
->crelocs
;
532 cs
->cst
->chunks
[0].length_dw
= cs
->base
.current
.cdw
;
534 for (i
= 0; i
< crelocs
; i
++) {
535 /* Update the number of active asynchronous CS ioctls for the buffer. */
536 p_atomic_inc(&cs
->cst
->relocs_bo
[i
].bo
->num_active_ioctls
);
539 switch (cs
->ring_type
) {
541 cs
->cst
->flags
[0] = 0;
542 cs
->cst
->flags
[1] = RADEON_CS_RING_DMA
;
543 cs
->cst
->cs
.num_chunks
= 3;
544 if (cs
->ws
->info
.has_virtual_memory
) {
545 cs
->cst
->flags
[0] |= RADEON_CS_USE_VM
;
550 cs
->cst
->flags
[0] = 0;
551 cs
->cst
->flags
[1] = RADEON_CS_RING_UVD
;
552 cs
->cst
->cs
.num_chunks
= 3;
556 cs
->cst
->flags
[0] = 0;
557 cs
->cst
->flags
[1] = RADEON_CS_RING_VCE
;
558 cs
->cst
->cs
.num_chunks
= 3;
564 cs
->cst
->flags
[0] = RADEON_CS_KEEP_TILING_FLAGS
;
565 cs
->cst
->flags
[1] = RADEON_CS_RING_GFX
;
566 cs
->cst
->cs
.num_chunks
= 3;
568 if (cs
->ws
->info
.has_virtual_memory
) {
569 cs
->cst
->flags
[0] |= RADEON_CS_USE_VM
;
570 cs
->cst
->cs
.num_chunks
= 3;
572 if (flags
& RADEON_FLUSH_END_OF_FRAME
) {
573 cs
->cst
->flags
[0] |= RADEON_CS_END_OF_FRAME
;
574 cs
->cst
->cs
.num_chunks
= 3;
576 if (cs
->ring_type
== RING_COMPUTE
) {
577 cs
->cst
->flags
[1] = RADEON_CS_RING_COMPUTE
;
578 cs
->cst
->cs
.num_chunks
= 3;
583 if (util_queue_is_initialized(&cs
->ws
->cs_queue
)) {
584 util_queue_add_job(&cs
->ws
->cs_queue
, cs
, &cs
->flush_completed
,
585 radeon_drm_cs_emit_ioctl_oneshot
, NULL
);
586 if (!(flags
& RADEON_FLUSH_ASYNC
))
587 radeon_drm_cs_sync_flush(rcs
);
589 radeon_drm_cs_emit_ioctl_oneshot(cs
, 0);
592 radeon_cs_context_cleanup(cs
->cst
);
595 /* Prepare a new CS. */
596 cs
->base
.current
.buf
= cs
->csc
->buf
;
597 cs
->base
.current
.cdw
= 0;
598 cs
->base
.used_vram
= 0;
599 cs
->base
.used_gart
= 0;
601 cs
->ws
->num_cs_flushes
++;
605 static void radeon_drm_cs_destroy(struct radeon_winsys_cs
*rcs
)
607 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
609 radeon_drm_cs_sync_flush(rcs
);
610 util_queue_fence_destroy(&cs
->flush_completed
);
611 radeon_cs_context_cleanup(&cs
->csc1
);
612 radeon_cs_context_cleanup(&cs
->csc2
);
613 p_atomic_dec(&cs
->ws
->num_cs
);
614 radeon_destroy_cs_context(&cs
->csc1
);
615 radeon_destroy_cs_context(&cs
->csc2
);
619 static bool radeon_bo_is_referenced(struct radeon_winsys_cs
*rcs
,
620 struct pb_buffer
*_buf
,
621 enum radeon_bo_usage usage
)
623 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
624 struct radeon_bo
*bo
= (struct radeon_bo
*)_buf
;
627 if (!bo
->num_cs_references
)
630 index
= radeon_lookup_buffer(cs
->csc
, bo
);
634 if ((usage
& RADEON_USAGE_WRITE
) && cs
->csc
->relocs
[index
].write_domain
)
636 if ((usage
& RADEON_USAGE_READ
) && cs
->csc
->relocs
[index
].read_domains
)
644 static struct pipe_fence_handle
*
645 radeon_cs_create_fence(struct radeon_winsys_cs
*rcs
)
647 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
648 struct pb_buffer
*fence
;
650 /* Create a fence, which is a dummy BO. */
651 fence
= cs
->ws
->base
.buffer_create(&cs
->ws
->base
, 1, 1,
652 RADEON_DOMAIN_GTT
, 0);
653 /* Add the fence as a dummy relocation. */
654 cs
->ws
->base
.cs_add_buffer(rcs
, fence
,
655 RADEON_USAGE_READWRITE
, RADEON_DOMAIN_GTT
,
657 return (struct pipe_fence_handle
*)fence
;
660 static bool radeon_fence_wait(struct radeon_winsys
*ws
,
661 struct pipe_fence_handle
*fence
,
664 return ws
->buffer_wait((struct pb_buffer
*)fence
, timeout
,
665 RADEON_USAGE_READWRITE
);
668 static void radeon_fence_reference(struct pipe_fence_handle
**dst
,
669 struct pipe_fence_handle
*src
)
671 pb_reference((struct pb_buffer
**)dst
, (struct pb_buffer
*)src
);
674 void radeon_drm_cs_init_functions(struct radeon_drm_winsys
*ws
)
676 ws
->base
.ctx_create
= radeon_drm_ctx_create
;
677 ws
->base
.ctx_destroy
= radeon_drm_ctx_destroy
;
678 ws
->base
.cs_create
= radeon_drm_cs_create
;
679 ws
->base
.cs_destroy
= radeon_drm_cs_destroy
;
680 ws
->base
.cs_add_buffer
= radeon_drm_cs_add_buffer
;
681 ws
->base
.cs_lookup_buffer
= radeon_drm_cs_lookup_buffer
;
682 ws
->base
.cs_validate
= radeon_drm_cs_validate
;
683 ws
->base
.cs_check_space
= radeon_drm_cs_check_space
;
684 ws
->base
.cs_memory_below_limit
= radeon_drm_cs_memory_below_limit
;
685 ws
->base
.cs_query_memory_usage
= radeon_drm_cs_query_memory_usage
;
686 ws
->base
.cs_get_buffer_list
= radeon_drm_cs_get_buffer_list
;
687 ws
->base
.cs_flush
= radeon_drm_cs_flush
;
688 ws
->base
.cs_is_buffer_referenced
= radeon_bo_is_referenced
;
689 ws
->base
.cs_sync_flush
= radeon_drm_cs_sync_flush
;
690 ws
->base
.fence_wait
= radeon_fence_wait
;
691 ws
->base
.fence_reference
= radeon_fence_reference
;