2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Marek Olšák <maraeo@gmail.com>
31 * Based on work from libdrm_radeon by:
32 * Aapo Tahkola <aet@rasterburn.org>
33 * Nicolai Haehnle <prefect_@gmx.net>
34 * Jérôme Glisse <glisse@freedesktop.org>
38 This file replaces libdrm's radeon_cs_gem with our own implemention.
39 It's optimized specifically for Radeon DRM.
40 Reloc writes and space checking are faster and simpler than their
41 counterparts in libdrm (the time complexity of all the functions
42 is O(1) in nearly all scenarios, thanks to hashing).
46 cs_add_reloc(cs, buf, read_domain, write_domain) adds a new relocation and
47 also adds the size of 'buf' to the used_gart and used_vram winsys variables
48 based on the domains, which are simply or'd for the accounting purposes.
49 The adding is skipped if the reloc is already present in the list, but it
50 accounts any newly-referenced domains.
52 cs_validate is then called, which just checks:
53 used_vram/gart < vram/gart_size * 0.8
54 The 0.8 number allows for some memory fragmentation. If the validation
55 fails, the pipe driver flushes CS and tries do the validation again,
56 i.e. it validates only that one operation. If it fails again, it drops
57 the operation on the floor and prints some nasty message to stderr.
58 (done in the pipe driver)
60 cs_write_reloc(cs, buf) just writes a reloc that has been added using
61 cs_add_reloc. The read_domain and write_domain parameters have been removed,
62 because we already specify them in cs_add_reloc.
65 #include "radeon_drm_cs.h"
67 #include "util/u_memory.h"
68 #include "os/os_time.h"
76 #define RELOC_DWORDS (sizeof(struct drm_radeon_cs_reloc) / sizeof(uint32_t))
78 static struct pipe_fence_handle
*
79 radeon_cs_create_fence(struct radeon_winsys_cs
*rcs
);
80 static void radeon_fence_reference(struct pipe_fence_handle
**dst
,
81 struct pipe_fence_handle
*src
);
83 static boolean
radeon_init_cs_context(struct radeon_cs_context
*csc
,
84 struct radeon_drm_winsys
*ws
)
90 csc
->relocs_bo
= (struct radeon_bo
**)
91 CALLOC(1, csc
->nrelocs
* sizeof(struct radeon_bo
*));
92 if (!csc
->relocs_bo
) {
96 csc
->relocs
= (struct drm_radeon_cs_reloc
*)
97 CALLOC(1, csc
->nrelocs
* sizeof(struct drm_radeon_cs_reloc
));
103 csc
->chunks
[0].chunk_id
= RADEON_CHUNK_ID_IB
;
104 csc
->chunks
[0].length_dw
= 0;
105 csc
->chunks
[0].chunk_data
= (uint64_t)(uintptr_t)csc
->buf
;
106 csc
->chunks
[1].chunk_id
= RADEON_CHUNK_ID_RELOCS
;
107 csc
->chunks
[1].length_dw
= 0;
108 csc
->chunks
[1].chunk_data
= (uint64_t)(uintptr_t)csc
->relocs
;
109 csc
->chunks
[2].chunk_id
= RADEON_CHUNK_ID_FLAGS
;
110 csc
->chunks
[2].length_dw
= 2;
111 csc
->chunks
[2].chunk_data
= (uint64_t)(uintptr_t)&csc
->flags
;
113 csc
->chunk_array
[0] = (uint64_t)(uintptr_t)&csc
->chunks
[0];
114 csc
->chunk_array
[1] = (uint64_t)(uintptr_t)&csc
->chunks
[1];
115 csc
->chunk_array
[2] = (uint64_t)(uintptr_t)&csc
->chunks
[2];
117 csc
->cs
.chunks
= (uint64_t)(uintptr_t)csc
->chunk_array
;
119 for (i
= 0; i
< Elements(csc
->reloc_indices_hashlist
); i
++) {
120 csc
->reloc_indices_hashlist
[i
] = -1;
125 static void radeon_cs_context_cleanup(struct radeon_cs_context
*csc
)
129 for (i
= 0; i
< csc
->crelocs
; i
++) {
130 p_atomic_dec(&csc
->relocs_bo
[i
]->num_cs_references
);
131 radeon_bo_reference(&csc
->relocs_bo
[i
], NULL
);
135 csc
->validated_crelocs
= 0;
136 csc
->chunks
[0].length_dw
= 0;
137 csc
->chunks
[1].length_dw
= 0;
141 for (i
= 0; i
< Elements(csc
->reloc_indices_hashlist
); i
++) {
142 csc
->reloc_indices_hashlist
[i
] = -1;
146 static void radeon_destroy_cs_context(struct radeon_cs_context
*csc
)
148 radeon_cs_context_cleanup(csc
);
149 FREE(csc
->relocs_bo
);
154 static struct radeon_winsys_cs
*
155 radeon_drm_cs_create(struct radeon_winsys
*rws
,
156 enum ring_type ring_type
,
157 void (*flush
)(void *ctx
, unsigned flags
,
158 struct pipe_fence_handle
**fence
),
160 struct radeon_winsys_cs_handle
*trace_buf
)
162 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
163 struct radeon_drm_cs
*cs
;
165 cs
= CALLOC_STRUCT(radeon_drm_cs
);
169 pipe_semaphore_init(&cs
->flush_completed
, 1);
172 cs
->flush_cs
= flush
;
173 cs
->flush_data
= flush_ctx
;
174 cs
->trace_buf
= (struct radeon_bo
*)trace_buf
;
176 if (!radeon_init_cs_context(&cs
->csc1
, cs
->ws
)) {
180 if (!radeon_init_cs_context(&cs
->csc2
, cs
->ws
)) {
181 radeon_destroy_cs_context(&cs
->csc1
);
186 /* Set the first command buffer as current. */
189 cs
->base
.buf
= cs
->csc
->buf
;
190 cs
->base
.ring_type
= ring_type
;
192 p_atomic_inc(&ws
->num_cs
);
196 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
198 static INLINE
void update_reloc(struct drm_radeon_cs_reloc
*reloc
,
199 enum radeon_bo_domain rd
,
200 enum radeon_bo_domain wd
,
202 enum radeon_bo_domain
*added_domains
)
204 *added_domains
= (rd
| wd
) & ~(reloc
->read_domains
| reloc
->write_domain
);
206 reloc
->read_domains
|= rd
;
207 reloc
->write_domain
|= wd
;
208 reloc
->flags
= MAX2(reloc
->flags
, priority
);
211 int radeon_get_reloc(struct radeon_cs_context
*csc
, struct radeon_bo
*bo
)
213 unsigned hash
= bo
->handle
& (Elements(csc
->reloc_indices_hashlist
)-1);
214 int i
= csc
->reloc_indices_hashlist
[hash
];
216 /* not found or found */
217 if (i
== -1 || csc
->relocs_bo
[i
] == bo
)
220 /* Hash collision, look for the BO in the list of relocs linearly. */
221 for (i
= csc
->crelocs
- 1; i
>= 0; i
--) {
222 if (csc
->relocs_bo
[i
] == bo
) {
223 /* Put this reloc in the hash list.
224 * This will prevent additional hash collisions if there are
225 * several consecutive get_reloc calls for the same buffer.
227 * Example: Assuming buffers A,B,C collide in the hash list,
228 * the following sequence of relocs:
229 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
230 * will collide here: ^ and here: ^,
231 * meaning that we should get very few collisions in the end. */
232 csc
->reloc_indices_hashlist
[hash
] = i
;
239 static unsigned radeon_add_reloc(struct radeon_drm_cs
*cs
,
240 struct radeon_bo
*bo
,
241 enum radeon_bo_usage usage
,
242 enum radeon_bo_domain domains
,
244 enum radeon_bo_domain
*added_domains
)
246 struct radeon_cs_context
*csc
= cs
->csc
;
247 struct drm_radeon_cs_reloc
*reloc
;
248 unsigned hash
= bo
->handle
& (Elements(csc
->reloc_indices_hashlist
)-1);
249 enum radeon_bo_domain rd
= usage
& RADEON_USAGE_READ
? domains
: 0;
250 enum radeon_bo_domain wd
= usage
& RADEON_USAGE_WRITE
? domains
: 0;
253 priority
= MIN2(priority
, 15);
256 i
= radeon_get_reloc(csc
, bo
);
259 reloc
= &csc
->relocs
[i
];
260 update_reloc(reloc
, rd
, wd
, priority
, added_domains
);
262 /* For async DMA, every add_reloc call must add a buffer to the list
263 * no matter how many duplicates there are. This is due to the fact
264 * the DMA CS checker doesn't use NOP packets for offset patching,
265 * but always uses the i-th buffer from the list to patch the i-th
266 * offset. If there are N offsets in a DMA CS, there must also be N
267 * buffers in the relocation list.
269 * This doesn't have to be done if virtual memory is enabled,
270 * because there is no offset patching with virtual memory.
272 if (cs
->base
.ring_type
!= RING_DMA
|| cs
->ws
->info
.r600_virtual_address
) {
277 /* New relocation, check if the backing array is large enough. */
278 if (csc
->crelocs
>= csc
->nrelocs
) {
282 size
= csc
->nrelocs
* sizeof(struct radeon_bo
*);
283 csc
->relocs_bo
= realloc(csc
->relocs_bo
, size
);
285 size
= csc
->nrelocs
* sizeof(struct drm_radeon_cs_reloc
);
286 csc
->relocs
= realloc(csc
->relocs
, size
);
288 csc
->chunks
[1].chunk_data
= (uint64_t)(uintptr_t)csc
->relocs
;
291 /* Initialize the new relocation. */
292 csc
->relocs_bo
[csc
->crelocs
] = NULL
;
293 radeon_bo_reference(&csc
->relocs_bo
[csc
->crelocs
], bo
);
294 p_atomic_inc(&bo
->num_cs_references
);
295 reloc
= &csc
->relocs
[csc
->crelocs
];
296 reloc
->handle
= bo
->handle
;
297 reloc
->read_domains
= rd
;
298 reloc
->write_domain
= wd
;
299 reloc
->flags
= priority
;
301 csc
->reloc_indices_hashlist
[hash
] = csc
->crelocs
;
303 csc
->chunks
[1].length_dw
+= RELOC_DWORDS
;
305 *added_domains
= rd
| wd
;
306 return csc
->crelocs
++;
309 static unsigned radeon_drm_cs_add_reloc(struct radeon_winsys_cs
*rcs
,
310 struct radeon_winsys_cs_handle
*buf
,
311 enum radeon_bo_usage usage
,
312 enum radeon_bo_domain domains
,
313 enum radeon_bo_priority priority
)
315 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
316 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
317 enum radeon_bo_domain added_domains
;
318 unsigned index
= radeon_add_reloc(cs
, bo
, usage
, domains
, priority
, &added_domains
);
320 if (added_domains
& RADEON_DOMAIN_GTT
)
321 cs
->csc
->used_gart
+= bo
->base
.size
;
322 if (added_domains
& RADEON_DOMAIN_VRAM
)
323 cs
->csc
->used_vram
+= bo
->base
.size
;
328 static int radeon_drm_cs_get_reloc(struct radeon_winsys_cs
*rcs
,
329 struct radeon_winsys_cs_handle
*buf
)
331 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
333 return radeon_get_reloc(cs
->csc
, (struct radeon_bo
*)buf
);
336 static boolean
radeon_drm_cs_validate(struct radeon_winsys_cs
*rcs
)
338 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
340 cs
->csc
->used_gart
< cs
->ws
->info
.gart_size
* 0.8 &&
341 cs
->csc
->used_vram
< cs
->ws
->info
.vram_size
* 0.8;
344 cs
->csc
->validated_crelocs
= cs
->csc
->crelocs
;
346 /* Remove lately-added relocations. The validation failed with them
347 * and the CS is about to be flushed because of that. Keep only
348 * the already-validated relocations. */
351 for (i
= cs
->csc
->validated_crelocs
; i
< cs
->csc
->crelocs
; i
++) {
352 p_atomic_dec(&cs
->csc
->relocs_bo
[i
]->num_cs_references
);
353 radeon_bo_reference(&cs
->csc
->relocs_bo
[i
], NULL
);
355 cs
->csc
->crelocs
= cs
->csc
->validated_crelocs
;
357 /* Flush if there are any relocs. Clean up otherwise. */
358 if (cs
->csc
->crelocs
) {
359 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
361 radeon_cs_context_cleanup(cs
->csc
);
363 assert(cs
->base
.cdw
== 0);
364 if (cs
->base
.cdw
!= 0) {
365 fprintf(stderr
, "radeon: Unexpected error in %s.\n", __func__
);
372 static boolean
radeon_drm_cs_memory_below_limit(struct radeon_winsys_cs
*rcs
, uint64_t vram
, uint64_t gtt
)
374 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
376 (cs
->csc
->used_gart
+ gtt
) < cs
->ws
->info
.gart_size
* 0.7 &&
377 (cs
->csc
->used_vram
+ vram
) < cs
->ws
->info
.vram_size
* 0.7;
382 void radeon_drm_cs_emit_ioctl_oneshot(struct radeon_drm_cs
*cs
, struct radeon_cs_context
*csc
)
386 if (drmCommandWriteRead(csc
->fd
, DRM_RADEON_CS
,
387 &csc
->cs
, sizeof(struct drm_radeon_cs
))) {
388 if (debug_get_bool_option("RADEON_DUMP_CS", FALSE
)) {
391 fprintf(stderr
, "radeon: The kernel rejected CS, dumping...\n");
392 for (i
= 0; i
< csc
->chunks
[0].length_dw
; i
++) {
393 fprintf(stderr
, "0x%08X\n", csc
->buf
[i
]);
396 fprintf(stderr
, "radeon: The kernel rejected CS, "
397 "see dmesg for more information.\n");
402 radeon_dump_cs_on_lockup(cs
, csc
);
405 for (i
= 0; i
< csc
->crelocs
; i
++)
406 p_atomic_dec(&csc
->relocs_bo
[i
]->num_active_ioctls
);
408 radeon_cs_context_cleanup(csc
);
412 * Make sure previous submission of this cs are completed
414 void radeon_drm_cs_sync_flush(struct radeon_winsys_cs
*rcs
)
416 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
418 /* Wait for any pending ioctl to complete. */
419 if (cs
->ws
->thread
) {
420 pipe_semaphore_wait(&cs
->flush_completed
);
421 pipe_semaphore_signal(&cs
->flush_completed
);
425 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", FALSE
)
427 static void radeon_drm_cs_flush(struct radeon_winsys_cs
*rcs
,
429 struct pipe_fence_handle
**fence
,
430 uint32_t cs_trace_id
)
432 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
433 struct radeon_cs_context
*tmp
;
435 switch (cs
->base
.ring_type
) {
437 /* pad DMA ring to 8 DWs */
438 if (cs
->ws
->info
.chip_class
<= SI
) {
440 OUT_CS(&cs
->base
, 0xf0000000); /* NOP packet */
443 OUT_CS(&cs
->base
, 0x00000000); /* NOP packet */
447 /* pad DMA ring to 8 DWs to meet CP fetch alignment requirements
448 * r6xx, requires at least 4 dw alignment to avoid a hw bug.
450 if (cs
->ws
->info
.chip_class
<= SI
) {
452 OUT_CS(&cs
->base
, 0x80000000); /* type2 nop packet */
455 OUT_CS(&cs
->base
, 0xffff1000); /* type3 nop packet */
459 while (rcs
->cdw
& 15)
460 OUT_CS(&cs
->base
, 0x80000000); /* type2 nop packet */
466 if (rcs
->cdw
> RADEON_MAX_CMDBUF_DWORDS
) {
467 fprintf(stderr
, "radeon: command stream overflowed\n");
471 radeon_fence_reference(fence
, NULL
);
472 *fence
= radeon_cs_create_fence(rcs
);
475 radeon_drm_cs_sync_flush(rcs
);
477 /* Swap command streams. */
482 cs
->cst
->cs_trace_id
= cs_trace_id
;
484 /* If the CS is not empty or overflowed, emit it in a separate thread. */
485 if (cs
->base
.cdw
&& cs
->base
.cdw
<= RADEON_MAX_CMDBUF_DWORDS
&& !debug_get_option_noop()) {
488 crelocs
= cs
->cst
->crelocs
;
490 cs
->cst
->chunks
[0].length_dw
= cs
->base
.cdw
;
492 for (i
= 0; i
< crelocs
; i
++) {
493 /* Update the number of active asynchronous CS ioctls for the buffer. */
494 p_atomic_inc(&cs
->cst
->relocs_bo
[i
]->num_active_ioctls
);
497 switch (cs
->base
.ring_type
) {
499 cs
->cst
->flags
[0] = 0;
500 cs
->cst
->flags
[1] = RADEON_CS_RING_DMA
;
501 cs
->cst
->cs
.num_chunks
= 3;
502 if (cs
->ws
->info
.r600_virtual_address
) {
503 cs
->cst
->flags
[0] |= RADEON_CS_USE_VM
;
508 cs
->cst
->flags
[0] = 0;
509 cs
->cst
->flags
[1] = RADEON_CS_RING_UVD
;
510 cs
->cst
->cs
.num_chunks
= 3;
514 cs
->cst
->flags
[0] = 0;
515 cs
->cst
->flags
[1] = RADEON_CS_RING_VCE
;
516 cs
->cst
->cs
.num_chunks
= 3;
521 cs
->cst
->flags
[0] = 0;
522 cs
->cst
->flags
[1] = RADEON_CS_RING_GFX
;
523 cs
->cst
->cs
.num_chunks
= 2;
524 if (flags
& RADEON_FLUSH_KEEP_TILING_FLAGS
) {
525 cs
->cst
->flags
[0] |= RADEON_CS_KEEP_TILING_FLAGS
;
526 cs
->cst
->cs
.num_chunks
= 3;
528 if (cs
->ws
->info
.r600_virtual_address
) {
529 cs
->cst
->flags
[0] |= RADEON_CS_USE_VM
;
530 cs
->cst
->cs
.num_chunks
= 3;
532 if (flags
& RADEON_FLUSH_END_OF_FRAME
) {
533 cs
->cst
->flags
[0] |= RADEON_CS_END_OF_FRAME
;
534 cs
->cst
->cs
.num_chunks
= 3;
536 if (flags
& RADEON_FLUSH_COMPUTE
) {
537 cs
->cst
->flags
[1] = RADEON_CS_RING_COMPUTE
;
538 cs
->cst
->cs
.num_chunks
= 3;
543 if (cs
->ws
->thread
) {
544 pipe_semaphore_wait(&cs
->flush_completed
);
545 radeon_drm_ws_queue_cs(cs
->ws
, cs
);
546 if (!(flags
& RADEON_FLUSH_ASYNC
))
547 radeon_drm_cs_sync_flush(rcs
);
549 radeon_drm_cs_emit_ioctl_oneshot(cs
, cs
->cst
);
552 radeon_cs_context_cleanup(cs
->cst
);
555 /* Prepare a new CS. */
556 cs
->base
.buf
= cs
->csc
->buf
;
559 cs
->ws
->num_cs_flushes
++;
562 static void radeon_drm_cs_destroy(struct radeon_winsys_cs
*rcs
)
564 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
566 radeon_drm_cs_sync_flush(rcs
);
567 pipe_semaphore_destroy(&cs
->flush_completed
);
568 radeon_cs_context_cleanup(&cs
->csc1
);
569 radeon_cs_context_cleanup(&cs
->csc2
);
570 p_atomic_dec(&cs
->ws
->num_cs
);
571 radeon_destroy_cs_context(&cs
->csc1
);
572 radeon_destroy_cs_context(&cs
->csc2
);
576 static boolean
radeon_bo_is_referenced(struct radeon_winsys_cs
*rcs
,
577 struct radeon_winsys_cs_handle
*_buf
,
578 enum radeon_bo_usage usage
)
580 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
581 struct radeon_bo
*bo
= (struct radeon_bo
*)_buf
;
584 if (!bo
->num_cs_references
)
587 index
= radeon_get_reloc(cs
->csc
, bo
);
591 if ((usage
& RADEON_USAGE_WRITE
) && cs
->csc
->relocs
[index
].write_domain
)
593 if ((usage
& RADEON_USAGE_READ
) && cs
->csc
->relocs
[index
].read_domains
)
601 static struct pipe_fence_handle
*
602 radeon_cs_create_fence(struct radeon_winsys_cs
*rcs
)
604 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
605 struct pb_buffer
*fence
;
607 /* Create a fence, which is a dummy BO. */
608 fence
= cs
->ws
->base
.buffer_create(&cs
->ws
->base
, 1, 1, TRUE
,
610 /* Add the fence as a dummy relocation. */
611 cs
->ws
->base
.cs_add_reloc(rcs
, cs
->ws
->base
.buffer_get_cs_handle(fence
),
612 RADEON_USAGE_READWRITE
, RADEON_DOMAIN_GTT
,
614 return (struct pipe_fence_handle
*)fence
;
617 static bool radeon_fence_wait(struct radeon_winsys
*ws
,
618 struct pipe_fence_handle
*fence
,
621 struct pb_buffer
*rfence
= (struct pb_buffer
*)fence
;
624 return !ws
->buffer_is_busy(rfence
, RADEON_USAGE_READWRITE
);
626 if (timeout
!= PIPE_TIMEOUT_INFINITE
) {
627 int64_t start_time
= os_time_get();
629 /* Convert to microseconds. */
632 /* Wait in a loop. */
633 while (ws
->buffer_is_busy(rfence
, RADEON_USAGE_READWRITE
)) {
634 if (os_time_get() - start_time
>= timeout
) {
642 ws
->buffer_wait(rfence
, RADEON_USAGE_READWRITE
);
646 static void radeon_fence_reference(struct pipe_fence_handle
**dst
,
647 struct pipe_fence_handle
*src
)
649 pb_reference((struct pb_buffer
**)dst
, (struct pb_buffer
*)src
);
652 void radeon_drm_cs_init_functions(struct radeon_drm_winsys
*ws
)
654 ws
->base
.cs_create
= radeon_drm_cs_create
;
655 ws
->base
.cs_destroy
= radeon_drm_cs_destroy
;
656 ws
->base
.cs_add_reloc
= radeon_drm_cs_add_reloc
;
657 ws
->base
.cs_get_reloc
= radeon_drm_cs_get_reloc
;
658 ws
->base
.cs_validate
= radeon_drm_cs_validate
;
659 ws
->base
.cs_memory_below_limit
= radeon_drm_cs_memory_below_limit
;
660 ws
->base
.cs_flush
= radeon_drm_cs_flush
;
661 ws
->base
.cs_is_buffer_referenced
= radeon_bo_is_referenced
;
662 ws
->base
.cs_sync_flush
= radeon_drm_cs_sync_flush
;
663 ws
->base
.fence_wait
= radeon_fence_wait
;
664 ws
->base
.fence_reference
= radeon_fence_reference
;