src/gallium/winsys/radeon/drm/radeon_drm_cs.c

   1 /*
   2  * Copyright © 2008 Jérôme Glisse
   3  * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Marek Olšák <maraeo@gmail.com>
  30  *
  31  * Based on work from libdrm_radeon by:
  32  *      Aapo Tahkola <aet@rasterburn.org>
  33  *      Nicolai Haehnle <prefect_@gmx.net>
  34  *      Jérôme Glisse <glisse@freedesktop.org>
  35  */
  36
  37 /*
  38     This file replaces libdrm's radeon_cs_gem with our own implemention.
  39     It's optimized specifically for Radeon DRM.
  40     Reloc writes and space checking are faster and simpler than their
  41     counterparts in libdrm (the time complexity of all the functions
  42     is O(1) in nearly all scenarios, thanks to hashing).
  43
  44     It works like this:
  45
  46     cs_add_reloc(cs, buf, read_domain, write_domain) adds a new relocation and
  47     also adds the size of 'buf' to the used_gart and used_vram winsys variables
  48     based on the domains, which are simply or'd for the accounting purposes.
  49     The adding is skipped if the reloc is already present in the list, but it
  50     accounts any newly-referenced domains.
  51
  52     cs_validate is then called, which just checks:
  53         used_vram/gart < vram/gart_size * 0.8
  54     The 0.8 number allows for some memory fragmentation. If the validation
  55     fails, the pipe driver flushes CS and tries do the validation again,
  56     i.e. it validates only that one operation. If it fails again, it drops
  57     the operation on the floor and prints some nasty message to stderr.
  58     (done in the pipe driver)
  59
  60     cs_write_reloc(cs, buf) just writes a reloc that has been added using
  61     cs_add_reloc. The read_domain and write_domain parameters have been removed,
  62     because we already specify them in cs_add_reloc.
  63 */
  64
  65 #include "radeon_drm_cs.h"
  66
  67 #include "util/u_memory.h"
  68
  69 #include <stdio.h>
  70 #include <stdlib.h>
  71 #include <stdint.h>
  72 #include <xf86drm.h>
  73
  74 /*
  75  * this are copy from radeon_drm, once an updated libdrm is released
  76  * we should bump configure.ac requirement for it and remove the following
  77  * field
  78  */
  79 #ifndef RADEON_CHUNK_ID_FLAGS
  80 #define RADEON_CHUNK_ID_FLAGS       0x03
  81
  82 /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
  83 #define RADEON_CS_KEEP_TILING_FLAGS 0x01
  84 #endif
  85
  86 #ifndef RADEON_CS_USE_VM
  87 #define RADEON_CS_USE_VM            0x02
  88 /* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
  89 #define RADEON_CS_RING_GFX          0
  90 #define RADEON_CS_RING_COMPUTE      1
  91 #endif
  92
  93 #ifndef RADEON_CS_RING_DMA
  94 #define RADEON_CS_RING_DMA          2
  95 #endif
  96
  97 #ifndef RADEON_CS_END_OF_FRAME
  98 #define RADEON_CS_END_OF_FRAME      0x04
  99 #endif
 100
 101
 102 #define RELOC_DWORDS (sizeof(struct drm_radeon_cs_reloc) / sizeof(uint32_t))
 103
 104 static boolean radeon_init_cs_context(struct radeon_cs_context *csc,
 105                                       struct radeon_drm_winsys *ws)
 106 {
 107     csc->fd = ws->fd;
 108     csc->nrelocs = 512;
 109     csc->relocs_bo = (struct radeon_bo**)
 110                      CALLOC(1, csc->nrelocs * sizeof(struct radeon_bo*));
 111     if (!csc->relocs_bo) {
 112         return FALSE;
 113     }
 114
 115     csc->relocs = (struct drm_radeon_cs_reloc*)
 116                   CALLOC(1, csc->nrelocs * sizeof(struct drm_radeon_cs_reloc));
 117     if (!csc->relocs) {
 118         FREE(csc->relocs_bo);
 119         return FALSE;
 120     }
 121
 122     csc->chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
 123     csc->chunks[0].length_dw = 0;
 124     csc->chunks[0].chunk_data = (uint64_t)(uintptr_t)csc->buf;
 125     csc->chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
 126     csc->chunks[1].length_dw = 0;
 127     csc->chunks[1].chunk_data = (uint64_t)(uintptr_t)csc->relocs;
 128     csc->chunks[2].chunk_id = RADEON_CHUNK_ID_FLAGS;
 129     csc->chunks[2].length_dw = 2;
 130     csc->chunks[2].chunk_data = (uint64_t)(uintptr_t)&csc->flags;
 131
 132     csc->chunk_array[0] = (uint64_t)(uintptr_t)&csc->chunks[0];
 133     csc->chunk_array[1] = (uint64_t)(uintptr_t)&csc->chunks[1];
 134     csc->chunk_array[2] = (uint64_t)(uintptr_t)&csc->chunks[2];
 135
 136     csc->cs.chunks = (uint64_t)(uintptr_t)csc->chunk_array;
 137     return TRUE;
 138 }
 139
 140 static void radeon_cs_context_cleanup(struct radeon_cs_context *csc)
 141 {
 142     unsigned i;
 143
 144     for (i = 0; i < csc->crelocs; i++) {
 145         p_atomic_dec(&csc->relocs_bo[i]->num_cs_references);
 146         radeon_bo_reference(&csc->relocs_bo[i], NULL);
 147     }
 148
 149     csc->crelocs = 0;
 150     csc->validated_crelocs = 0;
 151     csc->chunks[0].length_dw = 0;
 152     csc->chunks[1].length_dw = 0;
 153     csc->used_gart = 0;
 154     csc->used_vram = 0;
 155     memset(csc->is_handle_added, 0, sizeof(csc->is_handle_added));
 156 }
 157
 158 static void radeon_destroy_cs_context(struct radeon_cs_context *csc)
 159 {
 160     radeon_cs_context_cleanup(csc);
 161     FREE(csc->relocs_bo);
 162     FREE(csc->relocs);
 163 }
 164
 165
 166 static struct radeon_winsys_cs *radeon_drm_cs_create(struct radeon_winsys *rws, enum ring_type ring_type)
 167 {
 168     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 169     struct radeon_drm_cs *cs;
 170
 171     cs = CALLOC_STRUCT(radeon_drm_cs);
 172     if (!cs) {
 173         return NULL;
 174     }
 175     pipe_semaphore_init(&cs->flush_completed, 0);
 176
 177     cs->ws = ws;
 178
 179     if (!radeon_init_cs_context(&cs->csc1, cs->ws)) {
 180         FREE(cs);
 181         return NULL;
 182     }
 183     if (!radeon_init_cs_context(&cs->csc2, cs->ws)) {
 184         radeon_destroy_cs_context(&cs->csc1);
 185         FREE(cs);
 186         return NULL;
 187     }
 188
 189     /* Set the first command buffer as current. */
 190     cs->csc = &cs->csc1;
 191     cs->cst = &cs->csc2;
 192     cs->base.buf = cs->csc->buf;
 193     cs->base.ring_type = ring_type;
 194
 195     p_atomic_inc(&ws->num_cs);
 196     return &cs->base;
 197 }
 198
 199 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
 200
 201 static INLINE void update_reloc_domains(struct drm_radeon_cs_reloc *reloc,
 202                                         enum radeon_bo_domain rd,
 203                                         enum radeon_bo_domain wd,
 204                                         enum radeon_bo_domain *added_domains)
 205 {
 206     *added_domains = (rd | wd) & ~(reloc->read_domains | reloc->write_domain);
 207
 208     reloc->read_domains |= rd;
 209     reloc->write_domain |= wd;
 210 }
 211
 212 int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo *bo)
 213 {
 214     struct drm_radeon_cs_reloc *reloc;
 215     unsigned i;
 216     unsigned hash = bo->handle & (sizeof(csc->is_handle_added)-1);
 217
 218     if (csc->is_handle_added[hash]) {
 219         i = csc->reloc_indices_hashlist[hash];
 220         reloc = &csc->relocs[i];
 221         if (reloc->handle == bo->handle) {
 222             return i;
 223         }
 224
 225         /* Hash collision, look for the BO in the list of relocs linearly. */
 226         for (i = csc->crelocs; i != 0;) {
 227             --i;
 228             reloc = &csc->relocs[i];
 229             if (reloc->handle == bo->handle) {
 230                 /* Put this reloc in the hash list.
 231                  * This will prevent additional hash collisions if there are
 232                  * several consecutive get_reloc calls for the same buffer.
 233                  *
 234                  * Example: Assuming buffers A,B,C collide in the hash list,
 235                  * the following sequence of relocs:
 236                  *         AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
 237                  * will collide here: ^ and here:   ^,
 238                  * meaning that we should get very few collisions in the end. */
 239                 csc->reloc_indices_hashlist[hash] = i;
 240                 /*printf("write_reloc collision, hash: %i, handle: %i\n", hash, bo->handle);*/
 241                 return i;
 242             }
 243         }
 244     }
 245
 246     return -1;
 247 }
 248
 249 static unsigned radeon_add_reloc(struct radeon_drm_cs *cs,
 250                                  struct radeon_bo *bo,
 251                                  enum radeon_bo_usage usage,
 252                                  enum radeon_bo_domain domains,
 253                                  enum radeon_bo_domain *added_domains)
 254 {
 255     struct radeon_cs_context *csc = cs->csc;
 256     struct drm_radeon_cs_reloc *reloc;
 257     unsigned hash = bo->handle & (sizeof(csc->is_handle_added)-1);
 258     enum radeon_bo_domain rd = usage & RADEON_USAGE_READ ? domains : 0;
 259     enum radeon_bo_domain wd = usage & RADEON_USAGE_WRITE ? domains : 0;
 260     bool update_hash = TRUE;
 261     int i;
 262
 263     *added_domains = 0;
 264     if (csc->is_handle_added[hash]) {
 265         i = csc->reloc_indices_hashlist[hash];
 266         reloc = &csc->relocs[i];
 267         if (reloc->handle != bo->handle) {
 268             /* Hash collision, look for the BO in the list of relocs linearly. */
 269             for (i = csc->crelocs - 1; i >= 0; i--) {
 270                 reloc = &csc->relocs[i];
 271                 if (reloc->handle == bo->handle) {
 272                     /*printf("write_reloc collision, hash: %i, handle: %i\n", hash, bo->handle);*/
 273                     break;
 274                 }
 275             }
 276         }
 277
 278         if (i >= 0) {
 279             /* On DMA ring we need to emit as many relocation as there is use of the bo
 280              * thus each time this function is call we should grow add again the bo to
 281              * the relocation buffer
 282              *
 283              * Do not update the hash table if it's dma ring, so that first hash always point
 284              * to first bo relocation which will the one used by the kernel. Following relocation
 285              * will be ignore by the kernel memory placement (but still use by the kernel to
 286              * update the cmd stream with proper buffer offset).
 287              */
 288             update_hash = FALSE;
 289             update_reloc_domains(reloc, rd, wd, added_domains);
 290             if (cs->base.ring_type != RING_DMA) {
 291                 csc->reloc_indices_hashlist[hash] = i;
 292                 return i;
 293             }
 294         }
 295     }
 296
 297     /* New relocation, check if the backing array is large enough. */
 298     if (csc->crelocs >= csc->nrelocs) {
 299         uint32_t size;
 300         csc->nrelocs += 10;
 301
 302         size = csc->nrelocs * sizeof(struct radeon_bo*);
 303         csc->relocs_bo = realloc(csc->relocs_bo, size);
 304
 305         size = csc->nrelocs * sizeof(struct drm_radeon_cs_reloc);
 306         csc->relocs = realloc(csc->relocs, size);
 307
 308         csc->chunks[1].chunk_data = (uint64_t)(uintptr_t)csc->relocs;
 309     }
 310
 311     /* Initialize the new relocation. */
 312     csc->relocs_bo[csc->crelocs] = NULL;
 313     radeon_bo_reference(&csc->relocs_bo[csc->crelocs], bo);
 314     p_atomic_inc(&bo->num_cs_references);
 315     reloc = &csc->relocs[csc->crelocs];
 316     reloc->handle = bo->handle;
 317     reloc->read_domains = rd;
 318     reloc->write_domain = wd;
 319     reloc->flags = 0;
 320
 321     csc->is_handle_added[hash] = TRUE;
 322     if (update_hash) {
 323         csc->reloc_indices_hashlist[hash] = csc->crelocs;
 324     }
 325
 326     csc->chunks[1].length_dw += RELOC_DWORDS;
 327
 328     *added_domains = rd | wd;
 329     return csc->crelocs++;
 330 }
 331
 332 static unsigned radeon_drm_cs_add_reloc(struct radeon_winsys_cs *rcs,
 333                                         struct radeon_winsys_cs_handle *buf,
 334                                         enum radeon_bo_usage usage,
 335                                         enum radeon_bo_domain domains)
 336 {
 337     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 338     struct radeon_bo *bo = (struct radeon_bo*)buf;
 339     enum radeon_bo_domain added_domains;
 340     unsigned index = radeon_add_reloc(cs, bo, usage, domains, &added_domains);
 341
 342     if (added_domains & RADEON_DOMAIN_GTT)
 343         cs->csc->used_gart += bo->base.size;
 344     if (added_domains & RADEON_DOMAIN_VRAM)
 345         cs->csc->used_vram += bo->base.size;
 346
 347     return index;
 348 }
 349
 350 static boolean radeon_drm_cs_validate(struct radeon_winsys_cs *rcs)
 351 {
 352     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 353     boolean status =
 354         cs->csc->used_gart < cs->ws->info.gart_size * 0.8 &&
 355         cs->csc->used_vram < cs->ws->info.vram_size * 0.8;
 356
 357     if (status) {
 358         cs->csc->validated_crelocs = cs->csc->crelocs;
 359     } else {
 360         /* Remove lately-added relocations. The validation failed with them
 361          * and the CS is about to be flushed because of that. Keep only
 362          * the already-validated relocations. */
 363         unsigned i;
 364
 365         for (i = cs->csc->validated_crelocs; i < cs->csc->crelocs; i++) {
 366             p_atomic_dec(&cs->csc->relocs_bo[i]->num_cs_references);
 367             radeon_bo_reference(&cs->csc->relocs_bo[i], NULL);
 368         }
 369         cs->csc->crelocs = cs->csc->validated_crelocs;
 370
 371         /* Flush if there are any relocs. Clean up otherwise. */
 372         if (cs->csc->crelocs) {
 373             cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
 374         } else {
 375             radeon_cs_context_cleanup(cs->csc);
 376
 377             assert(cs->base.cdw == 0);
 378             if (cs->base.cdw != 0) {
 379                 fprintf(stderr, "radeon: Unexpected error in %s.\n", __func__);
 380             }
 381         }
 382     }
 383     return status;
 384 }
 385
 386 static boolean radeon_drm_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64_t gtt)
 387 {
 388     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 389     boolean status =
 390         (cs->csc->used_gart + gtt) < cs->ws->info.gart_size * 0.7 &&
 391         (cs->csc->used_vram + vram) < cs->ws->info.vram_size * 0.7;
 392
 393     return status;
 394 }
 395
 396 static void radeon_drm_cs_write_reloc(struct radeon_winsys_cs *rcs,
 397                                       struct radeon_winsys_cs_handle *buf)
 398 {
 399     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 400     struct radeon_bo *bo = (struct radeon_bo*)buf;
 401     unsigned index = radeon_get_reloc(cs->csc, bo);
 402
 403     if (index == -1) {
 404         fprintf(stderr, "radeon: Cannot get a relocation in %s.\n", __func__);
 405         return;
 406     }
 407
 408     OUT_CS(&cs->base, 0xc0001000);
 409     OUT_CS(&cs->base, index * RELOC_DWORDS);
 410 }
 411
 412 void radeon_drm_cs_emit_ioctl_oneshot(struct radeon_cs_context *csc)
 413 {
 414     unsigned i;
 415
 416     if (drmCommandWriteRead(csc->fd, DRM_RADEON_CS,
 417                             &csc->cs, sizeof(struct drm_radeon_cs))) {
 418         if (debug_get_bool_option("RADEON_DUMP_CS", FALSE)) {
 419             unsigned i;
 420
 421             fprintf(stderr, "radeon: The kernel rejected CS, dumping...\n");
 422             for (i = 0; i < csc->chunks[0].length_dw; i++) {
 423                 fprintf(stderr, "0x%08X\n", csc->buf[i]);
 424             }
 425         } else {
 426             fprintf(stderr, "radeon: The kernel rejected CS, "
 427                     "see dmesg for more information.\n");
 428         }
 429     }
 430
 431     for (i = 0; i < csc->crelocs; i++)
 432         p_atomic_dec(&csc->relocs_bo[i]->num_active_ioctls);
 433
 434     radeon_cs_context_cleanup(csc);
 435 }
 436
 437 /*
 438  * Make sure previous submission of this cs are completed
 439  */
 440 void radeon_drm_cs_sync_flush(struct radeon_winsys_cs *rcs)
 441 {
 442     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 443
 444     /* Wait for any pending ioctl to complete. */
 445     if (cs->ws->thread && cs->flush_started) {
 446         pipe_semaphore_wait(&cs->flush_completed);
 447         cs->flush_started = 0;
 448     }
 449 }
 450
 451 DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", FALSE)
 452
 453 static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs, unsigned flags)
 454 {
 455     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 456     struct radeon_cs_context *tmp;
 457
 458     if (rcs->cdw > RADEON_MAX_CMDBUF_DWORDS) {
 459        fprintf(stderr, "radeon: command stream overflowed\n");
 460     }
 461
 462     radeon_drm_cs_sync_flush(rcs);
 463
 464     /* Flip command streams. */
 465     tmp = cs->csc;
 466     cs->csc = cs->cst;
 467     cs->cst = tmp;
 468
 469     /* If the CS is not empty or overflowed, emit it in a separate thread. */
 470     if (cs->base.cdw && cs->base.cdw <= RADEON_MAX_CMDBUF_DWORDS && !debug_get_option_noop()) {
 471         unsigned i, crelocs = cs->cst->crelocs;
 472
 473         cs->cst->chunks[0].length_dw = cs->base.cdw;
 474
 475         for (i = 0; i < crelocs; i++) {
 476             /* Update the number of active asynchronous CS ioctls for the buffer. */
 477             p_atomic_inc(&cs->cst->relocs_bo[i]->num_active_ioctls);
 478         }
 479
 480         switch (cs->base.ring_type) {
 481         case RING_DMA:
 482             cs->cst->flags[0] = 0;
 483             cs->cst->flags[1] = RADEON_CS_RING_DMA;
 484             cs->cst->cs.num_chunks = 3;
 485             if (cs->ws->info.r600_virtual_address) {
 486                 cs->cst->flags[0] |= RADEON_CS_USE_VM;
 487             }
 488             break;
 489         default:
 490         case RING_GFX:
 491             cs->cst->flags[0] = 0;
 492             cs->cst->flags[1] = RADEON_CS_RING_GFX;
 493             cs->cst->cs.num_chunks = 2;
 494             if (flags & RADEON_FLUSH_KEEP_TILING_FLAGS) {
 495                 cs->cst->flags[0] |= RADEON_CS_KEEP_TILING_FLAGS;
 496                 cs->cst->cs.num_chunks = 3;
 497             }
 498             if (cs->ws->info.r600_virtual_address) {
 499                 cs->cst->flags[0] |= RADEON_CS_USE_VM;
 500                 cs->cst->cs.num_chunks = 3;
 501             }
 502             if (flags & RADEON_FLUSH_END_OF_FRAME) {
 503                 cs->cst->flags[0] |= RADEON_CS_END_OF_FRAME;
 504                 cs->cst->cs.num_chunks = 3;
 505             }
 506             if (flags & RADEON_FLUSH_COMPUTE) {
 507                 cs->cst->flags[1] = RADEON_CS_RING_COMPUTE;
 508                 cs->cst->cs.num_chunks = 3;
 509             }
 510             break;
 511         }
 512
 513         if (cs->ws->thread && (flags & RADEON_FLUSH_ASYNC)) {
 514             cs->flush_started = 1;
 515             radeon_drm_ws_queue_cs(cs->ws, cs);
 516         } else {
 517             pipe_mutex_lock(cs->ws->cs_stack_lock);
 518             if (cs->ws->thread) {
 519                 while (p_atomic_read(&cs->ws->ncs)) {
 520                     pipe_condvar_wait(cs->ws->cs_queue_empty, cs->ws->cs_stack_lock);
 521                 }
 522             }
 523             pipe_mutex_unlock(cs->ws->cs_stack_lock);
 524             radeon_drm_cs_emit_ioctl_oneshot(cs->cst);
 525         }
 526     } else {
 527         radeon_cs_context_cleanup(cs->cst);
 528     }
 529
 530     /* Prepare a new CS. */
 531     cs->base.buf = cs->csc->buf;
 532     cs->base.cdw = 0;
 533 }
 534
 535 static void radeon_drm_cs_destroy(struct radeon_winsys_cs *rcs)
 536 {
 537     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 538
 539     radeon_drm_cs_sync_flush(rcs);
 540     pipe_semaphore_destroy(&cs->flush_completed);
 541     radeon_cs_context_cleanup(&cs->csc1);
 542     radeon_cs_context_cleanup(&cs->csc2);
 543     p_atomic_dec(&cs->ws->num_cs);
 544     radeon_destroy_cs_context(&cs->csc1);
 545     radeon_destroy_cs_context(&cs->csc2);
 546     FREE(cs);
 547 }
 548
 549 static void radeon_drm_cs_set_flush(struct radeon_winsys_cs *rcs,
 550                                     void (*flush)(void *ctx, unsigned flags),
 551                                     void *user)
 552 {
 553     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 554
 555     cs->flush_cs = flush;
 556     cs->flush_data = user;
 557 }
 558
 559 static boolean radeon_bo_is_referenced(struct radeon_winsys_cs *rcs,
 560                                        struct radeon_winsys_cs_handle *_buf,
 561                                        enum radeon_bo_usage usage)
 562 {
 563     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 564     struct radeon_bo *bo = (struct radeon_bo*)_buf;
 565     int index;
 566
 567     if (!bo->num_cs_references)
 568         return FALSE;
 569
 570     index = radeon_get_reloc(cs->csc, bo);
 571     if (index == -1)
 572         return FALSE;
 573
 574     if ((usage & RADEON_USAGE_WRITE) && cs->csc->relocs[index].write_domain)
 575         return TRUE;
 576     if ((usage & RADEON_USAGE_READ) && cs->csc->relocs[index].read_domains)
 577         return TRUE;
 578
 579     return FALSE;
 580 }
 581
 582 void radeon_drm_cs_init_functions(struct radeon_drm_winsys *ws)
 583 {
 584     ws->base.cs_create = radeon_drm_cs_create;
 585     ws->base.cs_destroy = radeon_drm_cs_destroy;
 586     ws->base.cs_add_reloc = radeon_drm_cs_add_reloc;
 587     ws->base.cs_validate = radeon_drm_cs_validate;
 588     ws->base.cs_memory_below_limit = radeon_drm_cs_memory_below_limit;
 589     ws->base.cs_write_reloc = radeon_drm_cs_write_reloc;
 590     ws->base.cs_flush = radeon_drm_cs_flush;
 591     ws->base.cs_set_flush_callback = radeon_drm_cs_set_flush;
 592     ws->base.cs_is_buffer_referenced = radeon_bo_is_referenced;
 593     ws->base.cs_sync_flush = radeon_drm_cs_sync_flush;
 594 }