src/gallium/winsys/radeon/drm/radeon_drm_surface.c

   1 /*
   2  * Copyright © 2014 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  *
  26  * Authors:
  27  *   Marek Olšák <maraeo@gmail.com>
  28  */
  29
  30 #include "radeon_drm_winsys.h"
  31 #include "util/u_format.h"
  32 #include <radeon_surface.h>
  33
  34 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
  35 {
  36         unsigned index, tileb;
  37
  38         tileb = 8 * 8 * surf->bpe;
  39         tileb = MIN2(surf->tile_split, tileb);
  40
  41         for (index = 0; tileb > 64; index++)
  42                 tileb >>= 1;
  43
  44         assert(index < 16);
  45         return index;
  46 }
  47
  48 #define   G_009910_MICRO_TILE_MODE(x)          (((x) >> 0) & 0x03)
  49 #define   G_009910_MICRO_TILE_MODE_NEW(x)      (((x) >> 22) & 0x07)
  50
  51 static void set_micro_tile_mode(struct radeon_surf *surf,
  52                                 struct radeon_info *info)
  53 {
  54     uint32_t tile_mode;
  55
  56     if (info->chip_class < SI) {
  57         surf->micro_tile_mode = 0;
  58         return;
  59     }
  60
  61     tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
  62
  63     if (info->chip_class >= CIK)
  64         surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
  65     else
  66         surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
  67 }
  68
  69 static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
  70                                      const struct radeon_surf_level *level_ws)
  71 {
  72     level_drm->offset = level_ws->offset;
  73     level_drm->slice_size = level_ws->slice_size;
  74     level_drm->nblk_x = level_ws->nblk_x;
  75     level_drm->nblk_y = level_ws->nblk_y;
  76     level_drm->pitch_bytes = level_ws->pitch_bytes;
  77     level_drm->mode = level_ws->mode;
  78 }
  79
  80 static void surf_level_drm_to_winsys(struct radeon_surf_level *level_ws,
  81                                      const struct radeon_surface_level *level_drm)
  82 {
  83     level_ws->offset = level_drm->offset;
  84     level_ws->slice_size = level_drm->slice_size;
  85     level_ws->nblk_x = level_drm->nblk_x;
  86     level_ws->nblk_y = level_drm->nblk_y;
  87     level_ws->pitch_bytes = level_drm->pitch_bytes;
  88     level_ws->mode = level_drm->mode;
  89 }
  90
  91 static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
  92                                const struct pipe_resource *tex,
  93                                unsigned flags, unsigned bpe,
  94                                enum radeon_surf_mode mode,
  95                                const struct radeon_surf *surf_ws)
  96 {
  97     int i;
  98
  99     memset(surf_drm, 0, sizeof(*surf_drm));
 100
 101     surf_drm->npix_x = tex->width0;
 102     surf_drm->npix_y = tex->height0;
 103     surf_drm->npix_z = tex->depth0;
 104     surf_drm->blk_w = util_format_get_blockwidth(tex->format);
 105     surf_drm->blk_h = util_format_get_blockheight(tex->format);
 106     surf_drm->blk_d = 1;
 107     surf_drm->array_size = 1;
 108     surf_drm->last_level = tex->last_level;
 109     surf_drm->bpe = bpe;
 110     surf_drm->nsamples = tex->nr_samples ? tex->nr_samples : 1;
 111
 112     surf_drm->flags = flags;
 113     surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, TYPE);
 114     surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, MODE);
 115     surf_drm->flags |= RADEON_SURF_SET(mode, MODE) |
 116                        RADEON_SURF_HAS_SBUFFER_MIPTREE |
 117                        RADEON_SURF_HAS_TILE_MODE_INDEX;
 118
 119     switch (tex->target) {
 120     case PIPE_TEXTURE_1D:
 121             surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
 122             break;
 123     case PIPE_TEXTURE_RECT:
 124     case PIPE_TEXTURE_2D:
 125             surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
 126             break;
 127     case PIPE_TEXTURE_3D:
 128             surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
 129             break;
 130     case PIPE_TEXTURE_1D_ARRAY:
 131             surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
 132             surf_drm->array_size = tex->array_size;
 133             break;
 134     case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
 135             assert(tex->array_size % 6 == 0);
 136             /* fall through */
 137     case PIPE_TEXTURE_2D_ARRAY:
 138             surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
 139             surf_drm->array_size = tex->array_size;
 140             break;
 141     case PIPE_TEXTURE_CUBE:
 142             surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
 143             break;
 144     case PIPE_BUFFER:
 145     default:
 146             assert(0);
 147     }
 148
 149     surf_drm->bo_size = surf_ws->surf_size;
 150     surf_drm->bo_alignment = surf_ws->surf_alignment;
 151
 152     surf_drm->bankw = surf_ws->bankw;
 153     surf_drm->bankh = surf_ws->bankh;
 154     surf_drm->mtilea = surf_ws->mtilea;
 155     surf_drm->tile_split = surf_ws->tile_split;
 156     surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
 157
 158     for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
 159         surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i]);
 160         surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
 161                                  &surf_ws->stencil_level[i]);
 162
 163         surf_drm->tiling_index[i] = surf_ws->tiling_index[i];
 164         surf_drm->stencil_tiling_index[i] = surf_ws->stencil_tiling_index[i];
 165     }
 166 }
 167
 168 static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
 169                                struct radeon_surf *surf_ws,
 170                                const struct radeon_surface *surf_drm)
 171 {
 172     int i;
 173
 174     memset(surf_ws, 0, sizeof(*surf_ws));
 175
 176     surf_ws->blk_w = surf_drm->blk_w;
 177     surf_ws->blk_h = surf_drm->blk_h;
 178     surf_ws->bpe = surf_drm->bpe;
 179     surf_ws->flags = surf_drm->flags;
 180
 181     surf_ws->surf_size = surf_drm->bo_size;
 182     surf_ws->surf_alignment = surf_drm->bo_alignment;
 183
 184     surf_ws->bankw = surf_drm->bankw;
 185     surf_ws->bankh = surf_drm->bankh;
 186     surf_ws->mtilea = surf_drm->mtilea;
 187     surf_ws->tile_split = surf_drm->tile_split;
 188     surf_ws->stencil_tile_split = surf_drm->stencil_tile_split;
 189
 190     surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
 191
 192     for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
 193         surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i]);
 194         surf_level_drm_to_winsys(&surf_ws->stencil_level[i],
 195                                  &surf_drm->stencil_level[i]);
 196
 197         surf_ws->tiling_index[i] = surf_drm->tiling_index[i];
 198         surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
 199     }
 200
 201     set_micro_tile_mode(surf_ws, &ws->info);
 202 }
 203
 204 static int radeon_winsys_surface_init(struct radeon_winsys *rws,
 205                                       const struct pipe_resource *tex,
 206                                       unsigned flags, unsigned bpe,
 207                                       enum radeon_surf_mode mode,
 208                                       struct radeon_surf *surf_ws)
 209 {
 210     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 211     struct radeon_surface surf_drm;
 212     int r;
 213
 214     surf_winsys_to_drm(&surf_drm, tex, flags, bpe, mode, surf_ws);
 215
 216     if (!(surf_ws->flags & RADEON_SURF_IMPORTED)) {
 217        r = radeon_surface_best(ws->surf_man, &surf_drm);
 218        if (r)
 219           return r;
 220     }
 221
 222     r = radeon_surface_init(ws->surf_man, &surf_drm);
 223     if (r)
 224         return r;
 225
 226     surf_drm_to_winsys(ws, surf_ws, &surf_drm);
 227     return 0;
 228 }
 229
 230 void radeon_surface_init_functions(struct radeon_drm_winsys *ws)
 231 {
 232     ws->base.surface_init = radeon_winsys_surface_init;
 233 }