2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Corbin Simpson <MostAwesomeDude@gmail.com>
30 * Joakim Sindholt <opensource@zhasha.com>
31 * Marek Olšák <maraeo@gmail.com>
34 #include "radeon_drm_bo.h"
35 #include "radeon_drm_cs.h"
36 #include "radeon_drm_public.h"
38 #include "pipebuffer/pb_bufmgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_hash_table.h"
44 #include <sys/types.h>
47 #include <radeon_surface.h>
49 #ifndef RADEON_INFO_ACTIVE_CU_COUNT
50 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
53 #ifndef RADEON_INFO_CURRENT_GPU_TEMP
54 #define RADEON_INFO_CURRENT_GPU_TEMP 0x21
55 #define RADEON_INFO_CURRENT_GPU_SCLK 0x22
56 #define RADEON_INFO_CURRENT_GPU_MCLK 0x23
57 #define RADEON_INFO_READ_REG 0x24
60 #define RADEON_INFO_VA_UNMAP_WORKING 0x25
62 #ifndef RADEON_INFO_GPU_RESET_COUNTER
63 #define RADEON_INFO_GPU_RESET_COUNTER 0x26
66 static struct util_hash_table
*fd_tab
= NULL
;
67 pipe_static_mutex(fd_tab_mutex
);
69 /* Enable/disable feature access for one command stream.
70 * If enable == TRUE, return TRUE on success.
71 * Otherwise, return FALSE.
73 * We basically do the same thing kernel does, because we have to deal
74 * with multiple contexts (here command streams) backed by one winsys. */
75 static boolean
radeon_set_fd_access(struct radeon_drm_cs
*applier
,
76 struct radeon_drm_cs
**owner
,
78 unsigned request
, const char *request_name
,
81 struct drm_radeon_info info
;
82 unsigned value
= enable
? 1 : 0;
84 memset(&info
, 0, sizeof(info
));
86 pipe_mutex_lock(*mutex
);
88 /* Early exit if we are sure the request will fail. */
91 pipe_mutex_unlock(*mutex
);
95 if (*owner
!= applier
) {
96 pipe_mutex_unlock(*mutex
);
101 /* Pass through the request to the kernel. */
102 info
.value
= (unsigned long)&value
;
103 info
.request
= request
;
104 if (drmCommandWriteRead(applier
->ws
->fd
, DRM_RADEON_INFO
,
105 &info
, sizeof(info
)) != 0) {
106 pipe_mutex_unlock(*mutex
);
110 /* Update the rights in the winsys. */
114 pipe_mutex_unlock(*mutex
);
121 pipe_mutex_unlock(*mutex
);
125 static boolean
radeon_get_drm_value(int fd
, unsigned request
,
126 const char *errname
, uint32_t *out
)
128 struct drm_radeon_info info
;
131 memset(&info
, 0, sizeof(info
));
133 info
.value
= (unsigned long)out
;
134 info
.request
= request
;
136 retval
= drmCommandWriteRead(fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
139 fprintf(stderr
, "radeon: Failed to get %s, error number %d\n",
147 /* Helper function to do the ioctls needed for setup and init. */
148 static boolean
do_winsys_init(struct radeon_drm_winsys
*ws
)
150 struct drm_radeon_gem_info gem_info
;
152 drmVersionPtr version
;
154 memset(&gem_info
, 0, sizeof(gem_info
));
156 /* We do things in a specific order here.
158 * DRM version first. We need to be sure we're running on a KMS chipset.
159 * This is also for some features.
161 * Then, the PCI ID. This is essential and should return usable numbers
162 * for all Radeons. If this fails, we probably got handed an FD for some
165 * The GEM info is actually bogus on the kernel side, as well as our side
166 * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
167 * we don't actually use the info for anything yet.
169 * The GB and Z pipe requests should always succeed, but they might not
170 * return sensical values for all chipsets, but that's alright because
171 * the pipe drivers already know that.
174 /* Get DRM version. */
175 version
= drmGetVersion(ws
->fd
);
176 if (version
->version_major
!= 2 ||
177 version
->version_minor
< 3) {
178 fprintf(stderr
, "%s: DRM version is %d.%d.%d but this driver is "
179 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
181 version
->version_major
,
182 version
->version_minor
,
183 version
->version_patchlevel
);
184 drmFreeVersion(version
);
188 ws
->info
.drm_major
= version
->version_major
;
189 ws
->info
.drm_minor
= version
->version_minor
;
190 ws
->info
.drm_patchlevel
= version
->version_patchlevel
;
191 drmFreeVersion(version
);
194 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_DEVICE_ID
, "PCI ID",
199 switch (ws
->info
.pci_id
) {
200 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
201 #include "pci_ids/r300_pci_ids.h"
204 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
205 #include "pci_ids/r600_pci_ids.h"
208 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
209 #include "pci_ids/radeonsi_pci_ids.h"
213 fprintf(stderr
, "radeon: Invalid PCI ID.\n");
217 switch (ws
->info
.family
) {
220 fprintf(stderr
, "radeon: Unknown family.\n");
230 ws
->info
.chip_class
= R300
;
232 case CHIP_R420
: /* R4xx-based cores. */
241 ws
->info
.chip_class
= R400
;
243 case CHIP_RV515
: /* R5xx-based cores. */
249 ws
->info
.chip_class
= R500
;
259 ws
->info
.chip_class
= R600
;
265 ws
->info
.chip_class
= R700
;
278 ws
->info
.chip_class
= EVERGREEN
;
282 ws
->info
.chip_class
= CAYMAN
;
289 ws
->info
.chip_class
= SI
;
296 ws
->info
.chip_class
= CIK
;
301 ws
->info
.has_sdma
= FALSE
;
302 /* DMA is disabled on R700. There is IB corruption and hangs. */
303 if (ws
->info
.chip_class
>= EVERGREEN
&& ws
->info
.drm_minor
>= 27) {
304 ws
->info
.has_sdma
= TRUE
;
307 /* Check for UVD and VCE */
308 ws
->info
.has_uvd
= FALSE
;
309 ws
->info
.vce_fw_version
= 0x00000000;
310 if (ws
->info
.drm_minor
>= 32) {
311 uint32_t value
= RADEON_CS_RING_UVD
;
312 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_RING_WORKING
,
313 "UVD Ring working", &value
))
314 ws
->info
.has_uvd
= value
;
316 value
= RADEON_CS_RING_VCE
;
317 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_RING_WORKING
,
318 NULL
, &value
) && value
) {
320 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_VCE_FW_VERSION
,
321 "VCE FW version", &value
))
322 ws
->info
.vce_fw_version
= value
;
326 /* Check for userptr support. */
328 struct drm_radeon_gem_userptr args
= {0};
330 /* If the ioctl doesn't exist, -EINVAL is returned.
332 * If the ioctl exists, it should return -EACCES
333 * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
336 ws
->info
.has_userptr
=
337 drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_USERPTR
,
338 &args
, sizeof(args
)) == -EACCES
;
342 retval
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_INFO
,
343 &gem_info
, sizeof(gem_info
));
345 fprintf(stderr
, "radeon: Failed to get MM info, error number %d\n",
349 ws
->info
.gart_size
= gem_info
.gart_size
;
350 ws
->info
.vram_size
= gem_info
.vram_size
;
352 /* Get max clock frequency info and convert it to MHz */
353 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SCLK
, NULL
,
354 &ws
->info
.max_shader_clock
);
355 ws
->info
.max_shader_clock
/= 1000;
357 radeon_get_drm_value(ws
->fd
, RADEON_INFO_SI_BACKEND_ENABLED_MASK
, NULL
,
358 &ws
->info
.enabled_rb_mask
);
360 ws
->num_cpus
= sysconf(_SC_NPROCESSORS_ONLN
);
362 /* Generation-specific queries. */
363 if (ws
->gen
== DRV_R300
) {
364 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_GB_PIPES
,
366 &ws
->info
.r300_num_gb_pipes
))
369 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_Z_PIPES
,
371 &ws
->info
.r300_num_z_pipes
))
374 else if (ws
->gen
>= DRV_R600
) {
375 if (ws
->info
.drm_minor
>= 9 &&
376 !radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BACKENDS
,
378 &ws
->info
.num_render_backends
))
381 /* get the GPU counter frequency, failure is not fatal */
382 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CLOCK_CRYSTAL_FREQ
, NULL
,
383 &ws
->info
.clock_crystal_freq
);
385 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TILING_CONFIG
, NULL
,
386 &ws
->info
.r600_tiling_config
);
388 if (ws
->info
.drm_minor
>= 11) {
389 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_TILE_PIPES
, NULL
,
390 &ws
->info
.num_tile_pipes
);
392 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_BACKEND_MAP
, NULL
,
393 &ws
->info
.r600_gb_backend_map
))
394 ws
->info
.r600_gb_backend_map_valid
= TRUE
;
397 ws
->info
.has_virtual_memory
= FALSE
;
398 if (ws
->info
.drm_minor
>= 13) {
399 uint32_t ib_vm_max_size
;
401 ws
->info
.has_virtual_memory
= TRUE
;
402 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_VA_START
, NULL
,
404 ws
->info
.has_virtual_memory
= FALSE
;
405 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_IB_VM_MAX_SIZE
, NULL
,
407 ws
->info
.has_virtual_memory
= FALSE
;
408 radeon_get_drm_value(ws
->fd
, RADEON_INFO_VA_UNMAP_WORKING
, NULL
,
409 &ws
->va_unmap_working
);
411 if (ws
->gen
== DRV_R600
&& !debug_get_bool_option("RADEON_VA", FALSE
))
412 ws
->info
.has_virtual_memory
= FALSE
;
415 /* Get max pipes, this is only needed for compute shaders. All evergreen+
416 * chips have at least 2 pipes, so we use 2 as a default. */
417 ws
->info
.r600_max_quad_pipes
= 2;
418 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_PIPES
, NULL
,
419 &ws
->info
.r600_max_quad_pipes
);
421 /* All GPUs have at least one compute unit */
422 ws
->info
.num_good_compute_units
= 1;
423 radeon_get_drm_value(ws
->fd
, RADEON_INFO_ACTIVE_CU_COUNT
, NULL
,
424 &ws
->info
.num_good_compute_units
);
426 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SE
, NULL
,
429 if (!ws
->info
.max_se
) {
430 switch (ws
->info
.family
) {
449 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SH_PER_SE
, NULL
,
450 &ws
->info
.max_sh_per_se
);
452 radeon_get_drm_value(ws
->fd
, RADEON_INFO_ACCEL_WORKING2
, NULL
,
453 &ws
->accel_working2
);
454 if (ws
->info
.family
== CHIP_HAWAII
&& ws
->accel_working2
< 2) {
455 fprintf(stderr
, "radeon: GPU acceleration for Hawaii disabled, "
456 "returned accel_working2 value %u is smaller than 2. "
457 "Please install a newer kernel.\n",
462 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_SI_TILE_MODE_ARRAY
, NULL
,
463 ws
->info
.si_tile_mode_array
)) {
464 ws
->info
.si_tile_mode_array_valid
= TRUE
;
467 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY
, NULL
,
468 ws
->info
.cik_macrotile_mode_array
)) {
469 ws
->info
.cik_macrotile_mode_array_valid
= TRUE
;
472 /* Hawaii with old firmware needs type2 nop packet.
473 * accel_working2 with value 3 indicates the new firmware.
475 ws
->info
.gfx_ib_pad_with_type2
= ws
->info
.chip_class
<= SI
||
476 (ws
->info
.family
== CHIP_HAWAII
&&
477 ws
->accel_working2
< 3);
482 static void radeon_winsys_destroy(struct radeon_winsys
*rws
)
484 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
488 pipe_semaphore_signal(&ws
->cs_queued
);
489 pipe_thread_wait(ws
->thread
);
491 pipe_semaphore_destroy(&ws
->cs_queued
);
493 pipe_mutex_destroy(ws
->hyperz_owner_mutex
);
494 pipe_mutex_destroy(ws
->cmask_owner_mutex
);
495 pipe_mutex_destroy(ws
->cs_stack_lock
);
497 pb_cache_deinit(&ws
->bo_cache
);
499 if (ws
->gen
>= DRV_R600
) {
500 radeon_surface_manager_free(ws
->surf_man
);
503 util_hash_table_destroy(ws
->bo_names
);
504 util_hash_table_destroy(ws
->bo_handles
);
505 util_hash_table_destroy(ws
->bo_vas
);
506 pipe_mutex_destroy(ws
->bo_handles_mutex
);
507 pipe_mutex_destroy(ws
->bo_va_mutex
);
515 static void radeon_query_info(struct radeon_winsys
*rws
,
516 struct radeon_info
*info
)
518 *info
= ((struct radeon_drm_winsys
*)rws
)->info
;
521 static boolean
radeon_cs_request_feature(struct radeon_winsys_cs
*rcs
,
522 enum radeon_feature_id fid
,
525 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
528 case RADEON_FID_R300_HYPERZ_ACCESS
:
529 return radeon_set_fd_access(cs
, &cs
->ws
->hyperz_owner
,
530 &cs
->ws
->hyperz_owner_mutex
,
531 RADEON_INFO_WANT_HYPERZ
, "Hyper-Z",
534 case RADEON_FID_R300_CMASK_ACCESS
:
535 return radeon_set_fd_access(cs
, &cs
->ws
->cmask_owner
,
536 &cs
->ws
->cmask_owner_mutex
,
537 RADEON_INFO_WANT_CMASK
, "AA optimizations",
543 static uint64_t radeon_query_value(struct radeon_winsys
*rws
,
544 enum radeon_value_id value
)
546 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
550 case RADEON_REQUESTED_VRAM_MEMORY
:
551 return ws
->allocated_vram
;
552 case RADEON_REQUESTED_GTT_MEMORY
:
553 return ws
->allocated_gtt
;
554 case RADEON_BUFFER_WAIT_TIME_NS
:
555 return ws
->buffer_wait_time
;
556 case RADEON_TIMESTAMP
:
557 if (ws
->info
.drm_minor
< 20 || ws
->gen
< DRV_R600
) {
562 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TIMESTAMP
, "timestamp",
565 case RADEON_NUM_CS_FLUSHES
:
566 return ws
->num_cs_flushes
;
567 case RADEON_NUM_BYTES_MOVED
:
568 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BYTES_MOVED
,
569 "num-bytes-moved", (uint32_t*)&retval
);
571 case RADEON_VRAM_USAGE
:
572 radeon_get_drm_value(ws
->fd
, RADEON_INFO_VRAM_USAGE
,
573 "vram-usage", (uint32_t*)&retval
);
575 case RADEON_GTT_USAGE
:
576 radeon_get_drm_value(ws
->fd
, RADEON_INFO_GTT_USAGE
,
577 "gtt-usage", (uint32_t*)&retval
);
579 case RADEON_GPU_TEMPERATURE
:
580 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CURRENT_GPU_TEMP
,
581 "gpu-temp", (uint32_t*)&retval
);
583 case RADEON_CURRENT_SCLK
:
584 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CURRENT_GPU_SCLK
,
585 "current-gpu-sclk", (uint32_t*)&retval
);
587 case RADEON_CURRENT_MCLK
:
588 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CURRENT_GPU_MCLK
,
589 "current-gpu-mclk", (uint32_t*)&retval
);
591 case RADEON_GPU_RESET_COUNTER
:
592 radeon_get_drm_value(ws
->fd
, RADEON_INFO_GPU_RESET_COUNTER
,
593 "gpu-reset-counter", (uint32_t*)&retval
);
599 static bool radeon_read_registers(struct radeon_winsys
*rws
,
601 unsigned num_registers
, uint32_t *out
)
603 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
606 for (i
= 0; i
< num_registers
; i
++) {
607 uint32_t reg
= reg_offset
+ i
*4;
609 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_READ_REG
, NULL
, ®
))
616 static unsigned hash_fd(void *key
)
618 int fd
= pointer_to_intptr(key
);
622 return stat
.st_dev
^ stat
.st_ino
^ stat
.st_rdev
;
625 static int compare_fd(void *key1
, void *key2
)
627 int fd1
= pointer_to_intptr(key1
);
628 int fd2
= pointer_to_intptr(key2
);
629 struct stat stat1
, stat2
;
633 return stat1
.st_dev
!= stat2
.st_dev
||
634 stat1
.st_ino
!= stat2
.st_ino
||
635 stat1
.st_rdev
!= stat2
.st_rdev
;
638 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys
*ws
, struct radeon_drm_cs
*cs
)
641 pipe_mutex_lock(ws
->cs_stack_lock
);
642 if (ws
->ncs
>= RING_LAST
) {
643 /* no room left for a flush */
644 pipe_mutex_unlock(ws
->cs_stack_lock
);
647 ws
->cs_stack
[ws
->ncs
++] = cs
;
648 pipe_mutex_unlock(ws
->cs_stack_lock
);
649 pipe_semaphore_signal(&ws
->cs_queued
);
652 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl
, param
)
654 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)param
;
655 struct radeon_drm_cs
*cs
;
659 pipe_semaphore_wait(&ws
->cs_queued
);
663 pipe_mutex_lock(ws
->cs_stack_lock
);
664 cs
= ws
->cs_stack
[0];
665 for (i
= 1; i
< ws
->ncs
; i
++)
666 ws
->cs_stack
[i
- 1] = ws
->cs_stack
[i
];
667 ws
->cs_stack
[--ws
->ncs
] = NULL
;
668 pipe_mutex_unlock(ws
->cs_stack_lock
);
671 radeon_drm_cs_emit_ioctl_oneshot(cs
, cs
->cst
);
672 pipe_semaphore_signal(&cs
->flush_completed
);
675 pipe_mutex_lock(ws
->cs_stack_lock
);
676 for (i
= 0; i
< ws
->ncs
; i
++) {
677 pipe_semaphore_signal(&ws
->cs_stack
[i
]->flush_completed
);
678 ws
->cs_stack
[i
] = NULL
;
681 pipe_mutex_unlock(ws
->cs_stack_lock
);
685 DEBUG_GET_ONCE_BOOL_OPTION(thread
, "RADEON_THREAD", TRUE
)
686 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl
, param
);
688 static bool radeon_winsys_unref(struct radeon_winsys
*ws
)
690 struct radeon_drm_winsys
*rws
= (struct radeon_drm_winsys
*)ws
;
693 /* When the reference counter drops to zero, remove the fd from the table.
694 * This must happen while the mutex is locked, so that
695 * radeon_drm_winsys_create in another thread doesn't get the winsys
696 * from the table when the counter drops to 0. */
697 pipe_mutex_lock(fd_tab_mutex
);
699 destroy
= pipe_reference(&rws
->reference
, NULL
);
700 if (destroy
&& fd_tab
)
701 util_hash_table_remove(fd_tab
, intptr_to_pointer(rws
->fd
));
703 pipe_mutex_unlock(fd_tab_mutex
);
707 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
709 static unsigned handle_hash(void *key
)
711 return PTR_TO_UINT(key
);
714 static int handle_compare(void *key1
, void *key2
)
716 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
719 PUBLIC
struct radeon_winsys
*
720 radeon_drm_winsys_create(int fd
, radeon_screen_create_t screen_create
)
722 struct radeon_drm_winsys
*ws
;
724 pipe_mutex_lock(fd_tab_mutex
);
726 fd_tab
= util_hash_table_create(hash_fd
, compare_fd
);
729 ws
= util_hash_table_get(fd_tab
, intptr_to_pointer(fd
));
731 pipe_reference(NULL
, &ws
->reference
);
732 pipe_mutex_unlock(fd_tab_mutex
);
736 ws
= CALLOC_STRUCT(radeon_drm_winsys
);
738 pipe_mutex_unlock(fd_tab_mutex
);
744 if (!do_winsys_init(ws
))
747 pb_cache_init(&ws
->bo_cache
, 500000, 2.0f
, 0,
748 MIN2(ws
->info
.vram_size
, ws
->info
.gart_size
),
750 radeon_bo_can_reclaim
);
752 if (ws
->gen
>= DRV_R600
) {
753 ws
->surf_man
= radeon_surface_manager_new(ws
->fd
);
759 pipe_reference_init(&ws
->reference
, 1);
762 ws
->base
.unref
= radeon_winsys_unref
;
763 ws
->base
.destroy
= radeon_winsys_destroy
;
764 ws
->base
.query_info
= radeon_query_info
;
765 ws
->base
.cs_request_feature
= radeon_cs_request_feature
;
766 ws
->base
.query_value
= radeon_query_value
;
767 ws
->base
.read_registers
= radeon_read_registers
;
769 radeon_drm_bo_init_functions(ws
);
770 radeon_drm_cs_init_functions(ws
);
771 radeon_surface_init_functions(ws
);
773 pipe_mutex_init(ws
->hyperz_owner_mutex
);
774 pipe_mutex_init(ws
->cmask_owner_mutex
);
775 pipe_mutex_init(ws
->cs_stack_lock
);
777 ws
->bo_names
= util_hash_table_create(handle_hash
, handle_compare
);
778 ws
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
779 ws
->bo_vas
= util_hash_table_create(handle_hash
, handle_compare
);
780 pipe_mutex_init(ws
->bo_handles_mutex
);
781 pipe_mutex_init(ws
->bo_va_mutex
);
782 ws
->va_offset
= ws
->va_start
;
783 list_inithead(&ws
->va_holes
);
785 /* TTM aligns the BO size to the CPU page size */
786 ws
->size_align
= sysconf(_SC_PAGESIZE
);
789 pipe_semaphore_init(&ws
->cs_queued
, 0);
790 if (ws
->num_cpus
> 1 && debug_get_option_thread())
791 ws
->thread
= pipe_thread_create(radeon_drm_cs_emit_ioctl
, ws
);
793 /* Create the screen at the end. The winsys must be initialized
796 * Alternatively, we could create the screen based on "ws->gen"
797 * and link all drivers into one binary blob. */
798 ws
->base
.screen
= screen_create(&ws
->base
);
799 if (!ws
->base
.screen
) {
800 radeon_winsys_destroy(&ws
->base
);
801 pipe_mutex_unlock(fd_tab_mutex
);
805 util_hash_table_set(fd_tab
, intptr_to_pointer(ws
->fd
), ws
);
807 /* We must unlock the mutex once the winsys is fully initialized, so that
808 * other threads attempting to create the winsys from the same fd will
809 * get a fully initialized winsys and not just half-way initialized. */
810 pipe_mutex_unlock(fd_tab_mutex
);
815 pb_cache_deinit(&ws
->bo_cache
);
817 pipe_mutex_unlock(fd_tab_mutex
);
819 radeon_surface_manager_free(ws
->surf_man
);