2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Corbin Simpson <MostAwesomeDude@gmail.com>
30 * Joakim Sindholt <opensource@zhasha.com>
31 * Marek Olšák <maraeo@gmail.com>
34 #include "radeon_drm_bo.h"
35 #include "radeon_drm_cs.h"
36 #include "radeon_drm_public.h"
38 #include "pipebuffer/pb_bufmgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_hash_table.h"
46 * this are copy from radeon_drm, once an updated libdrm is released
47 * we should bump configure.ac requirement for it and remove the following
50 #ifndef RADEON_INFO_TILING_CONFIG
51 #define RADEON_INFO_TILING_CONFIG 6
54 #ifndef RADEON_INFO_WANT_HYPERZ
55 #define RADEON_INFO_WANT_HYPERZ 7
58 #ifndef RADEON_INFO_WANT_CMASK
59 #define RADEON_INFO_WANT_CMASK 8
62 #ifndef RADEON_INFO_CLOCK_CRYSTAL_FREQ
63 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 9
66 #ifndef RADEON_INFO_NUM_BACKENDS
67 #define RADEON_INFO_NUM_BACKENDS 0xa
70 #ifndef RADEON_INFO_NUM_TILE_PIPES
71 #define RADEON_INFO_NUM_TILE_PIPES 0xb
74 #ifndef RADEON_INFO_BACKEND_MAP
75 #define RADEON_INFO_BACKEND_MAP 0xd
78 #ifndef RADEON_INFO_VA_START
79 /* virtual address start, va < start are reserved by the kernel */
80 #define RADEON_INFO_VA_START 0x0e
81 /* maximum size of ib using the virtual memory cs */
82 #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
85 #ifndef RADEON_INFO_MAX_PIPES
86 #define RADEON_INFO_MAX_PIPES 0x10
89 #ifndef RADEON_INFO_TIMESTAMP
90 #define RADEON_INFO_TIMESTAMP 0x11
93 #ifndef RADEON_INFO_RING_WORKING
94 #define RADEON_INFO_RING_WORKING 0x15
97 #ifndef RADEON_CS_RING_UVD
98 #define RADEON_CS_RING_UVD 3
101 static struct util_hash_table
*fd_tab
= NULL
;
103 /* Enable/disable feature access for one command stream.
104 * If enable == TRUE, return TRUE on success.
105 * Otherwise, return FALSE.
107 * We basically do the same thing kernel does, because we have to deal
108 * with multiple contexts (here command streams) backed by one winsys. */
109 static boolean
radeon_set_fd_access(struct radeon_drm_cs
*applier
,
110 struct radeon_drm_cs
**owner
,
112 unsigned request
, const char *request_name
,
115 struct drm_radeon_info info
;
116 unsigned value
= enable
? 1 : 0;
118 memset(&info
, 0, sizeof(info
));
120 pipe_mutex_lock(*mutex
);
122 /* Early exit if we are sure the request will fail. */
125 pipe_mutex_unlock(*mutex
);
129 if (*owner
!= applier
) {
130 pipe_mutex_unlock(*mutex
);
135 /* Pass through the request to the kernel. */
136 info
.value
= (unsigned long)&value
;
137 info
.request
= request
;
138 if (drmCommandWriteRead(applier
->ws
->fd
, DRM_RADEON_INFO
,
139 &info
, sizeof(info
)) != 0) {
140 pipe_mutex_unlock(*mutex
);
144 /* Update the rights in the winsys. */
148 printf("radeon: Acquired access to %s.\n", request_name
);
149 pipe_mutex_unlock(*mutex
);
154 printf("radeon: Released access to %s.\n", request_name
);
157 pipe_mutex_unlock(*mutex
);
161 static boolean
radeon_get_drm_value(int fd
, unsigned request
,
162 const char *errname
, uint32_t *out
)
164 struct drm_radeon_info info
;
167 memset(&info
, 0, sizeof(info
));
169 info
.value
= (unsigned long)out
;
170 info
.request
= request
;
172 retval
= drmCommandWriteRead(fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
175 fprintf(stderr
, "radeon: Failed to get %s, error number %d\n",
183 /* Helper function to do the ioctls needed for setup and init. */
184 static boolean
do_winsys_init(struct radeon_drm_winsys
*ws
)
186 struct drm_radeon_gem_info gem_info
;
188 drmVersionPtr version
;
190 memset(&gem_info
, 0, sizeof(gem_info
));
192 /* We do things in a specific order here.
194 * DRM version first. We need to be sure we're running on a KMS chipset.
195 * This is also for some features.
197 * Then, the PCI ID. This is essential and should return usable numbers
198 * for all Radeons. If this fails, we probably got handed an FD for some
201 * The GEM info is actually bogus on the kernel side, as well as our side
202 * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
203 * we don't actually use the info for anything yet.
205 * The GB and Z pipe requests should always succeed, but they might not
206 * return sensical values for all chipsets, but that's alright because
207 * the pipe drivers already know that.
210 /* Get DRM version. */
211 version
= drmGetVersion(ws
->fd
);
212 if (version
->version_major
!= 2 ||
213 version
->version_minor
< 3) {
214 fprintf(stderr
, "%s: DRM version is %d.%d.%d but this driver is "
215 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
217 version
->version_major
,
218 version
->version_minor
,
219 version
->version_patchlevel
);
220 drmFreeVersion(version
);
224 ws
->info
.drm_major
= version
->version_major
;
225 ws
->info
.drm_minor
= version
->version_minor
;
226 ws
->info
.drm_patchlevel
= version
->version_patchlevel
;
227 drmFreeVersion(version
);
230 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_DEVICE_ID
, "PCI ID",
235 switch (ws
->info
.pci_id
) {
236 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
237 #include "pci_ids/r300_pci_ids.h"
240 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
241 #include "pci_ids/r600_pci_ids.h"
244 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
245 #include "pci_ids/radeonsi_pci_ids.h"
249 fprintf(stderr
, "radeon: Invalid PCI ID.\n");
253 switch (ws
->info
.family
) {
256 fprintf(stderr
, "radeon: Unknown family.\n");
266 ws
->info
.chip_class
= R300
;
268 case CHIP_R420
: /* R4xx-based cores. */
277 ws
->info
.chip_class
= R400
;
279 case CHIP_RV515
: /* R5xx-based cores. */
285 ws
->info
.chip_class
= R500
;
295 ws
->info
.chip_class
= R600
;
301 ws
->info
.chip_class
= R700
;
314 ws
->info
.chip_class
= EVERGREEN
;
318 ws
->info
.chip_class
= CAYMAN
;
324 ws
->info
.chip_class
= TAHITI
;
329 ws
->info
.r600_has_dma
= FALSE
;
330 if (ws
->info
.chip_class
>= R700
&& ws
->info
.drm_minor
>= 27) {
331 ws
->info
.r600_has_dma
= TRUE
;
335 ws
->info
.has_uvd
= FALSE
;
336 if (ws
->info
.drm_minor
>= 32) {
337 uint32_t value
= RADEON_CS_RING_UVD
;
338 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_RING_WORKING
,
339 "UVD Ring working", &value
))
340 ws
->info
.has_uvd
= value
;
344 retval
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_INFO
,
345 &gem_info
, sizeof(gem_info
));
347 fprintf(stderr
, "radeon: Failed to get MM info, error number %d\n",
351 ws
->info
.gart_size
= gem_info
.gart_size
;
352 ws
->info
.vram_size
= gem_info
.vram_size
;
354 ws
->num_cpus
= sysconf(_SC_NPROCESSORS_ONLN
);
356 /* Generation-specific queries. */
357 if (ws
->gen
== DRV_R300
) {
358 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_GB_PIPES
,
360 &ws
->info
.r300_num_gb_pipes
))
363 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_Z_PIPES
,
365 &ws
->info
.r300_num_z_pipes
))
368 else if (ws
->gen
>= DRV_R600
) {
369 if (ws
->info
.drm_minor
>= 9 &&
370 !radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BACKENDS
,
372 &ws
->info
.r600_num_backends
))
375 /* get the GPU counter frequency, failure is not fatal */
376 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CLOCK_CRYSTAL_FREQ
, NULL
,
377 &ws
->info
.r600_clock_crystal_freq
);
379 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TILING_CONFIG
, NULL
,
380 &ws
->info
.r600_tiling_config
);
382 if (ws
->info
.drm_minor
>= 11) {
383 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_TILE_PIPES
, NULL
,
384 &ws
->info
.r600_num_tile_pipes
);
386 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_BACKEND_MAP
, NULL
,
387 &ws
->info
.r600_backend_map
))
388 ws
->info
.r600_backend_map_valid
= TRUE
;
391 ws
->info
.r600_virtual_address
= FALSE
;
392 if (ws
->info
.drm_minor
>= 13) {
393 ws
->info
.r600_virtual_address
= TRUE
;
394 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_VA_START
, NULL
,
395 &ws
->info
.r600_va_start
))
396 ws
->info
.r600_virtual_address
= FALSE
;
397 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_IB_VM_MAX_SIZE
, NULL
,
398 &ws
->info
.r600_ib_vm_max_size
))
399 ws
->info
.r600_virtual_address
= FALSE
;
403 /* Get max pipes, this is only needed for compute shaders. All evergreen+
404 * chips have at least 2 pipes, so we use 2 as a default. */
405 ws
->info
.r600_max_pipes
= 2;
406 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_PIPES
, NULL
,
407 &ws
->info
.r600_max_pipes
);
412 static void radeon_winsys_destroy(struct radeon_winsys
*rws
)
414 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
418 pipe_semaphore_signal(&ws
->cs_queued
);
419 pipe_thread_wait(ws
->thread
);
421 pipe_semaphore_destroy(&ws
->cs_queued
);
422 pipe_condvar_destroy(ws
->cs_queue_empty
);
424 if (!pipe_reference(&ws
->base
.reference
, NULL
)) {
428 pipe_mutex_destroy(ws
->hyperz_owner_mutex
);
429 pipe_mutex_destroy(ws
->cmask_owner_mutex
);
430 pipe_mutex_destroy(ws
->cs_stack_lock
);
432 ws
->cman
->destroy(ws
->cman
);
433 ws
->kman
->destroy(ws
->kman
);
434 if (ws
->gen
>= DRV_R600
) {
435 radeon_surface_manager_free(ws
->surf_man
);
438 util_hash_table_remove(fd_tab
, intptr_to_pointer(ws
->fd
));
443 static void radeon_query_info(struct radeon_winsys
*rws
,
444 struct radeon_info
*info
)
446 *info
= ((struct radeon_drm_winsys
*)rws
)->info
;
449 static boolean
radeon_cs_request_feature(struct radeon_winsys_cs
*rcs
,
450 enum radeon_feature_id fid
,
453 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
456 case RADEON_FID_R300_HYPERZ_ACCESS
:
457 return radeon_set_fd_access(cs
, &cs
->ws
->hyperz_owner
,
458 &cs
->ws
->hyperz_owner_mutex
,
459 RADEON_INFO_WANT_HYPERZ
, "Hyper-Z",
462 case RADEON_FID_R300_CMASK_ACCESS
:
463 return radeon_set_fd_access(cs
, &cs
->ws
->cmask_owner
,
464 &cs
->ws
->cmask_owner_mutex
,
465 RADEON_INFO_WANT_CMASK
, "AA optimizations",
471 static int radeon_drm_winsys_surface_init(struct radeon_winsys
*rws
,
472 struct radeon_surface
*surf
)
474 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
476 return radeon_surface_init(ws
->surf_man
, surf
);
479 static int radeon_drm_winsys_surface_best(struct radeon_winsys
*rws
,
480 struct radeon_surface
*surf
)
482 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
484 return radeon_surface_best(ws
->surf_man
, surf
);
487 static uint64_t radeon_query_timestamp(struct radeon_winsys
*rws
)
489 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
492 if (ws
->info
.drm_minor
< 20 ||
493 ws
->gen
< DRV_R600
) {
498 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TIMESTAMP
, "timestamp",
503 static uint64_t radeon_query_value(struct radeon_winsys
*rws
,
504 enum radeon_value_id value
)
506 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
509 case RADEON_REQUESTED_VRAM_MEMORY
:
510 return ws
->allocated_vram
;
511 case RADEON_REQUESTED_GTT_MEMORY
:
512 return ws
->allocated_gtt
;
513 case RADEON_BUFFER_WAIT_TIME_NS
:
514 return ws
->buffer_wait_time
;
519 static unsigned hash_fd(void *key
)
521 return pointer_to_intptr(key
);
524 static int compare_fd(void *key1
, void *key2
)
526 return pointer_to_intptr(key1
) != pointer_to_intptr(key2
);
529 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys
*ws
, struct radeon_drm_cs
*cs
)
532 pipe_mutex_lock(ws
->cs_stack_lock
);
533 if (p_atomic_read(&ws
->ncs
) >= RING_LAST
) {
534 /* no room left for a flush */
535 pipe_mutex_unlock(ws
->cs_stack_lock
);
538 ws
->cs_stack
[p_atomic_read(&ws
->ncs
)] = cs
;
539 p_atomic_inc(&ws
->ncs
);
540 pipe_mutex_unlock(ws
->cs_stack_lock
);
541 pipe_semaphore_signal(&ws
->cs_queued
);
544 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl
, param
)
546 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)param
;
547 struct radeon_drm_cs
*cs
;
548 unsigned i
, empty_stack
;
551 pipe_semaphore_wait(&ws
->cs_queued
);
555 pipe_mutex_lock(ws
->cs_stack_lock
);
556 cs
= ws
->cs_stack
[0];
557 pipe_mutex_unlock(ws
->cs_stack_lock
);
560 radeon_drm_cs_emit_ioctl_oneshot(cs
->cst
);
562 pipe_mutex_lock(ws
->cs_stack_lock
);
563 for (i
= 1; i
< p_atomic_read(&ws
->ncs
); i
++) {
564 ws
->cs_stack
[i
- 1] = ws
->cs_stack
[i
];
566 ws
->cs_stack
[p_atomic_read(&ws
->ncs
) - 1] = NULL
;
567 empty_stack
= p_atomic_dec_zero(&ws
->ncs
);
569 pipe_condvar_signal(ws
->cs_queue_empty
);
571 pipe_mutex_unlock(ws
->cs_stack_lock
);
573 pipe_semaphore_signal(&cs
->flush_completed
);
580 pipe_mutex_lock(ws
->cs_stack_lock
);
581 for (i
= 0; i
< p_atomic_read(&ws
->ncs
); i
++) {
582 pipe_semaphore_signal(&ws
->cs_stack
[i
]->flush_completed
);
583 ws
->cs_stack
[i
] = NULL
;
585 p_atomic_set(&ws
->ncs
, 0);
586 pipe_condvar_signal(ws
->cs_queue_empty
);
587 pipe_mutex_unlock(ws
->cs_stack_lock
);
591 DEBUG_GET_ONCE_BOOL_OPTION(thread
, "RADEON_THREAD", TRUE
)
592 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl
, param
);
594 struct radeon_winsys
*radeon_drm_winsys_create(int fd
)
596 struct radeon_drm_winsys
*ws
;
599 fd_tab
= util_hash_table_create(hash_fd
, compare_fd
);
602 ws
= util_hash_table_get(fd_tab
, intptr_to_pointer(fd
));
604 pipe_reference(NULL
, &ws
->base
.reference
);
608 ws
= CALLOC_STRUCT(radeon_drm_winsys
);
613 util_hash_table_set(fd_tab
, intptr_to_pointer(fd
), ws
);
615 if (!do_winsys_init(ws
))
618 /* Create managers. */
619 ws
->kman
= radeon_bomgr_create(ws
);
622 ws
->cman
= pb_cache_manager_create(ws
->kman
, 1000000);
626 if (ws
->gen
>= DRV_R600
) {
627 ws
->surf_man
= radeon_surface_manager_new(fd
);
633 pipe_reference_init(&ws
->base
.reference
, 1);
636 ws
->base
.destroy
= radeon_winsys_destroy
;
637 ws
->base
.query_info
= radeon_query_info
;
638 ws
->base
.cs_request_feature
= radeon_cs_request_feature
;
639 ws
->base
.surface_init
= radeon_drm_winsys_surface_init
;
640 ws
->base
.surface_best
= radeon_drm_winsys_surface_best
;
641 ws
->base
.query_timestamp
= radeon_query_timestamp
;
642 ws
->base
.query_value
= radeon_query_value
;
644 radeon_bomgr_init_functions(ws
);
645 radeon_drm_cs_init_functions(ws
);
647 pipe_mutex_init(ws
->hyperz_owner_mutex
);
648 pipe_mutex_init(ws
->cmask_owner_mutex
);
649 pipe_mutex_init(ws
->cs_stack_lock
);
651 p_atomic_set(&ws
->ncs
, 0);
652 pipe_semaphore_init(&ws
->cs_queued
, 0);
653 pipe_condvar_init(ws
->cs_queue_empty
);
654 if (ws
->num_cpus
> 1 && debug_get_option_thread())
655 ws
->thread
= pipe_thread_create(radeon_drm_cs_emit_ioctl
, ws
);
661 ws
->cman
->destroy(ws
->cman
);
663 ws
->kman
->destroy(ws
->kman
);
665 radeon_surface_manager_free(ws
->surf_man
);