2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Corbin Simpson <MostAwesomeDude@gmail.com>
30 * Joakim Sindholt <opensource@zhasha.com>
31 * Marek Olšák <maraeo@gmail.com>
34 #include "radeon_drm_bo.h"
35 #include "radeon_drm_cs.h"
36 #include "radeon_drm_public.h"
38 #include "pipebuffer/pb_bufmgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_hash_table.h"
44 #include <sys/types.h>
47 #include <radeon_surface.h>
49 #ifndef RADEON_INFO_ACTIVE_CU_COUNT
50 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
53 #ifndef RADEON_INFO_CURRENT_GPU_TEMP
54 #define RADEON_INFO_CURRENT_GPU_TEMP 0x21
55 #define RADEON_INFO_CURRENT_GPU_SCLK 0x22
56 #define RADEON_INFO_CURRENT_GPU_MCLK 0x23
57 #define RADEON_INFO_READ_REG 0x24
60 #define RADEON_INFO_VA_UNMAP_WORKING 0x25
62 #ifndef RADEON_INFO_GPU_RESET_COUNTER
63 #define RADEON_INFO_GPU_RESET_COUNTER 0x26
66 static struct util_hash_table
*fd_tab
= NULL
;
67 pipe_static_mutex(fd_tab_mutex
);
69 /* Enable/disable feature access for one command stream.
70 * If enable == TRUE, return TRUE on success.
71 * Otherwise, return FALSE.
73 * We basically do the same thing kernel does, because we have to deal
74 * with multiple contexts (here command streams) backed by one winsys. */
75 static boolean
radeon_set_fd_access(struct radeon_drm_cs
*applier
,
76 struct radeon_drm_cs
**owner
,
78 unsigned request
, const char *request_name
,
81 struct drm_radeon_info info
;
82 unsigned value
= enable
? 1 : 0;
84 memset(&info
, 0, sizeof(info
));
86 pipe_mutex_lock(*mutex
);
88 /* Early exit if we are sure the request will fail. */
91 pipe_mutex_unlock(*mutex
);
95 if (*owner
!= applier
) {
96 pipe_mutex_unlock(*mutex
);
101 /* Pass through the request to the kernel. */
102 info
.value
= (unsigned long)&value
;
103 info
.request
= request
;
104 if (drmCommandWriteRead(applier
->ws
->fd
, DRM_RADEON_INFO
,
105 &info
, sizeof(info
)) != 0) {
106 pipe_mutex_unlock(*mutex
);
110 /* Update the rights in the winsys. */
114 pipe_mutex_unlock(*mutex
);
121 pipe_mutex_unlock(*mutex
);
125 static boolean
radeon_get_drm_value(int fd
, unsigned request
,
126 const char *errname
, uint32_t *out
)
128 struct drm_radeon_info info
;
131 memset(&info
, 0, sizeof(info
));
133 info
.value
= (unsigned long)out
;
134 info
.request
= request
;
136 retval
= drmCommandWriteRead(fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
139 fprintf(stderr
, "radeon: Failed to get %s, error number %d\n",
147 /* Helper function to do the ioctls needed for setup and init. */
148 static boolean
do_winsys_init(struct radeon_drm_winsys
*ws
)
150 struct drm_radeon_gem_info gem_info
;
152 drmVersionPtr version
;
154 memset(&gem_info
, 0, sizeof(gem_info
));
156 /* We do things in a specific order here.
158 * DRM version first. We need to be sure we're running on a KMS chipset.
159 * This is also for some features.
161 * Then, the PCI ID. This is essential and should return usable numbers
162 * for all Radeons. If this fails, we probably got handed an FD for some
165 * The GEM info is actually bogus on the kernel side, as well as our side
166 * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
167 * we don't actually use the info for anything yet.
169 * The GB and Z pipe requests should always succeed, but they might not
170 * return sensical values for all chipsets, but that's alright because
171 * the pipe drivers already know that.
174 /* Get DRM version. */
175 version
= drmGetVersion(ws
->fd
);
176 if (version
->version_major
!= 2 ||
177 version
->version_minor
< 12) {
178 fprintf(stderr
, "%s: DRM version is %d.%d.%d but this driver is "
179 "only compatible with 2.12.0 (kernel 3.2) or later.\n",
181 version
->version_major
,
182 version
->version_minor
,
183 version
->version_patchlevel
);
184 drmFreeVersion(version
);
188 ws
->info
.drm_major
= version
->version_major
;
189 ws
->info
.drm_minor
= version
->version_minor
;
190 ws
->info
.drm_patchlevel
= version
->version_patchlevel
;
191 drmFreeVersion(version
);
194 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_DEVICE_ID
, "PCI ID",
199 switch (ws
->info
.pci_id
) {
200 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
201 #include "pci_ids/r300_pci_ids.h"
204 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
205 #include "pci_ids/r600_pci_ids.h"
208 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
209 #include "pci_ids/radeonsi_pci_ids.h"
213 fprintf(stderr
, "radeon: Invalid PCI ID.\n");
217 switch (ws
->info
.family
) {
220 fprintf(stderr
, "radeon: Unknown family.\n");
230 ws
->info
.chip_class
= R300
;
232 case CHIP_R420
: /* R4xx-based cores. */
241 ws
->info
.chip_class
= R400
;
243 case CHIP_RV515
: /* R5xx-based cores. */
249 ws
->info
.chip_class
= R500
;
259 ws
->info
.chip_class
= R600
;
265 ws
->info
.chip_class
= R700
;
278 ws
->info
.chip_class
= EVERGREEN
;
282 ws
->info
.chip_class
= CAYMAN
;
289 ws
->info
.chip_class
= SI
;
296 ws
->info
.chip_class
= CIK
;
300 /* Set which chips don't have dedicated VRAM. */
301 switch (ws
->info
.family
) {
317 ws
->info
.has_dedicated_vram
= false;
321 ws
->info
.has_dedicated_vram
= true;
325 ws
->info
.has_sdma
= FALSE
;
326 /* DMA is disabled on R700. There is IB corruption and hangs. */
327 if (ws
->info
.chip_class
>= EVERGREEN
&& ws
->info
.drm_minor
>= 27) {
328 ws
->info
.has_sdma
= TRUE
;
331 /* Check for UVD and VCE */
332 ws
->info
.has_uvd
= FALSE
;
333 ws
->info
.vce_fw_version
= 0x00000000;
334 if (ws
->info
.drm_minor
>= 32) {
335 uint32_t value
= RADEON_CS_RING_UVD
;
336 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_RING_WORKING
,
337 "UVD Ring working", &value
))
338 ws
->info
.has_uvd
= value
;
340 value
= RADEON_CS_RING_VCE
;
341 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_RING_WORKING
,
342 NULL
, &value
) && value
) {
344 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_VCE_FW_VERSION
,
345 "VCE FW version", &value
))
346 ws
->info
.vce_fw_version
= value
;
350 /* Check for userptr support. */
352 struct drm_radeon_gem_userptr args
= {0};
354 /* If the ioctl doesn't exist, -EINVAL is returned.
356 * If the ioctl exists, it should return -EACCES
357 * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
360 ws
->info
.has_userptr
=
361 drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_USERPTR
,
362 &args
, sizeof(args
)) == -EACCES
;
366 retval
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_INFO
,
367 &gem_info
, sizeof(gem_info
));
369 fprintf(stderr
, "radeon: Failed to get MM info, error number %d\n",
373 ws
->info
.gart_size
= gem_info
.gart_size
;
374 ws
->info
.vram_size
= gem_info
.vram_size
;
376 /* Get max clock frequency info and convert it to MHz */
377 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SCLK
, NULL
,
378 &ws
->info
.max_shader_clock
);
379 ws
->info
.max_shader_clock
/= 1000;
381 radeon_get_drm_value(ws
->fd
, RADEON_INFO_SI_BACKEND_ENABLED_MASK
, NULL
,
382 &ws
->info
.enabled_rb_mask
);
384 ws
->num_cpus
= sysconf(_SC_NPROCESSORS_ONLN
);
386 /* Generation-specific queries. */
387 if (ws
->gen
== DRV_R300
) {
388 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_GB_PIPES
,
390 &ws
->info
.r300_num_gb_pipes
))
393 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_Z_PIPES
,
395 &ws
->info
.r300_num_z_pipes
))
398 else if (ws
->gen
>= DRV_R600
) {
399 uint32_t tiling_config
= 0;
401 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BACKENDS
,
403 &ws
->info
.num_render_backends
))
406 /* get the GPU counter frequency, failure is not fatal */
407 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CLOCK_CRYSTAL_FREQ
, NULL
,
408 &ws
->info
.clock_crystal_freq
);
410 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TILING_CONFIG
, NULL
,
413 ws
->info
.r600_num_banks
=
414 ws
->info
.chip_class
>= EVERGREEN
?
415 4 << ((tiling_config
& 0xf0) >> 4) :
416 4 << ((tiling_config
& 0x30) >> 4);
418 ws
->info
.pipe_interleave_bytes
=
419 ws
->info
.chip_class
>= EVERGREEN
?
420 256 << ((tiling_config
& 0xf00) >> 8) :
421 256 << ((tiling_config
& 0xc0) >> 6);
423 if (!ws
->info
.pipe_interleave_bytes
)
424 ws
->info
.pipe_interleave_bytes
=
425 ws
->info
.chip_class
>= EVERGREEN
? 512 : 256;
427 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_TILE_PIPES
, NULL
,
428 &ws
->info
.num_tile_pipes
);
430 /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
431 * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
432 * reports a different value (12). Fix it by setting what's in the
433 * GB_TILE_MODE array (8).
435 if (ws
->gen
== DRV_SI
&& ws
->info
.num_tile_pipes
== 12)
436 ws
->info
.num_tile_pipes
= 8;
438 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_BACKEND_MAP
, NULL
,
439 &ws
->info
.r600_gb_backend_map
))
440 ws
->info
.r600_gb_backend_map_valid
= TRUE
;
442 ws
->info
.has_virtual_memory
= FALSE
;
443 if (ws
->info
.drm_minor
>= 13) {
444 uint32_t ib_vm_max_size
;
446 ws
->info
.has_virtual_memory
= TRUE
;
447 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_VA_START
, NULL
,
449 ws
->info
.has_virtual_memory
= FALSE
;
450 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_IB_VM_MAX_SIZE
, NULL
,
452 ws
->info
.has_virtual_memory
= FALSE
;
453 radeon_get_drm_value(ws
->fd
, RADEON_INFO_VA_UNMAP_WORKING
, NULL
,
454 &ws
->va_unmap_working
);
456 if (ws
->gen
== DRV_R600
&& !debug_get_bool_option("RADEON_VA", FALSE
))
457 ws
->info
.has_virtual_memory
= FALSE
;
460 /* Get max pipes, this is only needed for compute shaders. All evergreen+
461 * chips have at least 2 pipes, so we use 2 as a default. */
462 ws
->info
.r600_max_quad_pipes
= 2;
463 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_PIPES
, NULL
,
464 &ws
->info
.r600_max_quad_pipes
);
466 /* All GPUs have at least one compute unit */
467 ws
->info
.num_good_compute_units
= 1;
468 radeon_get_drm_value(ws
->fd
, RADEON_INFO_ACTIVE_CU_COUNT
, NULL
,
469 &ws
->info
.num_good_compute_units
);
471 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SE
, NULL
,
474 if (!ws
->info
.max_se
) {
475 switch (ws
->info
.family
) {
494 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SH_PER_SE
, NULL
,
495 &ws
->info
.max_sh_per_se
);
497 radeon_get_drm_value(ws
->fd
, RADEON_INFO_ACCEL_WORKING2
, NULL
,
498 &ws
->accel_working2
);
499 if (ws
->info
.family
== CHIP_HAWAII
&& ws
->accel_working2
< 2) {
500 fprintf(stderr
, "radeon: GPU acceleration for Hawaii disabled, "
501 "returned accel_working2 value %u is smaller than 2. "
502 "Please install a newer kernel.\n",
507 if (ws
->info
.chip_class
== CIK
) {
508 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY
, NULL
,
509 ws
->info
.cik_macrotile_mode_array
)) {
510 fprintf(stderr
, "radeon: Kernel 3.13 is required for CIK support.\n");
513 ws
->info
.cik_macrotile_mode_array_valid
= TRUE
;
516 if (ws
->info
.chip_class
>= SI
) {
517 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_SI_TILE_MODE_ARRAY
, NULL
,
518 ws
->info
.si_tile_mode_array
)) {
519 fprintf(stderr
, "radeon: Kernel 3.10 is required for SI support.\n");
522 ws
->info
.si_tile_mode_array_valid
= TRUE
;
525 /* Hawaii with old firmware needs type2 nop packet.
526 * accel_working2 with value 3 indicates the new firmware.
528 ws
->info
.gfx_ib_pad_with_type2
= ws
->info
.chip_class
<= SI
||
529 (ws
->info
.family
== CHIP_HAWAII
&&
530 ws
->accel_working2
< 3);
535 static void radeon_winsys_destroy(struct radeon_winsys
*rws
)
537 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
541 pipe_semaphore_signal(&ws
->cs_queued
);
542 pipe_thread_wait(ws
->thread
);
544 pipe_semaphore_destroy(&ws
->cs_queued
);
546 pipe_mutex_destroy(ws
->hyperz_owner_mutex
);
547 pipe_mutex_destroy(ws
->cmask_owner_mutex
);
548 pipe_mutex_destroy(ws
->cs_stack_lock
);
550 pb_cache_deinit(&ws
->bo_cache
);
552 if (ws
->gen
>= DRV_R600
) {
553 radeon_surface_manager_free(ws
->surf_man
);
556 util_hash_table_destroy(ws
->bo_names
);
557 util_hash_table_destroy(ws
->bo_handles
);
558 util_hash_table_destroy(ws
->bo_vas
);
559 pipe_mutex_destroy(ws
->bo_handles_mutex
);
560 pipe_mutex_destroy(ws
->bo_va_mutex
);
568 static void radeon_query_info(struct radeon_winsys
*rws
,
569 struct radeon_info
*info
)
571 *info
= ((struct radeon_drm_winsys
*)rws
)->info
;
574 static boolean
radeon_cs_request_feature(struct radeon_winsys_cs
*rcs
,
575 enum radeon_feature_id fid
,
578 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
581 case RADEON_FID_R300_HYPERZ_ACCESS
:
582 return radeon_set_fd_access(cs
, &cs
->ws
->hyperz_owner
,
583 &cs
->ws
->hyperz_owner_mutex
,
584 RADEON_INFO_WANT_HYPERZ
, "Hyper-Z",
587 case RADEON_FID_R300_CMASK_ACCESS
:
588 return radeon_set_fd_access(cs
, &cs
->ws
->cmask_owner
,
589 &cs
->ws
->cmask_owner_mutex
,
590 RADEON_INFO_WANT_CMASK
, "AA optimizations",
596 static uint64_t radeon_query_value(struct radeon_winsys
*rws
,
597 enum radeon_value_id value
)
599 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
603 case RADEON_REQUESTED_VRAM_MEMORY
:
604 return ws
->allocated_vram
;
605 case RADEON_REQUESTED_GTT_MEMORY
:
606 return ws
->allocated_gtt
;
607 case RADEON_BUFFER_WAIT_TIME_NS
:
608 return ws
->buffer_wait_time
;
609 case RADEON_TIMESTAMP
:
610 if (ws
->info
.drm_minor
< 20 || ws
->gen
< DRV_R600
) {
615 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TIMESTAMP
, "timestamp",
618 case RADEON_NUM_CS_FLUSHES
:
619 return ws
->num_cs_flushes
;
620 case RADEON_NUM_BYTES_MOVED
:
621 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BYTES_MOVED
,
622 "num-bytes-moved", (uint32_t*)&retval
);
624 case RADEON_VRAM_USAGE
:
625 radeon_get_drm_value(ws
->fd
, RADEON_INFO_VRAM_USAGE
,
626 "vram-usage", (uint32_t*)&retval
);
628 case RADEON_GTT_USAGE
:
629 radeon_get_drm_value(ws
->fd
, RADEON_INFO_GTT_USAGE
,
630 "gtt-usage", (uint32_t*)&retval
);
632 case RADEON_GPU_TEMPERATURE
:
633 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CURRENT_GPU_TEMP
,
634 "gpu-temp", (uint32_t*)&retval
);
636 case RADEON_CURRENT_SCLK
:
637 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CURRENT_GPU_SCLK
,
638 "current-gpu-sclk", (uint32_t*)&retval
);
640 case RADEON_CURRENT_MCLK
:
641 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CURRENT_GPU_MCLK
,
642 "current-gpu-mclk", (uint32_t*)&retval
);
644 case RADEON_GPU_RESET_COUNTER
:
645 radeon_get_drm_value(ws
->fd
, RADEON_INFO_GPU_RESET_COUNTER
,
646 "gpu-reset-counter", (uint32_t*)&retval
);
652 static bool radeon_read_registers(struct radeon_winsys
*rws
,
654 unsigned num_registers
, uint32_t *out
)
656 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
659 for (i
= 0; i
< num_registers
; i
++) {
660 uint32_t reg
= reg_offset
+ i
*4;
662 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_READ_REG
, NULL
, ®
))
669 static unsigned hash_fd(void *key
)
671 int fd
= pointer_to_intptr(key
);
675 return stat
.st_dev
^ stat
.st_ino
^ stat
.st_rdev
;
678 static int compare_fd(void *key1
, void *key2
)
680 int fd1
= pointer_to_intptr(key1
);
681 int fd2
= pointer_to_intptr(key2
);
682 struct stat stat1
, stat2
;
686 return stat1
.st_dev
!= stat2
.st_dev
||
687 stat1
.st_ino
!= stat2
.st_ino
||
688 stat1
.st_rdev
!= stat2
.st_rdev
;
691 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys
*ws
, struct radeon_drm_cs
*cs
)
694 pipe_mutex_lock(ws
->cs_stack_lock
);
695 if (ws
->ncs
>= RING_LAST
) {
696 /* no room left for a flush */
697 pipe_mutex_unlock(ws
->cs_stack_lock
);
700 ws
->cs_stack
[ws
->ncs
++] = cs
;
701 pipe_mutex_unlock(ws
->cs_stack_lock
);
702 pipe_semaphore_signal(&ws
->cs_queued
);
705 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl
, param
)
707 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)param
;
708 struct radeon_drm_cs
*cs
;
712 pipe_semaphore_wait(&ws
->cs_queued
);
716 pipe_mutex_lock(ws
->cs_stack_lock
);
717 cs
= ws
->cs_stack
[0];
718 for (i
= 1; i
< ws
->ncs
; i
++)
719 ws
->cs_stack
[i
- 1] = ws
->cs_stack
[i
];
720 ws
->cs_stack
[--ws
->ncs
] = NULL
;
721 pipe_mutex_unlock(ws
->cs_stack_lock
);
724 radeon_drm_cs_emit_ioctl_oneshot(cs
, cs
->cst
);
725 pipe_semaphore_signal(&cs
->flush_completed
);
728 pipe_mutex_lock(ws
->cs_stack_lock
);
729 for (i
= 0; i
< ws
->ncs
; i
++) {
730 pipe_semaphore_signal(&ws
->cs_stack
[i
]->flush_completed
);
731 ws
->cs_stack
[i
] = NULL
;
734 pipe_mutex_unlock(ws
->cs_stack_lock
);
738 DEBUG_GET_ONCE_BOOL_OPTION(thread
, "RADEON_THREAD", TRUE
)
739 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl
, param
);
741 static bool radeon_winsys_unref(struct radeon_winsys
*ws
)
743 struct radeon_drm_winsys
*rws
= (struct radeon_drm_winsys
*)ws
;
746 /* When the reference counter drops to zero, remove the fd from the table.
747 * This must happen while the mutex is locked, so that
748 * radeon_drm_winsys_create in another thread doesn't get the winsys
749 * from the table when the counter drops to 0. */
750 pipe_mutex_lock(fd_tab_mutex
);
752 destroy
= pipe_reference(&rws
->reference
, NULL
);
753 if (destroy
&& fd_tab
)
754 util_hash_table_remove(fd_tab
, intptr_to_pointer(rws
->fd
));
756 pipe_mutex_unlock(fd_tab_mutex
);
760 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
762 static unsigned handle_hash(void *key
)
764 return PTR_TO_UINT(key
);
767 static int handle_compare(void *key1
, void *key2
)
769 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
772 PUBLIC
struct radeon_winsys
*
773 radeon_drm_winsys_create(int fd
, radeon_screen_create_t screen_create
)
775 struct radeon_drm_winsys
*ws
;
777 pipe_mutex_lock(fd_tab_mutex
);
779 fd_tab
= util_hash_table_create(hash_fd
, compare_fd
);
782 ws
= util_hash_table_get(fd_tab
, intptr_to_pointer(fd
));
784 pipe_reference(NULL
, &ws
->reference
);
785 pipe_mutex_unlock(fd_tab_mutex
);
789 ws
= CALLOC_STRUCT(radeon_drm_winsys
);
791 pipe_mutex_unlock(fd_tab_mutex
);
797 if (!do_winsys_init(ws
))
800 pb_cache_init(&ws
->bo_cache
, 500000, 2.0f
, 0,
801 MIN2(ws
->info
.vram_size
, ws
->info
.gart_size
),
803 radeon_bo_can_reclaim
);
805 if (ws
->gen
>= DRV_R600
) {
806 ws
->surf_man
= radeon_surface_manager_new(ws
->fd
);
812 pipe_reference_init(&ws
->reference
, 1);
815 ws
->base
.unref
= radeon_winsys_unref
;
816 ws
->base
.destroy
= radeon_winsys_destroy
;
817 ws
->base
.query_info
= radeon_query_info
;
818 ws
->base
.cs_request_feature
= radeon_cs_request_feature
;
819 ws
->base
.query_value
= radeon_query_value
;
820 ws
->base
.read_registers
= radeon_read_registers
;
822 radeon_drm_bo_init_functions(ws
);
823 radeon_drm_cs_init_functions(ws
);
824 radeon_surface_init_functions(ws
);
826 pipe_mutex_init(ws
->hyperz_owner_mutex
);
827 pipe_mutex_init(ws
->cmask_owner_mutex
);
828 pipe_mutex_init(ws
->cs_stack_lock
);
830 ws
->bo_names
= util_hash_table_create(handle_hash
, handle_compare
);
831 ws
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
832 ws
->bo_vas
= util_hash_table_create(handle_hash
, handle_compare
);
833 pipe_mutex_init(ws
->bo_handles_mutex
);
834 pipe_mutex_init(ws
->bo_va_mutex
);
835 ws
->va_offset
= ws
->va_start
;
836 list_inithead(&ws
->va_holes
);
838 /* TTM aligns the BO size to the CPU page size */
839 ws
->size_align
= sysconf(_SC_PAGESIZE
);
842 pipe_semaphore_init(&ws
->cs_queued
, 0);
843 if (ws
->num_cpus
> 1 && debug_get_option_thread())
844 ws
->thread
= pipe_thread_create(radeon_drm_cs_emit_ioctl
, ws
);
846 /* Create the screen at the end. The winsys must be initialized
849 * Alternatively, we could create the screen based on "ws->gen"
850 * and link all drivers into one binary blob. */
851 ws
->base
.screen
= screen_create(&ws
->base
);
852 if (!ws
->base
.screen
) {
853 radeon_winsys_destroy(&ws
->base
);
854 pipe_mutex_unlock(fd_tab_mutex
);
858 util_hash_table_set(fd_tab
, intptr_to_pointer(ws
->fd
), ws
);
860 /* We must unlock the mutex once the winsys is fully initialized, so that
861 * other threads attempting to create the winsys from the same fd will
862 * get a fully initialized winsys and not just half-way initialized. */
863 pipe_mutex_unlock(fd_tab_mutex
);
868 pb_cache_deinit(&ws
->bo_cache
);
870 pipe_mutex_unlock(fd_tab_mutex
);
872 radeon_surface_manager_free(ws
->surf_man
);