src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 #include "radeon_drm_bo.h"
  29 #include "radeon_drm_cs.h"
  30 #include "radeon_drm_public.h"
  31
  32 #include "util/u_cpu_detect.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_hash_table.h"
  35
  36 #include <xf86drm.h>
  37 #include <stdio.h>
  38 #include <sys/types.h>
  39 #include <sys/stat.h>
  40 #include <unistd.h>
  41 #include <fcntl.h>
  42 #include <radeon_surface.h>
  43
  44 static struct util_hash_table *fd_tab = NULL;
  45 static mtx_t fd_tab_mutex = _MTX_INITIALIZER_NP;
  46
  47 /* Enable/disable feature access for one command stream.
  48  * If enable == true, return true on success.
  49  * Otherwise, return false.
  50  *
  51  * We basically do the same thing kernel does, because we have to deal
  52  * with multiple contexts (here command streams) backed by one winsys. */
  53 static bool radeon_set_fd_access(struct radeon_drm_cs *applier,
  54                                  struct radeon_drm_cs **owner,
  55                                  mtx_t *mutex,
  56                                  unsigned request, const char *request_name,
  57                                  bool enable)
  58 {
  59     struct drm_radeon_info info;
  60     unsigned value = enable ? 1 : 0;
  61
  62     memset(&info, 0, sizeof(info));
  63
  64     mtx_lock(&*mutex);
  65
  66     /* Early exit if we are sure the request will fail. */
  67     if (enable) {
  68         if (*owner) {
  69             mtx_unlock(&*mutex);
  70             return false;
  71         }
  72     } else {
  73         if (*owner != applier) {
  74             mtx_unlock(&*mutex);
  75             return false;
  76         }
  77     }
  78
  79     /* Pass through the request to the kernel. */
  80     info.value = (unsigned long)&value;
  81     info.request = request;
  82     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
  83                             &info, sizeof(info)) != 0) {
  84         mtx_unlock(&*mutex);
  85         return false;
  86     }
  87
  88     /* Update the rights in the winsys. */
  89     if (enable) {
  90         if (value) {
  91             *owner = applier;
  92             mtx_unlock(&*mutex);
  93             return true;
  94         }
  95     } else {
  96         *owner = NULL;
  97     }
  98
  99     mtx_unlock(&*mutex);
 100     return false;
 101 }
 102
 103 static bool radeon_get_drm_value(int fd, unsigned request,
 104                                  const char *errname, uint32_t *out)
 105 {
 106     struct drm_radeon_info info;
 107     int retval;
 108
 109     memset(&info, 0, sizeof(info));
 110
 111     info.value = (unsigned long)out;
 112     info.request = request;
 113
 114     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 115     if (retval) {
 116         if (errname) {
 117             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 118                     errname, retval);
 119         }
 120         return false;
 121     }
 122     return true;
 123 }
 124
 125 /* Helper function to do the ioctls needed for setup and init. */
 126 static bool do_winsys_init(struct radeon_drm_winsys *ws)
 127 {
 128     struct drm_radeon_gem_info gem_info;
 129     int retval;
 130     drmVersionPtr version;
 131
 132     memset(&gem_info, 0, sizeof(gem_info));
 133
 134     /* We do things in a specific order here.
 135      *
 136      * DRM version first. We need to be sure we're running on a KMS chipset.
 137      * This is also for some features.
 138      *
 139      * Then, the PCI ID. This is essential and should return usable numbers
 140      * for all Radeons. If this fails, we probably got handed an FD for some
 141      * non-Radeon card.
 142      *
 143      * The GEM info is actually bogus on the kernel side, as well as our side
 144      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 145      * we don't actually use the info for anything yet.
 146      *
 147      * The GB and Z pipe requests should always succeed, but they might not
 148      * return sensical values for all chipsets, but that's alright because
 149      * the pipe drivers already know that.
 150      */
 151
 152     /* Get DRM version. */
 153     version = drmGetVersion(ws->fd);
 154     if (version->version_major != 2 ||
 155         version->version_minor < 12) {
 156         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 157                 "only compatible with 2.12.0 (kernel 3.2) or later.\n",
 158                 __FUNCTION__,
 159                 version->version_major,
 160                 version->version_minor,
 161                 version->version_patchlevel);
 162         drmFreeVersion(version);
 163         return false;
 164     }
 165
 166     ws->info.drm_major = version->version_major;
 167     ws->info.drm_minor = version->version_minor;
 168     ws->info.drm_patchlevel = version->version_patchlevel;
 169     drmFreeVersion(version);
 170
 171     /* Get PCI ID. */
 172     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 173                               &ws->info.pci_id))
 174         return false;
 175
 176     /* Check PCI ID. */
 177     switch (ws->info.pci_id) {
 178 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 179 #include "pci_ids/r300_pci_ids.h"
 180 #undef CHIPSET
 181
 182 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 183 #include "pci_ids/r600_pci_ids.h"
 184 #undef CHIPSET
 185
 186 #define CHIPSET(pci_id, cfamily) \
 187     case pci_id: \
 188         ws->info.family = CHIP_##cfamily; \
 189         ws->info.name = #cfamily; \
 190         ws->gen = DRV_SI; \
 191         break;
 192 #include "pci_ids/radeonsi_pci_ids.h"
 193 #undef CHIPSET
 194
 195     default:
 196         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 197         return false;
 198     }
 199
 200     switch (ws->info.family) {
 201     default:
 202     case CHIP_UNKNOWN:
 203         fprintf(stderr, "radeon: Unknown family.\n");
 204         return false;
 205     case CHIP_R300:
 206     case CHIP_R350:
 207     case CHIP_RV350:
 208     case CHIP_RV370:
 209     case CHIP_RV380:
 210     case CHIP_RS400:
 211     case CHIP_RC410:
 212     case CHIP_RS480:
 213         ws->info.chip_class = R300;
 214         break;
 215     case CHIP_R420:     /* R4xx-based cores. */
 216     case CHIP_R423:
 217     case CHIP_R430:
 218     case CHIP_R480:
 219     case CHIP_R481:
 220     case CHIP_RV410:
 221     case CHIP_RS600:
 222     case CHIP_RS690:
 223     case CHIP_RS740:
 224         ws->info.chip_class = R400;
 225         break;
 226     case CHIP_RV515:    /* R5xx-based cores. */
 227     case CHIP_R520:
 228     case CHIP_RV530:
 229     case CHIP_R580:
 230     case CHIP_RV560:
 231     case CHIP_RV570:
 232         ws->info.chip_class = R500;
 233         break;
 234     case CHIP_R600:
 235     case CHIP_RV610:
 236     case CHIP_RV630:
 237     case CHIP_RV670:
 238     case CHIP_RV620:
 239     case CHIP_RV635:
 240     case CHIP_RS780:
 241     case CHIP_RS880:
 242         ws->info.chip_class = R600;
 243         break;
 244     case CHIP_RV770:
 245     case CHIP_RV730:
 246     case CHIP_RV710:
 247     case CHIP_RV740:
 248         ws->info.chip_class = R700;
 249         break;
 250     case CHIP_CEDAR:
 251     case CHIP_REDWOOD:
 252     case CHIP_JUNIPER:
 253     case CHIP_CYPRESS:
 254     case CHIP_HEMLOCK:
 255     case CHIP_PALM:
 256     case CHIP_SUMO:
 257     case CHIP_SUMO2:
 258     case CHIP_BARTS:
 259     case CHIP_TURKS:
 260     case CHIP_CAICOS:
 261         ws->info.chip_class = EVERGREEN;
 262         break;
 263     case CHIP_CAYMAN:
 264     case CHIP_ARUBA:
 265         ws->info.chip_class = CAYMAN;
 266         break;
 267     case CHIP_TAHITI:
 268     case CHIP_PITCAIRN:
 269     case CHIP_VERDE:
 270     case CHIP_OLAND:
 271     case CHIP_HAINAN:
 272         ws->info.chip_class = GFX6;
 273         break;
 274     case CHIP_BONAIRE:
 275     case CHIP_KAVERI:
 276     case CHIP_KABINI:
 277     case CHIP_HAWAII:
 278         ws->info.chip_class = GFX7;
 279         break;
 280     }
 281
 282     /* Set which chips don't have dedicated VRAM. */
 283     switch (ws->info.family) {
 284     case CHIP_RS400:
 285     case CHIP_RC410:
 286     case CHIP_RS480:
 287     case CHIP_RS600:
 288     case CHIP_RS690:
 289     case CHIP_RS740:
 290     case CHIP_RS780:
 291     case CHIP_RS880:
 292     case CHIP_PALM:
 293     case CHIP_SUMO:
 294     case CHIP_SUMO2:
 295     case CHIP_ARUBA:
 296     case CHIP_KAVERI:
 297     case CHIP_KABINI:
 298        ws->info.has_dedicated_vram = false;
 299        break;
 300
 301     default:
 302        ws->info.has_dedicated_vram = true;
 303     }
 304
 305     /* Check for dma */
 306     ws->info.num_sdma_rings = 0;
 307     /* DMA is disabled on R700. There is IB corruption and hangs. */
 308     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 309         ws->info.num_sdma_rings = 1;
 310     }
 311
 312     /* Check for UVD and VCE */
 313     ws->info.has_hw_decode = false;
 314     ws->info.vce_fw_version = 0x00000000;
 315     if (ws->info.drm_minor >= 32) {
 316         uint32_t value = RADEON_CS_RING_UVD;
 317         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 318                                  "UVD Ring working", &value))
 319             ws->info.has_hw_decode = value;
 320
 321         value = RADEON_CS_RING_VCE;
 322         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 323                                  NULL, &value) && value) {
 324
 325             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 326                                      "VCE FW version", &value))
 327                 ws->info.vce_fw_version = value;
 328         }
 329     }
 330
 331     /* Check for userptr support. */
 332     {
 333         struct drm_radeon_gem_userptr args = {0};
 334
 335         /* If the ioctl doesn't exist, -EINVAL is returned.
 336          *
 337          * If the ioctl exists, it should return -EACCES
 338          * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
 339          * aren't set.
 340          */
 341         ws->info.has_userptr =
 342             drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
 343                                 &args, sizeof(args)) == -EACCES;
 344     }
 345
 346     /* Get GEM info. */
 347     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 348             &gem_info, sizeof(gem_info));
 349     if (retval) {
 350         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 351                 retval);
 352         return false;
 353     }
 354     ws->info.gart_size = gem_info.gart_size;
 355     ws->info.vram_size = gem_info.vram_size;
 356     ws->info.vram_vis_size = gem_info.vram_visible;
 357     /* Older versions of the kernel driver reported incorrect values, and
 358      * didn't support more than 256MB of visible VRAM anyway
 359      */
 360     if (ws->info.drm_minor < 49)
 361         ws->info.vram_vis_size = MIN2(ws->info.vram_vis_size, 256*1024*1024);
 362
 363     /* Radeon allocates all buffers contiguously, which makes large allocations
 364      * unlikely to succeed. */
 365     if (ws->info.has_dedicated_vram)
 366             ws->info.max_alloc_size = ws->info.vram_size * 0.7;
 367     else
 368             ws->info.max_alloc_size = ws->info.gart_size * 0.7;
 369
 370     if (ws->info.drm_minor < 40)
 371         ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
 372     /* Both 32-bit and 64-bit address spaces only have 4GB. */
 373     ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 3ull*1024*1024*1024);
 374
 375     /* Get max clock frequency info and convert it to MHz */
 376     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 377                          &ws->info.max_shader_clock);
 378     ws->info.max_shader_clock /= 1000;
 379
 380     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 381
 382     /* Generation-specific queries. */
 383     if (ws->gen == DRV_R300) {
 384         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 385                                   "GB pipe count",
 386                                   &ws->info.r300_num_gb_pipes))
 387             return false;
 388
 389         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 390                                   "Z pipe count",
 391                                   &ws->info.r300_num_z_pipes))
 392             return false;
 393     }
 394     else if (ws->gen >= DRV_R600) {
 395         uint32_t tiling_config = 0;
 396
 397         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 398                                   "num backends",
 399                                   &ws->info.num_render_backends))
 400             return false;
 401
 402         /* get the GPU counter frequency, failure is not fatal */
 403         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 404                              &ws->info.clock_crystal_freq);
 405
 406         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 407                              &tiling_config);
 408
 409         ws->info.r600_num_banks =
 410             ws->info.chip_class >= EVERGREEN ?
 411                 4 << ((tiling_config & 0xf0) >> 4) :
 412                 4 << ((tiling_config & 0x30) >> 4);
 413
 414         ws->info.pipe_interleave_bytes =
 415             ws->info.chip_class >= EVERGREEN ?
 416                 256 << ((tiling_config & 0xf00) >> 8) :
 417                 256 << ((tiling_config & 0xc0) >> 6);
 418
 419         if (!ws->info.pipe_interleave_bytes)
 420             ws->info.pipe_interleave_bytes =
 421                 ws->info.chip_class >= EVERGREEN ? 512 : 256;
 422
 423         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 424                              &ws->info.num_tile_pipes);
 425
 426         /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
 427          * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
 428          * reports a different value (12). Fix it by setting what's in the
 429          * GB_TILE_MODE array (8).
 430          */
 431         if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
 432             ws->info.num_tile_pipes = 8;
 433
 434         if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 435                                   &ws->info.r600_gb_backend_map))
 436             ws->info.r600_gb_backend_map_valid = true;
 437
 438         /* Default value. */
 439         ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.num_render_backends);
 440         /*
 441          * This fails (silently) on non-GCN or older kernels, overwriting the
 442          * default enabled_rb_mask with the result of the last query.
 443         */
 444         if (ws->gen >= DRV_SI)
 445             radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
 446                                  &ws->info.enabled_rb_mask);
 447
 448         ws->info.r600_has_virtual_memory = false;
 449         if (ws->info.drm_minor >= 13) {
 450             uint32_t ib_vm_max_size;
 451
 452             ws->info.r600_has_virtual_memory = true;
 453             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 454                                       &ws->va_start))
 455                 ws->info.r600_has_virtual_memory = false;
 456             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 457                                       &ib_vm_max_size))
 458                 ws->info.r600_has_virtual_memory = false;
 459             radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
 460                                  &ws->va_unmap_working);
 461         }
 462         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false))
 463                 ws->info.r600_has_virtual_memory = false;
 464     }
 465
 466     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 467      * chips have at least 2 pipes, so we use 2 as a default. */
 468     ws->info.r600_max_quad_pipes = 2;
 469     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 470                          &ws->info.r600_max_quad_pipes);
 471
 472     /* All GPUs have at least one compute unit */
 473     ws->info.num_good_compute_units = 1;
 474     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 475                          &ws->info.num_good_compute_units);
 476
 477     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 478                          &ws->info.max_se);
 479
 480     switch (ws->info.family) {
 481     case CHIP_HAINAN:
 482     case CHIP_KABINI:
 483         ws->info.num_tcc_blocks = 2;
 484         break;
 485     case CHIP_VERDE:
 486     case CHIP_OLAND:
 487     case CHIP_BONAIRE:
 488     case CHIP_KAVERI:
 489         ws->info.num_tcc_blocks = 4;
 490         break;
 491     case CHIP_PITCAIRN:
 492         ws->info.num_tcc_blocks = 8;
 493         break;
 494     case CHIP_TAHITI:
 495         ws->info.num_tcc_blocks = 12;
 496         break;
 497     case CHIP_HAWAII:
 498         ws->info.num_tcc_blocks = 16;
 499         break;
 500     default:
 501         ws->info.num_tcc_blocks = 0;
 502         break;
 503     }
 504
 505     if (!ws->info.max_se) {
 506         switch (ws->info.family) {
 507         default:
 508             ws->info.max_se = 1;
 509             break;
 510         case CHIP_CYPRESS:
 511         case CHIP_HEMLOCK:
 512         case CHIP_BARTS:
 513         case CHIP_CAYMAN:
 514         case CHIP_TAHITI:
 515         case CHIP_PITCAIRN:
 516         case CHIP_BONAIRE:
 517             ws->info.max_se = 2;
 518             break;
 519         case CHIP_HAWAII:
 520             ws->info.max_se = 4;
 521             break;
 522         }
 523     }
 524
 525     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 526                          &ws->info.max_sh_per_se);
 527     if (ws->gen == DRV_SI) {
 528         ws->info.num_good_cu_per_sh = ws->info.num_good_compute_units /
 529                                       (ws->info.max_se * ws->info.max_sh_per_se);
 530     }
 531
 532     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 533                          &ws->accel_working2);
 534     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 535         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 536                 "returned accel_working2 value %u is smaller than 2. "
 537                 "Please install a newer kernel.\n",
 538                 ws->accel_working2);
 539         return false;
 540     }
 541
 542     if (ws->info.chip_class == GFX7) {
 543         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 544                                   ws->info.cik_macrotile_mode_array)) {
 545             fprintf(stderr, "radeon: Kernel 3.13 is required for Sea Islands support.\n");
 546             return false;
 547         }
 548     }
 549
 550     if (ws->info.chip_class >= GFX6) {
 551         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 552                                   ws->info.si_tile_mode_array)) {
 553             fprintf(stderr, "radeon: Kernel 3.10 is required for Southern Islands support.\n");
 554             return false;
 555         }
 556     }
 557
 558     /* Hawaii with old firmware needs type2 nop packet.
 559      * accel_working2 with value 3 indicates the new firmware.
 560      */
 561     ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= GFX6 ||
 562                                      (ws->info.family == CHIP_HAWAII &&
 563                                       ws->accel_working2 < 3);
 564     ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
 565     ws->info.ib_start_alignment = 4096;
 566     ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
 567     /* HTILE is broken with 1D tiling on old kernels and GFX7. */
 568     ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != GFX7 ||
 569                                              ws->info.drm_minor >= 38;
 570     ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
 571     ws->info.has_bo_metadata = false;
 572     ws->info.has_gpu_reset_status_query = ws->info.drm_minor >= 43;
 573     ws->info.has_eqaa_surface_allocator = false;
 574     ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
 575     ws->info.kernel_flushes_tc_l2_after_ib = true;
 576     /* Old kernels disallowed register writes via COPY_DATA
 577      * that are used for indirect compute dispatches. */
 578     ws->info.has_indirect_compute_dispatch = ws->info.chip_class == GFX7 ||
 579                                              (ws->info.chip_class == GFX6 &&
 580                                               ws->info.drm_minor >= 45);
 581     /* GFX6 doesn't support unaligned loads. */
 582     ws->info.has_unaligned_shader_loads = ws->info.chip_class == GFX7 &&
 583                                           ws->info.drm_minor >= 50;
 584     ws->info.has_sparse_vm_mappings = false;
 585     /* 2D tiling on GFX7 is supported since DRM 2.35.0 */
 586     ws->info.has_2d_tiling = ws->info.chip_class <= GFX6 || ws->info.drm_minor >= 35;
 587     ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
 588     ws->info.max_alignment = 1024*1024;
 589
 590     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
 591
 592     return true;
 593 }
 594
 595 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 596 {
 597     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 598
 599     if (util_queue_is_initialized(&ws->cs_queue))
 600         util_queue_destroy(&ws->cs_queue);
 601
 602     mtx_destroy(&ws->hyperz_owner_mutex);
 603     mtx_destroy(&ws->cmask_owner_mutex);
 604
 605     if (ws->info.r600_has_virtual_memory)
 606         pb_slabs_deinit(&ws->bo_slabs);
 607     pb_cache_deinit(&ws->bo_cache);
 608
 609     if (ws->gen >= DRV_R600) {
 610         radeon_surface_manager_free(ws->surf_man);
 611     }
 612
 613     util_hash_table_destroy(ws->bo_names);
 614     util_hash_table_destroy(ws->bo_handles);
 615     util_hash_table_destroy(ws->bo_vas);
 616     mtx_destroy(&ws->bo_handles_mutex);
 617     mtx_destroy(&ws->vm32.mutex);
 618     mtx_destroy(&ws->vm64.mutex);
 619     mtx_destroy(&ws->bo_fence_lock);
 620
 621     if (ws->fd >= 0)
 622         close(ws->fd);
 623
 624     FREE(rws);
 625 }
 626
 627 static void radeon_query_info(struct radeon_winsys *rws,
 628                               struct radeon_info *info)
 629 {
 630     *info = ((struct radeon_drm_winsys *)rws)->info;
 631 }
 632
 633 static bool radeon_cs_request_feature(struct radeon_cmdbuf *rcs,
 634                                       enum radeon_feature_id fid,
 635                                       bool enable)
 636 {
 637     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 638
 639     switch (fid) {
 640     case RADEON_FID_R300_HYPERZ_ACCESS:
 641         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 642                                     &cs->ws->hyperz_owner_mutex,
 643                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 644                                     enable);
 645
 646     case RADEON_FID_R300_CMASK_ACCESS:
 647         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 648                                     &cs->ws->cmask_owner_mutex,
 649                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 650                                     enable);
 651     }
 652     return false;
 653 }
 654
 655 uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws)
 656 {
 657     uint64_t retval = 0;
 658
 659     if (!ws->info.has_gpu_reset_status_query)
 660         return 0;
 661
 662     radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
 663                          "gpu-reset-counter", (uint32_t*)&retval);
 664     return retval;
 665 }
 666
 667 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 668                                    enum radeon_value_id value)
 669 {
 670     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 671     uint64_t retval = 0;
 672
 673     switch (value) {
 674     case RADEON_REQUESTED_VRAM_MEMORY:
 675         return ws->allocated_vram;
 676     case RADEON_REQUESTED_GTT_MEMORY:
 677         return ws->allocated_gtt;
 678     case RADEON_MAPPED_VRAM:
 679        return ws->mapped_vram;
 680     case RADEON_MAPPED_GTT:
 681        return ws->mapped_gtt;
 682     case RADEON_BUFFER_WAIT_TIME_NS:
 683         return ws->buffer_wait_time;
 684     case RADEON_NUM_MAPPED_BUFFERS:
 685         return ws->num_mapped_buffers;
 686     case RADEON_TIMESTAMP:
 687         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 688             assert(0);
 689             return 0;
 690         }
 691
 692         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 693                              (uint32_t*)&retval);
 694         return retval;
 695     case RADEON_NUM_GFX_IBS:
 696         return ws->num_gfx_IBs;
 697     case RADEON_NUM_SDMA_IBS:
 698         return ws->num_sdma_IBs;
 699     case RADEON_NUM_BYTES_MOVED:
 700         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 701                              "num-bytes-moved", (uint32_t*)&retval);
 702         return retval;
 703     case RADEON_NUM_EVICTIONS:
 704     case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 705     case RADEON_VRAM_VIS_USAGE:
 706     case RADEON_GFX_BO_LIST_COUNTER:
 707     case RADEON_GFX_IB_SIZE_COUNTER:
 708         return 0; /* unimplemented */
 709     case RADEON_VRAM_USAGE:
 710         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 711                              "vram-usage", (uint32_t*)&retval);
 712         return retval;
 713     case RADEON_GTT_USAGE:
 714         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 715                              "gtt-usage", (uint32_t*)&retval);
 716         return retval;
 717     case RADEON_GPU_TEMPERATURE:
 718         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
 719                              "gpu-temp", (uint32_t*)&retval);
 720         return retval;
 721     case RADEON_CURRENT_SCLK:
 722         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
 723                              "current-gpu-sclk", (uint32_t*)&retval);
 724         return retval;
 725     case RADEON_CURRENT_MCLK:
 726         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
 727                              "current-gpu-mclk", (uint32_t*)&retval);
 728         return retval;
 729     case RADEON_CS_THREAD_TIME:
 730         return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 731     }
 732     return 0;
 733 }
 734
 735 static bool radeon_read_registers(struct radeon_winsys *rws,
 736                                   unsigned reg_offset,
 737                                   unsigned num_registers, uint32_t *out)
 738 {
 739     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 740     unsigned i;
 741
 742     for (i = 0; i < num_registers; i++) {
 743         uint32_t reg = reg_offset + i*4;
 744
 745         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg))
 746             return false;
 747         out[i] = reg;
 748     }
 749     return true;
 750 }
 751
 752 static unsigned hash_fd(void *key)
 753 {
 754     int fd = pointer_to_intptr(key);
 755     struct stat stat;
 756     fstat(fd, &stat);
 757
 758     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 759 }
 760
 761 static int compare_fd(void *key1, void *key2)
 762 {
 763     int fd1 = pointer_to_intptr(key1);
 764     int fd2 = pointer_to_intptr(key2);
 765     struct stat stat1, stat2;
 766     fstat(fd1, &stat1);
 767     fstat(fd2, &stat2);
 768
 769     return stat1.st_dev != stat2.st_dev ||
 770            stat1.st_ino != stat2.st_ino ||
 771            stat1.st_rdev != stat2.st_rdev;
 772 }
 773
 774 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", true)
 775
 776 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 777 {
 778     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 779     bool destroy;
 780
 781     /* When the reference counter drops to zero, remove the fd from the table.
 782      * This must happen while the mutex is locked, so that
 783      * radeon_drm_winsys_create in another thread doesn't get the winsys
 784      * from the table when the counter drops to 0. */
 785     mtx_lock(&fd_tab_mutex);
 786
 787     destroy = pipe_reference(&rws->reference, NULL);
 788     if (destroy && fd_tab) {
 789         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 790         if (util_hash_table_count(fd_tab) == 0) {
 791            util_hash_table_destroy(fd_tab);
 792            fd_tab = NULL;
 793         }
 794     }
 795
 796     mtx_unlock(&fd_tab_mutex);
 797     return destroy;
 798 }
 799
 800 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 801
 802 static unsigned handle_hash(void *key)
 803 {
 804     return PTR_TO_UINT(key);
 805 }
 806
 807 static int handle_compare(void *key1, void *key2)
 808 {
 809     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 810 }
 811
 812 static void radeon_pin_threads_to_L3_cache(struct radeon_winsys *ws,
 813                                            unsigned cache)
 814 {
 815     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 816
 817     if (util_queue_is_initialized(&rws->cs_queue)) {
 818         util_pin_thread_to_L3(rws->cs_queue.threads[0], cache,
 819                               util_cpu_caps.cores_per_L3);
 820     }
 821 }
 822
 823 PUBLIC struct radeon_winsys *
 824 radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
 825                          radeon_screen_create_t screen_create)
 826 {
 827     struct radeon_drm_winsys *ws;
 828
 829     mtx_lock(&fd_tab_mutex);
 830     if (!fd_tab) {
 831         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 832     }
 833
 834     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 835     if (ws) {
 836         pipe_reference(NULL, &ws->reference);
 837         mtx_unlock(&fd_tab_mutex);
 838         return &ws->base;
 839     }
 840
 841     ws = CALLOC_STRUCT(radeon_drm_winsys);
 842     if (!ws) {
 843         mtx_unlock(&fd_tab_mutex);
 844         return NULL;
 845     }
 846
 847     ws->fd = fcntl(fd, F_DUPFD_CLOEXEC, 3);
 848
 849     if (!do_winsys_init(ws))
 850         goto fail1;
 851
 852     pb_cache_init(&ws->bo_cache, RADEON_MAX_CACHED_HEAPS,
 853                   500000, ws->check_vm ? 1.0f : 2.0f, 0,
 854                   MIN2(ws->info.vram_size, ws->info.gart_size),
 855                   radeon_bo_destroy,
 856                   radeon_bo_can_reclaim);
 857
 858     if (ws->info.r600_has_virtual_memory) {
 859         /* There is no fundamental obstacle to using slab buffer allocation
 860          * without GPUVM, but enabling it requires making sure that the drivers
 861          * honor the address offset.
 862          */
 863         if (!pb_slabs_init(&ws->bo_slabs,
 864                            RADEON_SLAB_MIN_SIZE_LOG2, RADEON_SLAB_MAX_SIZE_LOG2,
 865                            RADEON_MAX_SLAB_HEAPS,
 866                            ws,
 867                            radeon_bo_can_reclaim_slab,
 868                            radeon_bo_slab_alloc,
 869                            radeon_bo_slab_free))
 870             goto fail_cache;
 871
 872         ws->info.min_alloc_size = 1 << RADEON_SLAB_MIN_SIZE_LOG2;
 873     } else {
 874         ws->info.min_alloc_size = ws->info.gart_page_size;
 875     }
 876
 877     if (ws->gen >= DRV_R600) {
 878         ws->surf_man = radeon_surface_manager_new(ws->fd);
 879         if (!ws->surf_man)
 880             goto fail_slab;
 881     }
 882
 883     /* init reference */
 884     pipe_reference_init(&ws->reference, 1);
 885
 886     /* Set functions. */
 887     ws->base.unref = radeon_winsys_unref;
 888     ws->base.destroy = radeon_winsys_destroy;
 889     ws->base.query_info = radeon_query_info;
 890     ws->base.pin_threads_to_L3_cache = radeon_pin_threads_to_L3_cache;
 891     ws->base.cs_request_feature = radeon_cs_request_feature;
 892     ws->base.query_value = radeon_query_value;
 893     ws->base.read_registers = radeon_read_registers;
 894
 895     radeon_drm_bo_init_functions(ws);
 896     radeon_drm_cs_init_functions(ws);
 897     radeon_surface_init_functions(ws);
 898
 899     (void) mtx_init(&ws->hyperz_owner_mutex, mtx_plain);
 900     (void) mtx_init(&ws->cmask_owner_mutex, mtx_plain);
 901
 902     ws->bo_names = util_hash_table_create(handle_hash, handle_compare);
 903     ws->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 904     ws->bo_vas = util_hash_table_create(handle_hash, handle_compare);
 905     (void) mtx_init(&ws->bo_handles_mutex, mtx_plain);
 906     (void) mtx_init(&ws->vm32.mutex, mtx_plain);
 907     (void) mtx_init(&ws->vm64.mutex, mtx_plain);
 908     (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
 909     list_inithead(&ws->vm32.holes);
 910     list_inithead(&ws->vm64.holes);
 911
 912     /* The kernel currently returns 8MB. Make sure this doesn't change. */
 913     if (ws->va_start > 8 * 1024 * 1024) {
 914         /* Not enough 32-bit address space. */
 915         radeon_winsys_destroy(&ws->base);
 916         mtx_unlock(&fd_tab_mutex);
 917         return NULL;
 918     }
 919
 920     ws->vm32.start = ws->va_start;
 921     ws->vm32.end = 1ull << 32;
 922
 923     /* The maximum is 8GB of virtual address space limited by the kernel.
 924      * It's obviously not enough for bigger cards, like Hawaiis with 4GB
 925      * and 8GB of physical memory and 4GB of GART.
 926      *
 927      * Older kernels set the limit to 4GB, which is even worse, so they only
 928      * have 32-bit address space.
 929      */
 930     if (ws->info.drm_minor >= 41) {
 931         ws->vm64.start = 1ull << 32;
 932         ws->vm64.end = 1ull << 33;
 933     }
 934
 935     /* TTM aligns the BO size to the CPU page size */
 936     ws->info.gart_page_size = sysconf(_SC_PAGESIZE);
 937
 938     if (ws->num_cpus > 1 && debug_get_option_thread())
 939         util_queue_init(&ws->cs_queue, "rcs", 8, 1, 0);
 940
 941     /* Create the screen at the end. The winsys must be initialized
 942      * completely.
 943      *
 944      * Alternatively, we could create the screen based on "ws->gen"
 945      * and link all drivers into one binary blob. */
 946     ws->base.screen = screen_create(&ws->base, config);
 947     if (!ws->base.screen) {
 948         radeon_winsys_destroy(&ws->base);
 949         mtx_unlock(&fd_tab_mutex);
 950         return NULL;
 951     }
 952
 953     util_hash_table_set(fd_tab, intptr_to_pointer(ws->fd), ws);
 954
 955     /* We must unlock the mutex once the winsys is fully initialized, so that
 956      * other threads attempting to create the winsys from the same fd will
 957      * get a fully initialized winsys and not just half-way initialized. */
 958     mtx_unlock(&fd_tab_mutex);
 959
 960     return &ws->base;
 961
 962 fail_slab:
 963     if (ws->info.r600_has_virtual_memory)
 964         pb_slabs_deinit(&ws->bo_slabs);
 965 fail_cache:
 966     pb_cache_deinit(&ws->bo_cache);
 967 fail1:
 968     mtx_unlock(&fd_tab_mutex);
 969     if (ws->surf_man)
 970         radeon_surface_manager_free(ws->surf_man);
 971     if (ws->fd >= 0)
 972         close(ws->fd);
 973
 974     FREE(ws);
 975     return NULL;
 976 }