2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Corbin Simpson <MostAwesomeDude@gmail.com>
30 * Joakim Sindholt <opensource@zhasha.com>
31 * Marek Olšák <maraeo@gmail.com>
34 #include "radeon_drm_bo.h"
35 #include "radeon_drm_cs.h"
36 #include "radeon_drm_public.h"
38 #include "pipebuffer/pb_bufmgr.h"
39 #include "util/u_memory.h"
45 * this are copy from radeon_drm, once an updated libdrm is released
46 * we should bump configure.ac requirement for it and remove the following
49 #ifndef RADEON_INFO_TILING_CONFIG
50 #define RADEON_INFO_TILING_CONFIG 6
53 #ifndef RADEON_INFO_WANT_HYPERZ
54 #define RADEON_INFO_WANT_HYPERZ 7
57 #ifndef RADEON_INFO_WANT_CMASK
58 #define RADEON_INFO_WANT_CMASK 8
61 #ifndef RADEON_INFO_CLOCK_CRYSTAL_FREQ
62 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 9
65 #ifndef RADEON_INFO_NUM_BACKENDS
66 #define RADEON_INFO_NUM_BACKENDS 0xa
69 #ifndef RADEON_INFO_NUM_TILE_PIPES
70 #define RADEON_INFO_NUM_TILE_PIPES 0xb
73 #ifndef RADEON_INFO_BACKEND_MAP
74 #define RADEON_INFO_BACKEND_MAP 0xd
77 #ifndef RADEON_INFO_VA_START
78 /* virtual address start, va < start are reserved by the kernel */
79 #define RADEON_INFO_VA_START 0x0e
80 /* maximum size of ib using the virtual memory cs */
81 #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
84 #ifndef RADEON_INFO_MAX_PIPES
85 #define RADEON_INFO_MAX_PIPES 0x10
89 /* Enable/disable feature access for one command stream.
90 * If enable == TRUE, return TRUE on success.
91 * Otherwise, return FALSE.
93 * We basically do the same thing kernel does, because we have to deal
94 * with multiple contexts (here command streams) backed by one winsys. */
95 static boolean
radeon_set_fd_access(struct radeon_drm_cs
*applier
,
96 struct radeon_drm_cs
**owner
,
98 unsigned request
, boolean enable
)
100 struct drm_radeon_info info
;
101 unsigned value
= enable
? 1 : 0;
103 memset(&info
, 0, sizeof(info
));
105 pipe_mutex_lock(*mutex
);
107 /* Early exit if we are sure the request will fail. */
110 pipe_mutex_unlock(*mutex
);
114 if (*owner
!= applier
) {
115 pipe_mutex_unlock(*mutex
);
120 /* Pass through the request to the kernel. */
121 info
.value
= (unsigned long)&value
;
122 info
.request
= request
;
123 if (drmCommandWriteRead(applier
->ws
->fd
, DRM_RADEON_INFO
,
124 &info
, sizeof(info
)) != 0) {
125 pipe_mutex_unlock(*mutex
);
129 /* Update the rights in the winsys. */
133 fprintf(stderr
, "radeon: Acquired Hyper-Z.\n");
134 pipe_mutex_unlock(*mutex
);
139 fprintf(stderr
, "radeon: Released Hyper-Z.\n");
142 pipe_mutex_unlock(*mutex
);
146 static boolean
radeon_get_drm_value(int fd
, unsigned request
,
147 const char *errname
, uint32_t *out
)
149 struct drm_radeon_info info
;
152 memset(&info
, 0, sizeof(info
));
154 info
.value
= (unsigned long)out
;
155 info
.request
= request
;
157 retval
= drmCommandWriteRead(fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
160 fprintf(stderr
, "radeon: Failed to get %s, error number %d\n",
168 /* Helper function to do the ioctls needed for setup and init. */
169 static boolean
do_winsys_init(struct radeon_drm_winsys
*ws
)
171 struct drm_radeon_gem_info gem_info
;
173 drmVersionPtr version
;
175 memset(&gem_info
, 0, sizeof(gem_info
));
177 /* We do things in a specific order here.
179 * DRM version first. We need to be sure we're running on a KMS chipset.
180 * This is also for some features.
182 * Then, the PCI ID. This is essential and should return usable numbers
183 * for all Radeons. If this fails, we probably got handed an FD for some
186 * The GEM info is actually bogus on the kernel side, as well as our side
187 * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
188 * we don't actually use the info for anything yet.
190 * The GB and Z pipe requests should always succeed, but they might not
191 * return sensical values for all chipsets, but that's alright because
192 * the pipe drivers already know that.
195 /* Get DRM version. */
196 version
= drmGetVersion(ws
->fd
);
197 if (version
->version_major
!= 2 ||
198 version
->version_minor
< 3) {
199 fprintf(stderr
, "%s: DRM version is %d.%d.%d but this driver is "
200 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
202 version
->version_major
,
203 version
->version_minor
,
204 version
->version_patchlevel
);
205 drmFreeVersion(version
);
209 ws
->info
.drm_major
= version
->version_major
;
210 ws
->info
.drm_minor
= version
->version_minor
;
211 ws
->info
.drm_patchlevel
= version
->version_patchlevel
;
212 drmFreeVersion(version
);
215 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_DEVICE_ID
, "PCI ID",
220 switch (ws
->info
.pci_id
) {
221 #define CHIPSET(pci_id, name, family) case pci_id:
222 #include "pci_ids/r300_pci_ids.h"
227 #define CHIPSET(pci_id, name, family) case pci_id:
228 #include "pci_ids/r600_pci_ids.h"
233 #define CHIPSET(pci_id, name, family) case pci_id:
234 #include "pci_ids/radeonsi_pci_ids.h"
240 fprintf(stderr
, "radeon: Invalid PCI ID.\n");
245 retval
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_INFO
,
246 &gem_info
, sizeof(gem_info
));
248 fprintf(stderr
, "radeon: Failed to get MM info, error number %d\n",
252 ws
->info
.gart_size
= gem_info
.gart_size
;
253 ws
->info
.vram_size
= gem_info
.vram_size
;
255 ws
->num_cpus
= sysconf(_SC_NPROCESSORS_ONLN
);
257 /* Generation-specific queries. */
258 if (ws
->gen
== R300
) {
259 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_GB_PIPES
,
261 &ws
->info
.r300_num_gb_pipes
))
264 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_Z_PIPES
,
266 &ws
->info
.r300_num_z_pipes
))
269 else if (ws
->gen
>= R600
) {
270 if (ws
->info
.drm_minor
>= 9 &&
271 !radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BACKENDS
,
273 &ws
->info
.r600_num_backends
))
276 /* get the GPU counter frequency, failure is not fatal */
277 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CLOCK_CRYSTAL_FREQ
, NULL
,
278 &ws
->info
.r600_clock_crystal_freq
);
280 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TILING_CONFIG
, NULL
,
281 &ws
->info
.r600_tiling_config
);
283 if (ws
->info
.drm_minor
>= 11) {
284 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_TILE_PIPES
, NULL
,
285 &ws
->info
.r600_num_tile_pipes
);
287 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_BACKEND_MAP
, NULL
,
288 &ws
->info
.r600_backend_map
))
289 ws
->info
.r600_backend_map_valid
= TRUE
;
292 ws
->info
.r600_virtual_address
= FALSE
;
293 if (ws
->info
.drm_minor
>= 13) {
294 ws
->info
.r600_virtual_address
= TRUE
;
295 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_VA_START
, NULL
,
296 &ws
->info
.r600_va_start
))
297 ws
->info
.r600_virtual_address
= FALSE
;
298 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_IB_VM_MAX_SIZE
, NULL
,
299 &ws
->info
.r600_ib_vm_max_size
))
300 ws
->info
.r600_virtual_address
= FALSE
;
303 ws
->info
.r600_has_streamout
= ws
->info
.drm_minor
>= 13;
306 /* Get max pipes, this is only needed for compute shaders. All evergreen+
307 * chips have at least 2 pipes, so we use 2 as a default. */
308 ws
->info
.r600_max_pipes
= 2;
309 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_PIPES
, NULL
,
310 &ws
->info
.r600_max_pipes
);
315 static void radeon_winsys_destroy(struct radeon_winsys
*rws
)
317 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
319 pipe_mutex_destroy(ws
->hyperz_owner_mutex
);
320 pipe_mutex_destroy(ws
->cmask_owner_mutex
);
322 ws
->cman
->destroy(ws
->cman
);
323 ws
->kman
->destroy(ws
->kman
);
324 if (ws
->gen
== R600
) {
325 radeon_surface_manager_free(ws
->surf_man
);
330 static void radeon_query_info(struct radeon_winsys
*rws
,
331 struct radeon_info
*info
)
333 *info
= ((struct radeon_drm_winsys
*)rws
)->info
;
336 static boolean
radeon_cs_request_feature(struct radeon_winsys_cs
*rcs
,
337 enum radeon_feature_id fid
,
340 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
343 case RADEON_FID_R300_HYPERZ_ACCESS
:
344 if (debug_get_bool_option("RADEON_HYPERZ", FALSE
)) {
345 return radeon_set_fd_access(cs
, &cs
->ws
->hyperz_owner
,
346 &cs
->ws
->hyperz_owner_mutex
,
347 RADEON_INFO_WANT_HYPERZ
, enable
);
352 case RADEON_FID_R300_CMASK_ACCESS
:
353 if (debug_get_bool_option("RADEON_CMASK", FALSE
)) {
354 return radeon_set_fd_access(cs
, &cs
->ws
->cmask_owner
,
355 &cs
->ws
->cmask_owner_mutex
,
356 RADEON_INFO_WANT_CMASK
, enable
);
364 static int radeon_drm_winsys_surface_init(struct radeon_winsys
*rws
,
365 struct radeon_surface
*surf
)
367 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
369 return radeon_surface_init(ws
->surf_man
, surf
);
372 static int radeon_drm_winsys_surface_best(struct radeon_winsys
*rws
,
373 struct radeon_surface
*surf
)
375 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
377 return radeon_surface_best(ws
->surf_man
, surf
);
380 struct radeon_winsys
*radeon_drm_winsys_create(int fd
)
382 struct radeon_drm_winsys
*ws
= CALLOC_STRUCT(radeon_drm_winsys
);
389 if (!do_winsys_init(ws
))
392 /* Create managers. */
393 ws
->kman
= radeon_bomgr_create(ws
);
396 ws
->cman
= pb_cache_manager_create(ws
->kman
, 1000000);
400 /* FIXME check for libdrm version ?? */
401 if (ws
->gen
== R600
) {
402 ws
->surf_man
= radeon_surface_manager_new(fd
);
408 ws
->base
.destroy
= radeon_winsys_destroy
;
409 ws
->base
.query_info
= radeon_query_info
;
410 ws
->base
.cs_request_feature
= radeon_cs_request_feature
;
411 ws
->base
.surface_init
= radeon_drm_winsys_surface_init
;
412 ws
->base
.surface_best
= radeon_drm_winsys_surface_best
;
414 radeon_bomgr_init_functions(ws
);
415 radeon_drm_cs_init_functions(ws
);
417 pipe_mutex_init(ws
->hyperz_owner_mutex
);
418 pipe_mutex_init(ws
->cmask_owner_mutex
);
424 ws
->cman
->destroy(ws
->cman
);
426 ws
->kman
->destroy(ws
->kman
);
428 radeon_surface_manager_free(ws
->surf_man
);