2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Corbin Simpson <MostAwesomeDude@gmail.com>
30 * Joakim Sindholt <opensource@zhasha.com>
31 * Marek Olšák <maraeo@gmail.com>
34 #include "radeon_drm_bo.h"
35 #include "radeon_drm_cs.h"
36 #include "radeon_drm_public.h"
38 #include "pipebuffer/pb_bufmgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_hash_table.h"
44 #include <sys/types.h>
48 #ifndef RADEON_INFO_ACTIVE_CU_COUNT
49 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
52 static struct util_hash_table
*fd_tab
= NULL
;
53 pipe_static_mutex(fd_tab_mutex
);
55 /* Enable/disable feature access for one command stream.
56 * If enable == TRUE, return TRUE on success.
57 * Otherwise, return FALSE.
59 * We basically do the same thing kernel does, because we have to deal
60 * with multiple contexts (here command streams) backed by one winsys. */
61 static boolean
radeon_set_fd_access(struct radeon_drm_cs
*applier
,
62 struct radeon_drm_cs
**owner
,
64 unsigned request
, const char *request_name
,
67 struct drm_radeon_info info
;
68 unsigned value
= enable
? 1 : 0;
70 memset(&info
, 0, sizeof(info
));
72 pipe_mutex_lock(*mutex
);
74 /* Early exit if we are sure the request will fail. */
77 pipe_mutex_unlock(*mutex
);
81 if (*owner
!= applier
) {
82 pipe_mutex_unlock(*mutex
);
87 /* Pass through the request to the kernel. */
88 info
.value
= (unsigned long)&value
;
89 info
.request
= request
;
90 if (drmCommandWriteRead(applier
->ws
->fd
, DRM_RADEON_INFO
,
91 &info
, sizeof(info
)) != 0) {
92 pipe_mutex_unlock(*mutex
);
96 /* Update the rights in the winsys. */
100 pipe_mutex_unlock(*mutex
);
107 pipe_mutex_unlock(*mutex
);
111 static boolean
radeon_get_drm_value(int fd
, unsigned request
,
112 const char *errname
, uint32_t *out
)
114 struct drm_radeon_info info
;
117 memset(&info
, 0, sizeof(info
));
119 info
.value
= (unsigned long)out
;
120 info
.request
= request
;
122 retval
= drmCommandWriteRead(fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
125 fprintf(stderr
, "radeon: Failed to get %s, error number %d\n",
133 /* Helper function to do the ioctls needed for setup and init. */
134 static boolean
do_winsys_init(struct radeon_drm_winsys
*ws
)
136 struct drm_radeon_gem_info gem_info
;
138 drmVersionPtr version
;
140 memset(&gem_info
, 0, sizeof(gem_info
));
142 /* We do things in a specific order here.
144 * DRM version first. We need to be sure we're running on a KMS chipset.
145 * This is also for some features.
147 * Then, the PCI ID. This is essential and should return usable numbers
148 * for all Radeons. If this fails, we probably got handed an FD for some
151 * The GEM info is actually bogus on the kernel side, as well as our side
152 * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
153 * we don't actually use the info for anything yet.
155 * The GB and Z pipe requests should always succeed, but they might not
156 * return sensical values for all chipsets, but that's alright because
157 * the pipe drivers already know that.
160 /* Get DRM version. */
161 version
= drmGetVersion(ws
->fd
);
162 if (version
->version_major
!= 2 ||
163 version
->version_minor
< 3) {
164 fprintf(stderr
, "%s: DRM version is %d.%d.%d but this driver is "
165 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
167 version
->version_major
,
168 version
->version_minor
,
169 version
->version_patchlevel
);
170 drmFreeVersion(version
);
174 ws
->info
.drm_major
= version
->version_major
;
175 ws
->info
.drm_minor
= version
->version_minor
;
176 ws
->info
.drm_patchlevel
= version
->version_patchlevel
;
177 drmFreeVersion(version
);
180 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_DEVICE_ID
, "PCI ID",
185 switch (ws
->info
.pci_id
) {
186 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
187 #include "pci_ids/r300_pci_ids.h"
190 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
191 #include "pci_ids/r600_pci_ids.h"
194 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
195 #include "pci_ids/radeonsi_pci_ids.h"
199 fprintf(stderr
, "radeon: Invalid PCI ID.\n");
203 switch (ws
->info
.family
) {
206 fprintf(stderr
, "radeon: Unknown family.\n");
216 ws
->info
.chip_class
= R300
;
218 case CHIP_R420
: /* R4xx-based cores. */
227 ws
->info
.chip_class
= R400
;
229 case CHIP_RV515
: /* R5xx-based cores. */
235 ws
->info
.chip_class
= R500
;
245 ws
->info
.chip_class
= R600
;
251 ws
->info
.chip_class
= R700
;
264 ws
->info
.chip_class
= EVERGREEN
;
268 ws
->info
.chip_class
= CAYMAN
;
275 ws
->info
.chip_class
= SI
;
282 ws
->info
.chip_class
= CIK
;
287 ws
->info
.r600_has_dma
= FALSE
;
288 /* DMA is disabled on R700. There is IB corruption and hangs. */
289 if (ws
->info
.chip_class
>= EVERGREEN
&& ws
->info
.drm_minor
>= 27) {
290 ws
->info
.r600_has_dma
= TRUE
;
293 /* Check for UVD and VCE */
294 ws
->info
.has_uvd
= FALSE
;
295 ws
->info
.vce_fw_version
= 0x00000000;
296 if (ws
->info
.drm_minor
>= 32) {
297 uint32_t value
= RADEON_CS_RING_UVD
;
298 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_RING_WORKING
,
299 "UVD Ring working", &value
))
300 ws
->info
.has_uvd
= value
;
302 value
= RADEON_CS_RING_VCE
;
303 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_RING_WORKING
,
304 NULL
, &value
) && value
) {
306 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_VCE_FW_VERSION
,
307 "VCE FW version", &value
))
308 ws
->info
.vce_fw_version
= value
;
313 retval
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_INFO
,
314 &gem_info
, sizeof(gem_info
));
316 fprintf(stderr
, "radeon: Failed to get MM info, error number %d\n",
320 ws
->info
.gart_size
= gem_info
.gart_size
;
321 ws
->info
.vram_size
= gem_info
.vram_size
;
323 /* Get max clock frequency info and convert it to MHz */
324 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SCLK
, NULL
,
326 ws
->info
.max_sclk
/= 1000;
328 radeon_get_drm_value(ws
->fd
, RADEON_INFO_SI_BACKEND_ENABLED_MASK
, NULL
,
329 &ws
->info
.si_backend_enabled_mask
);
331 ws
->num_cpus
= sysconf(_SC_NPROCESSORS_ONLN
);
333 /* Generation-specific queries. */
334 if (ws
->gen
== DRV_R300
) {
335 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_GB_PIPES
,
337 &ws
->info
.r300_num_gb_pipes
))
340 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_Z_PIPES
,
342 &ws
->info
.r300_num_z_pipes
))
345 else if (ws
->gen
>= DRV_R600
) {
346 if (ws
->info
.drm_minor
>= 9 &&
347 !radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BACKENDS
,
349 &ws
->info
.r600_num_backends
))
352 /* get the GPU counter frequency, failure is not fatal */
353 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CLOCK_CRYSTAL_FREQ
, NULL
,
354 &ws
->info
.r600_clock_crystal_freq
);
356 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TILING_CONFIG
, NULL
,
357 &ws
->info
.r600_tiling_config
);
359 if (ws
->info
.drm_minor
>= 11) {
360 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_TILE_PIPES
, NULL
,
361 &ws
->info
.r600_num_tile_pipes
);
363 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_BACKEND_MAP
, NULL
,
364 &ws
->info
.r600_backend_map
))
365 ws
->info
.r600_backend_map_valid
= TRUE
;
368 ws
->info
.r600_virtual_address
= FALSE
;
369 if (ws
->info
.drm_minor
>= 13) {
370 uint32_t ib_vm_max_size
;
372 ws
->info
.r600_virtual_address
= TRUE
;
373 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_VA_START
, NULL
,
375 ws
->info
.r600_virtual_address
= FALSE
;
376 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_IB_VM_MAX_SIZE
, NULL
,
378 ws
->info
.r600_virtual_address
= FALSE
;
380 if (ws
->gen
== DRV_R600
&& !debug_get_bool_option("RADEON_VA", FALSE
))
381 ws
->info
.r600_virtual_address
= FALSE
;
384 /* Get max pipes, this is only needed for compute shaders. All evergreen+
385 * chips have at least 2 pipes, so we use 2 as a default. */
386 ws
->info
.r600_max_pipes
= 2;
387 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_PIPES
, NULL
,
388 &ws
->info
.r600_max_pipes
);
390 /* All GPUs have at least one compute unit */
391 ws
->info
.max_compute_units
= 1;
392 radeon_get_drm_value(ws
->fd
, RADEON_INFO_ACTIVE_CU_COUNT
, NULL
,
393 &ws
->info
.max_compute_units
);
395 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SE
, NULL
,
398 if (!ws
->info
.max_se
) {
399 switch (ws
->info
.family
) {
418 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SH_PER_SE
, NULL
,
419 &ws
->info
.max_sh_per_se
);
421 radeon_get_drm_value(ws
->fd
, RADEON_INFO_ACCEL_WORKING2
, NULL
,
422 &ws
->accel_working2
);
423 if (ws
->info
.family
== CHIP_HAWAII
&& ws
->accel_working2
< 2) {
424 fprintf(stderr
, "radeon: GPU acceleration for Hawaii disabled, "
425 "returned accel_working2 value %u is smaller than 2. "
426 "Please install a newer kernel.\n",
431 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_SI_TILE_MODE_ARRAY
, NULL
,
432 ws
->info
.si_tile_mode_array
)) {
433 ws
->info
.si_tile_mode_array_valid
= TRUE
;
436 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY
, NULL
,
437 ws
->info
.cik_macrotile_mode_array
)) {
438 ws
->info
.cik_macrotile_mode_array_valid
= TRUE
;
444 static void radeon_winsys_destroy(struct radeon_winsys
*rws
)
446 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
450 pipe_semaphore_signal(&ws
->cs_queued
);
451 pipe_thread_wait(ws
->thread
);
453 pipe_semaphore_destroy(&ws
->cs_queued
);
455 pipe_mutex_destroy(ws
->hyperz_owner_mutex
);
456 pipe_mutex_destroy(ws
->cmask_owner_mutex
);
457 pipe_mutex_destroy(ws
->cs_stack_lock
);
459 ws
->cman
->destroy(ws
->cman
);
460 ws
->kman
->destroy(ws
->kman
);
461 if (ws
->gen
>= DRV_R600
) {
462 radeon_surface_manager_free(ws
->surf_man
);
467 static void radeon_query_info(struct radeon_winsys
*rws
,
468 struct radeon_info
*info
)
470 *info
= ((struct radeon_drm_winsys
*)rws
)->info
;
473 static boolean
radeon_cs_request_feature(struct radeon_winsys_cs
*rcs
,
474 enum radeon_feature_id fid
,
477 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
480 case RADEON_FID_R300_HYPERZ_ACCESS
:
481 return radeon_set_fd_access(cs
, &cs
->ws
->hyperz_owner
,
482 &cs
->ws
->hyperz_owner_mutex
,
483 RADEON_INFO_WANT_HYPERZ
, "Hyper-Z",
486 case RADEON_FID_R300_CMASK_ACCESS
:
487 return radeon_set_fd_access(cs
, &cs
->ws
->cmask_owner
,
488 &cs
->ws
->cmask_owner_mutex
,
489 RADEON_INFO_WANT_CMASK
, "AA optimizations",
495 static int radeon_drm_winsys_surface_init(struct radeon_winsys
*rws
,
496 struct radeon_surface
*surf
)
498 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
500 return radeon_surface_init(ws
->surf_man
, surf
);
503 static int radeon_drm_winsys_surface_best(struct radeon_winsys
*rws
,
504 struct radeon_surface
*surf
)
506 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
508 return radeon_surface_best(ws
->surf_man
, surf
);
511 static uint64_t radeon_query_value(struct radeon_winsys
*rws
,
512 enum radeon_value_id value
)
514 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
518 case RADEON_REQUESTED_VRAM_MEMORY
:
519 return ws
->allocated_vram
;
520 case RADEON_REQUESTED_GTT_MEMORY
:
521 return ws
->allocated_gtt
;
522 case RADEON_BUFFER_WAIT_TIME_NS
:
523 return ws
->buffer_wait_time
;
524 case RADEON_TIMESTAMP
:
525 if (ws
->info
.drm_minor
< 20 || ws
->gen
< DRV_R600
) {
530 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TIMESTAMP
, "timestamp",
533 case RADEON_NUM_CS_FLUSHES
:
534 return ws
->num_cs_flushes
;
535 case RADEON_NUM_BYTES_MOVED
:
536 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BYTES_MOVED
,
537 "num-bytes-moved", (uint32_t*)&retval
);
539 case RADEON_VRAM_USAGE
:
540 radeon_get_drm_value(ws
->fd
, RADEON_INFO_VRAM_USAGE
,
541 "vram-usage", (uint32_t*)&retval
);
543 case RADEON_GTT_USAGE
:
544 radeon_get_drm_value(ws
->fd
, RADEON_INFO_GTT_USAGE
,
545 "gtt-usage", (uint32_t*)&retval
);
551 static unsigned hash_fd(void *key
)
553 int fd
= pointer_to_intptr(key
);
557 return stat
.st_dev
^ stat
.st_ino
^ stat
.st_rdev
;
560 static int compare_fd(void *key1
, void *key2
)
562 int fd1
= pointer_to_intptr(key1
);
563 int fd2
= pointer_to_intptr(key2
);
564 struct stat stat1
, stat2
;
568 return stat1
.st_dev
!= stat2
.st_dev
||
569 stat1
.st_ino
!= stat2
.st_ino
||
570 stat1
.st_rdev
!= stat2
.st_rdev
;
573 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys
*ws
, struct radeon_drm_cs
*cs
)
576 pipe_mutex_lock(ws
->cs_stack_lock
);
577 if (ws
->ncs
>= RING_LAST
) {
578 /* no room left for a flush */
579 pipe_mutex_unlock(ws
->cs_stack_lock
);
582 ws
->cs_stack
[ws
->ncs
++] = cs
;
583 pipe_mutex_unlock(ws
->cs_stack_lock
);
584 pipe_semaphore_signal(&ws
->cs_queued
);
587 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl
, param
)
589 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)param
;
590 struct radeon_drm_cs
*cs
;
594 pipe_semaphore_wait(&ws
->cs_queued
);
598 pipe_mutex_lock(ws
->cs_stack_lock
);
599 cs
= ws
->cs_stack
[0];
600 for (i
= 1; i
< ws
->ncs
; i
++)
601 ws
->cs_stack
[i
- 1] = ws
->cs_stack
[i
];
602 ws
->cs_stack
[--ws
->ncs
] = NULL
;
603 pipe_mutex_unlock(ws
->cs_stack_lock
);
606 radeon_drm_cs_emit_ioctl_oneshot(cs
, cs
->cst
);
607 pipe_semaphore_signal(&cs
->flush_completed
);
610 pipe_mutex_lock(ws
->cs_stack_lock
);
611 for (i
= 0; i
< ws
->ncs
; i
++) {
612 pipe_semaphore_signal(&ws
->cs_stack
[i
]->flush_completed
);
613 ws
->cs_stack
[i
] = NULL
;
616 pipe_mutex_unlock(ws
->cs_stack_lock
);
620 DEBUG_GET_ONCE_BOOL_OPTION(thread
, "RADEON_THREAD", TRUE
)
621 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl
, param
);
623 static bool radeon_winsys_unref(struct radeon_winsys
*ws
)
625 struct radeon_drm_winsys
*rws
= (struct radeon_drm_winsys
*)ws
;
628 /* When the reference counter drops to zero, remove the fd from the table.
629 * This must happen while the mutex is locked, so that
630 * radeon_drm_winsys_create in another thread doesn't get the winsys
631 * from the table when the counter drops to 0. */
632 pipe_mutex_lock(fd_tab_mutex
);
634 destroy
= pipe_reference(&rws
->reference
, NULL
);
635 if (destroy
&& fd_tab
)
636 util_hash_table_remove(fd_tab
, intptr_to_pointer(rws
->fd
));
638 pipe_mutex_unlock(fd_tab_mutex
);
642 PUBLIC
struct radeon_winsys
*
643 radeon_drm_winsys_create(int fd
, radeon_screen_create_t screen_create
)
645 struct radeon_drm_winsys
*ws
;
647 pipe_mutex_lock(fd_tab_mutex
);
649 fd_tab
= util_hash_table_create(hash_fd
, compare_fd
);
652 ws
= util_hash_table_get(fd_tab
, intptr_to_pointer(fd
));
654 pipe_reference(NULL
, &ws
->reference
);
655 pipe_mutex_unlock(fd_tab_mutex
);
659 ws
= CALLOC_STRUCT(radeon_drm_winsys
);
661 pipe_mutex_unlock(fd_tab_mutex
);
667 if (!do_winsys_init(ws
))
670 /* Create managers. */
671 ws
->kman
= radeon_bomgr_create(ws
);
675 ws
->cman
= pb_cache_manager_create(ws
->kman
, 1000000, 2.0f
, 0,
676 (ws
->info
.vram_size
+ ws
->info
.gart_size
) / 8);
680 if (ws
->gen
>= DRV_R600
) {
681 ws
->surf_man
= radeon_surface_manager_new(fd
);
687 pipe_reference_init(&ws
->reference
, 1);
690 ws
->base
.unref
= radeon_winsys_unref
;
691 ws
->base
.destroy
= radeon_winsys_destroy
;
692 ws
->base
.query_info
= radeon_query_info
;
693 ws
->base
.cs_request_feature
= radeon_cs_request_feature
;
694 ws
->base
.surface_init
= radeon_drm_winsys_surface_init
;
695 ws
->base
.surface_best
= radeon_drm_winsys_surface_best
;
696 ws
->base
.query_value
= radeon_query_value
;
698 radeon_bomgr_init_functions(ws
);
699 radeon_drm_cs_init_functions(ws
);
701 pipe_mutex_init(ws
->hyperz_owner_mutex
);
702 pipe_mutex_init(ws
->cmask_owner_mutex
);
703 pipe_mutex_init(ws
->cs_stack_lock
);
706 pipe_semaphore_init(&ws
->cs_queued
, 0);
707 if (ws
->num_cpus
> 1 && debug_get_option_thread())
708 ws
->thread
= pipe_thread_create(radeon_drm_cs_emit_ioctl
, ws
);
710 /* Create the screen at the end. The winsys must be initialized
713 * Alternatively, we could create the screen based on "ws->gen"
714 * and link all drivers into one binary blob. */
715 ws
->base
.screen
= screen_create(&ws
->base
);
716 if (!ws
->base
.screen
) {
717 radeon_winsys_destroy(&ws
->base
);
718 pipe_mutex_unlock(fd_tab_mutex
);
722 util_hash_table_set(fd_tab
, intptr_to_pointer(fd
), ws
);
724 /* We must unlock the mutex once the winsys is fully initialized, so that
725 * other threads attempting to create the winsys from the same fd will
726 * get a fully initialized winsys and not just half-way initialized. */
727 pipe_mutex_unlock(fd_tab_mutex
);
732 pipe_mutex_unlock(fd_tab_mutex
);
734 ws
->cman
->destroy(ws
->cman
);
736 ws
->kman
->destroy(ws
->kman
);
738 radeon_surface_manager_free(ws
->surf_man
);