2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Corbin Simpson <MostAwesomeDude@gmail.com>
30 * Joakim Sindholt <opensource@zhasha.com>
31 * Marek Olšák <maraeo@gmail.com>
34 #include "radeon_drm_bo.h"
35 #include "radeon_drm_cs.h"
36 #include "radeon_drm_public.h"
38 #include "pipebuffer/pb_bufmgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_hash_table.h"
44 #include <sys/types.h>
48 static struct util_hash_table
*fd_tab
= NULL
;
50 /* Enable/disable feature access for one command stream.
51 * If enable == TRUE, return TRUE on success.
52 * Otherwise, return FALSE.
54 * We basically do the same thing kernel does, because we have to deal
55 * with multiple contexts (here command streams) backed by one winsys. */
56 static boolean
radeon_set_fd_access(struct radeon_drm_cs
*applier
,
57 struct radeon_drm_cs
**owner
,
59 unsigned request
, const char *request_name
,
62 struct drm_radeon_info info
;
63 unsigned value
= enable
? 1 : 0;
65 memset(&info
, 0, sizeof(info
));
67 pipe_mutex_lock(*mutex
);
69 /* Early exit if we are sure the request will fail. */
72 pipe_mutex_unlock(*mutex
);
76 if (*owner
!= applier
) {
77 pipe_mutex_unlock(*mutex
);
82 /* Pass through the request to the kernel. */
83 info
.value
= (unsigned long)&value
;
84 info
.request
= request
;
85 if (drmCommandWriteRead(applier
->ws
->fd
, DRM_RADEON_INFO
,
86 &info
, sizeof(info
)) != 0) {
87 pipe_mutex_unlock(*mutex
);
91 /* Update the rights in the winsys. */
95 printf("radeon: Acquired access to %s.\n", request_name
);
96 pipe_mutex_unlock(*mutex
);
101 printf("radeon: Released access to %s.\n", request_name
);
104 pipe_mutex_unlock(*mutex
);
108 static boolean
radeon_get_drm_value(int fd
, unsigned request
,
109 const char *errname
, uint32_t *out
)
111 struct drm_radeon_info info
;
114 memset(&info
, 0, sizeof(info
));
116 info
.value
= (unsigned long)out
;
117 info
.request
= request
;
119 retval
= drmCommandWriteRead(fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
122 fprintf(stderr
, "radeon: Failed to get %s, error number %d\n",
130 /* Helper function to do the ioctls needed for setup and init. */
131 static boolean
do_winsys_init(struct radeon_drm_winsys
*ws
)
133 struct drm_radeon_gem_info gem_info
;
135 drmVersionPtr version
;
137 memset(&gem_info
, 0, sizeof(gem_info
));
139 /* We do things in a specific order here.
141 * DRM version first. We need to be sure we're running on a KMS chipset.
142 * This is also for some features.
144 * Then, the PCI ID. This is essential and should return usable numbers
145 * for all Radeons. If this fails, we probably got handed an FD for some
148 * The GEM info is actually bogus on the kernel side, as well as our side
149 * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
150 * we don't actually use the info for anything yet.
152 * The GB and Z pipe requests should always succeed, but they might not
153 * return sensical values for all chipsets, but that's alright because
154 * the pipe drivers already know that.
157 /* Get DRM version. */
158 version
= drmGetVersion(ws
->fd
);
159 if (version
->version_major
!= 2 ||
160 version
->version_minor
< 3) {
161 fprintf(stderr
, "%s: DRM version is %d.%d.%d but this driver is "
162 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
164 version
->version_major
,
165 version
->version_minor
,
166 version
->version_patchlevel
);
167 drmFreeVersion(version
);
171 ws
->info
.drm_major
= version
->version_major
;
172 ws
->info
.drm_minor
= version
->version_minor
;
173 ws
->info
.drm_patchlevel
= version
->version_patchlevel
;
174 drmFreeVersion(version
);
177 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_DEVICE_ID
, "PCI ID",
182 switch (ws
->info
.pci_id
) {
183 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
184 #include "pci_ids/r300_pci_ids.h"
187 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
188 #include "pci_ids/r600_pci_ids.h"
191 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
192 #include "pci_ids/radeonsi_pci_ids.h"
196 fprintf(stderr
, "radeon: Invalid PCI ID.\n");
200 switch (ws
->info
.family
) {
203 fprintf(stderr
, "radeon: Unknown family.\n");
213 ws
->info
.chip_class
= R300
;
215 case CHIP_R420
: /* R4xx-based cores. */
224 ws
->info
.chip_class
= R400
;
226 case CHIP_RV515
: /* R5xx-based cores. */
232 ws
->info
.chip_class
= R500
;
242 ws
->info
.chip_class
= R600
;
248 ws
->info
.chip_class
= R700
;
261 ws
->info
.chip_class
= EVERGREEN
;
265 ws
->info
.chip_class
= CAYMAN
;
272 ws
->info
.chip_class
= SI
;
278 ws
->info
.chip_class
= CIK
;
283 ws
->info
.r600_has_dma
= FALSE
;
284 if (ws
->info
.chip_class
>= R700
&& ws
->info
.drm_minor
>= 27) {
285 ws
->info
.r600_has_dma
= TRUE
;
288 /* Check for UVD and VCE */
289 ws
->info
.has_uvd
= FALSE
;
290 ws
->info
.vce_fw_version
= 0x00000000;
291 if (ws
->info
.drm_minor
>= 32) {
292 uint32_t value
= RADEON_CS_RING_UVD
;
293 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_RING_WORKING
,
294 "UVD Ring working", &value
))
295 ws
->info
.has_uvd
= value
;
297 value
= RADEON_CS_RING_VCE
;
298 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_RING_WORKING
,
299 NULL
, &value
) && value
) {
301 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_VCE_FW_VERSION
,
302 "VCE FW version", &value
))
303 ws
->info
.vce_fw_version
= value
;
308 retval
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_INFO
,
309 &gem_info
, sizeof(gem_info
));
311 fprintf(stderr
, "radeon: Failed to get MM info, error number %d\n",
315 ws
->info
.gart_size
= gem_info
.gart_size
;
316 ws
->info
.vram_size
= gem_info
.vram_size
;
318 ws
->num_cpus
= sysconf(_SC_NPROCESSORS_ONLN
);
320 /* Generation-specific queries. */
321 if (ws
->gen
== DRV_R300
) {
322 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_GB_PIPES
,
324 &ws
->info
.r300_num_gb_pipes
))
327 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_Z_PIPES
,
329 &ws
->info
.r300_num_z_pipes
))
332 else if (ws
->gen
>= DRV_R600
) {
333 if (ws
->info
.drm_minor
>= 9 &&
334 !radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BACKENDS
,
336 &ws
->info
.r600_num_backends
))
339 /* get the GPU counter frequency, failure is not fatal */
340 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CLOCK_CRYSTAL_FREQ
, NULL
,
341 &ws
->info
.r600_clock_crystal_freq
);
343 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TILING_CONFIG
, NULL
,
344 &ws
->info
.r600_tiling_config
);
346 if (ws
->info
.drm_minor
>= 11) {
347 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_TILE_PIPES
, NULL
,
348 &ws
->info
.r600_num_tile_pipes
);
350 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_BACKEND_MAP
, NULL
,
351 &ws
->info
.r600_backend_map
))
352 ws
->info
.r600_backend_map_valid
= TRUE
;
355 ws
->info
.r600_virtual_address
= FALSE
;
356 if (ws
->info
.drm_minor
>= 13) {
357 ws
->info
.r600_virtual_address
= TRUE
;
358 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_VA_START
, NULL
,
359 &ws
->info
.r600_va_start
))
360 ws
->info
.r600_virtual_address
= FALSE
;
361 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_IB_VM_MAX_SIZE
, NULL
,
362 &ws
->info
.r600_ib_vm_max_size
))
363 ws
->info
.r600_virtual_address
= FALSE
;
365 if (ws
->gen
== DRV_R600
&& !debug_get_bool_option("RADEON_VA", FALSE
))
366 ws
->info
.r600_virtual_address
= FALSE
;
369 /* Get max pipes, this is only needed for compute shaders. All evergreen+
370 * chips have at least 2 pipes, so we use 2 as a default. */
371 ws
->info
.r600_max_pipes
= 2;
372 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_PIPES
, NULL
,
373 &ws
->info
.r600_max_pipes
);
375 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_SI_TILE_MODE_ARRAY
, NULL
,
376 ws
->info
.si_tile_mode_array
)) {
377 ws
->info
.si_tile_mode_array_valid
= TRUE
;
380 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY
, NULL
,
381 ws
->info
.cik_macrotile_mode_array
)) {
382 ws
->info
.cik_macrotile_mode_array_valid
= TRUE
;
388 static void radeon_winsys_destroy(struct radeon_winsys
*rws
)
390 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
394 pipe_semaphore_signal(&ws
->cs_queued
);
395 pipe_thread_wait(ws
->thread
);
397 pipe_semaphore_destroy(&ws
->cs_queued
);
399 pipe_mutex_destroy(ws
->hyperz_owner_mutex
);
400 pipe_mutex_destroy(ws
->cmask_owner_mutex
);
401 pipe_mutex_destroy(ws
->cs_stack_lock
);
403 ws
->cman
->destroy(ws
->cman
);
404 ws
->kman
->destroy(ws
->kman
);
405 if (ws
->gen
>= DRV_R600
) {
406 radeon_surface_manager_free(ws
->surf_man
);
409 util_hash_table_remove(fd_tab
, intptr_to_pointer(ws
->fd
));
414 static void radeon_query_info(struct radeon_winsys
*rws
,
415 struct radeon_info
*info
)
417 *info
= ((struct radeon_drm_winsys
*)rws
)->info
;
420 static boolean
radeon_cs_request_feature(struct radeon_winsys_cs
*rcs
,
421 enum radeon_feature_id fid
,
424 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
427 case RADEON_FID_R300_HYPERZ_ACCESS
:
428 return radeon_set_fd_access(cs
, &cs
->ws
->hyperz_owner
,
429 &cs
->ws
->hyperz_owner_mutex
,
430 RADEON_INFO_WANT_HYPERZ
, "Hyper-Z",
433 case RADEON_FID_R300_CMASK_ACCESS
:
434 return radeon_set_fd_access(cs
, &cs
->ws
->cmask_owner
,
435 &cs
->ws
->cmask_owner_mutex
,
436 RADEON_INFO_WANT_CMASK
, "AA optimizations",
442 static int radeon_drm_winsys_surface_init(struct radeon_winsys
*rws
,
443 struct radeon_surface
*surf
)
445 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
447 return radeon_surface_init(ws
->surf_man
, surf
);
450 static int radeon_drm_winsys_surface_best(struct radeon_winsys
*rws
,
451 struct radeon_surface
*surf
)
453 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
455 return radeon_surface_best(ws
->surf_man
, surf
);
458 static uint64_t radeon_query_value(struct radeon_winsys
*rws
,
459 enum radeon_value_id value
)
461 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
465 case RADEON_REQUESTED_VRAM_MEMORY
:
466 return ws
->allocated_vram
;
467 case RADEON_REQUESTED_GTT_MEMORY
:
468 return ws
->allocated_gtt
;
469 case RADEON_BUFFER_WAIT_TIME_NS
:
470 return ws
->buffer_wait_time
;
471 case RADEON_TIMESTAMP
:
472 if (ws
->info
.drm_minor
< 20 || ws
->gen
< DRV_R600
) {
477 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TIMESTAMP
, "timestamp",
480 case RADEON_NUM_CS_FLUSHES
:
481 return ws
->num_cs_flushes
;
482 case RADEON_NUM_BYTES_MOVED
:
483 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BYTES_MOVED
,
484 "num-bytes-moved", (uint32_t*)&retval
);
486 case RADEON_VRAM_USAGE
:
487 radeon_get_drm_value(ws
->fd
, RADEON_INFO_VRAM_USAGE
,
488 "vram-usage", (uint32_t*)&retval
);
490 case RADEON_GTT_USAGE
:
491 radeon_get_drm_value(ws
->fd
, RADEON_INFO_GTT_USAGE
,
492 "gtt-usage", (uint32_t*)&retval
);
498 static unsigned hash_fd(void *key
)
500 int fd
= pointer_to_intptr(key
);
504 return stat
.st_dev
^ stat
.st_ino
^ stat
.st_rdev
;
507 static int compare_fd(void *key1
, void *key2
)
509 int fd1
= pointer_to_intptr(key1
);
510 int fd2
= pointer_to_intptr(key2
);
511 struct stat stat1
, stat2
;
515 return stat1
.st_dev
!= stat2
.st_dev
||
516 stat1
.st_ino
!= stat2
.st_ino
||
517 stat1
.st_rdev
!= stat2
.st_rdev
;
520 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys
*ws
, struct radeon_drm_cs
*cs
)
523 pipe_mutex_lock(ws
->cs_stack_lock
);
524 if (ws
->ncs
>= RING_LAST
) {
525 /* no room left for a flush */
526 pipe_mutex_unlock(ws
->cs_stack_lock
);
529 ws
->cs_stack
[ws
->ncs
++] = cs
;
530 pipe_mutex_unlock(ws
->cs_stack_lock
);
531 pipe_semaphore_signal(&ws
->cs_queued
);
534 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl
, param
)
536 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)param
;
537 struct radeon_drm_cs
*cs
;
541 pipe_semaphore_wait(&ws
->cs_queued
);
545 pipe_mutex_lock(ws
->cs_stack_lock
);
546 cs
= ws
->cs_stack
[0];
547 for (i
= 1; i
< ws
->ncs
; i
++)
548 ws
->cs_stack
[i
- 1] = ws
->cs_stack
[i
];
549 ws
->cs_stack
[--ws
->ncs
] = NULL
;
550 pipe_mutex_unlock(ws
->cs_stack_lock
);
553 radeon_drm_cs_emit_ioctl_oneshot(cs
, cs
->cst
);
554 pipe_semaphore_signal(&cs
->flush_completed
);
557 pipe_mutex_lock(ws
->cs_stack_lock
);
558 for (i
= 0; i
< ws
->ncs
; i
++) {
559 pipe_semaphore_signal(&ws
->cs_stack
[i
]->flush_completed
);
560 ws
->cs_stack
[i
] = NULL
;
563 pipe_mutex_unlock(ws
->cs_stack_lock
);
567 DEBUG_GET_ONCE_BOOL_OPTION(thread
, "RADEON_THREAD", TRUE
)
568 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl
, param
);
570 PUBLIC
struct radeon_winsys
*radeon_drm_winsys_create(int fd
)
572 struct radeon_drm_winsys
*ws
;
575 fd_tab
= util_hash_table_create(hash_fd
, compare_fd
);
578 ws
= util_hash_table_get(fd_tab
, intptr_to_pointer(fd
));
580 pipe_reference(NULL
, &ws
->base
.reference
);
584 ws
= CALLOC_STRUCT(radeon_drm_winsys
);
589 util_hash_table_set(fd_tab
, intptr_to_pointer(fd
), ws
);
591 if (!do_winsys_init(ws
))
594 /* Create managers. */
595 ws
->kman
= radeon_bomgr_create(ws
);
598 ws
->cman
= pb_cache_manager_create(ws
->kman
, 1000000, 2.0f
, 0);
602 if (ws
->gen
>= DRV_R600
) {
603 ws
->surf_man
= radeon_surface_manager_new(fd
);
609 pipe_reference_init(&ws
->base
.reference
, 1);
612 ws
->base
.destroy
= radeon_winsys_destroy
;
613 ws
->base
.query_info
= radeon_query_info
;
614 ws
->base
.cs_request_feature
= radeon_cs_request_feature
;
615 ws
->base
.surface_init
= radeon_drm_winsys_surface_init
;
616 ws
->base
.surface_best
= radeon_drm_winsys_surface_best
;
617 ws
->base
.query_value
= radeon_query_value
;
619 radeon_bomgr_init_functions(ws
);
620 radeon_drm_cs_init_functions(ws
);
622 pipe_mutex_init(ws
->hyperz_owner_mutex
);
623 pipe_mutex_init(ws
->cmask_owner_mutex
);
624 pipe_mutex_init(ws
->cs_stack_lock
);
627 pipe_semaphore_init(&ws
->cs_queued
, 0);
628 if (ws
->num_cpus
> 1 && debug_get_option_thread())
629 ws
->thread
= pipe_thread_create(radeon_drm_cs_emit_ioctl
, ws
);
635 ws
->cman
->destroy(ws
->cman
);
637 ws
->kman
->destroy(ws
->kman
);
639 radeon_surface_manager_free(ws
->surf_man
);