src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "pipebuffer/pb_bufmgr.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_hash_table.h"
  41
  42 #include <xf86drm.h>
  43 #include <stdio.h>
  44 #include <sys/types.h>
  45 #include <sys/stat.h>
  46 #include <unistd.h>
  47
  48 #ifndef RADEON_INFO_ACTIVE_CU_COUNT
  49 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
  50 #endif
  51
  52 static struct util_hash_table *fd_tab = NULL;
  53 pipe_static_mutex(fd_tab_mutex);
  54
  55 /* Enable/disable feature access for one command stream.
  56  * If enable == TRUE, return TRUE on success.
  57  * Otherwise, return FALSE.
  58  *
  59  * We basically do the same thing kernel does, because we have to deal
  60  * with multiple contexts (here command streams) backed by one winsys. */
  61 static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
  62                                     struct radeon_drm_cs **owner,
  63                                     pipe_mutex *mutex,
  64                                     unsigned request, const char *request_name,
  65                                     boolean enable)
  66 {
  67     struct drm_radeon_info info;
  68     unsigned value = enable ? 1 : 0;
  69
  70     memset(&info, 0, sizeof(info));
  71
  72     pipe_mutex_lock(*mutex);
  73
  74     /* Early exit if we are sure the request will fail. */
  75     if (enable) {
  76         if (*owner) {
  77             pipe_mutex_unlock(*mutex);
  78             return FALSE;
  79         }
  80     } else {
  81         if (*owner != applier) {
  82             pipe_mutex_unlock(*mutex);
  83             return FALSE;
  84         }
  85     }
  86
  87     /* Pass through the request to the kernel. */
  88     info.value = (unsigned long)&value;
  89     info.request = request;
  90     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
  91                             &info, sizeof(info)) != 0) {
  92         pipe_mutex_unlock(*mutex);
  93         return FALSE;
  94     }
  95
  96     /* Update the rights in the winsys. */
  97     if (enable) {
  98         if (value) {
  99             *owner = applier;
 100             printf("radeon: Acquired access to %s.\n", request_name);
 101             pipe_mutex_unlock(*mutex);
 102             return TRUE;
 103         }
 104     } else {
 105         *owner = NULL;
 106         printf("radeon: Released access to %s.\n", request_name);
 107     }
 108
 109     pipe_mutex_unlock(*mutex);
 110     return FALSE;
 111 }
 112
 113 static boolean radeon_get_drm_value(int fd, unsigned request,
 114                                     const char *errname, uint32_t *out)
 115 {
 116     struct drm_radeon_info info;
 117     int retval;
 118
 119     memset(&info, 0, sizeof(info));
 120
 121     info.value = (unsigned long)out;
 122     info.request = request;
 123
 124     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 125     if (retval) {
 126         if (errname) {
 127             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 128                     errname, retval);
 129         }
 130         return FALSE;
 131     }
 132     return TRUE;
 133 }
 134
 135 /* Helper function to do the ioctls needed for setup and init. */
 136 static boolean do_winsys_init(struct radeon_drm_winsys *ws)
 137 {
 138     struct drm_radeon_gem_info gem_info;
 139     int retval;
 140     drmVersionPtr version;
 141
 142     memset(&gem_info, 0, sizeof(gem_info));
 143
 144     /* We do things in a specific order here.
 145      *
 146      * DRM version first. We need to be sure we're running on a KMS chipset.
 147      * This is also for some features.
 148      *
 149      * Then, the PCI ID. This is essential and should return usable numbers
 150      * for all Radeons. If this fails, we probably got handed an FD for some
 151      * non-Radeon card.
 152      *
 153      * The GEM info is actually bogus on the kernel side, as well as our side
 154      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 155      * we don't actually use the info for anything yet.
 156      *
 157      * The GB and Z pipe requests should always succeed, but they might not
 158      * return sensical values for all chipsets, but that's alright because
 159      * the pipe drivers already know that.
 160      */
 161
 162     /* Get DRM version. */
 163     version = drmGetVersion(ws->fd);
 164     if (version->version_major != 2 ||
 165         version->version_minor < 3) {
 166         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 167                 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
 168                 __FUNCTION__,
 169                 version->version_major,
 170                 version->version_minor,
 171                 version->version_patchlevel);
 172         drmFreeVersion(version);
 173         return FALSE;
 174     }
 175
 176     ws->info.drm_major = version->version_major;
 177     ws->info.drm_minor = version->version_minor;
 178     ws->info.drm_patchlevel = version->version_patchlevel;
 179     drmFreeVersion(version);
 180
 181     /* Get PCI ID. */
 182     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 183                               &ws->info.pci_id))
 184         return FALSE;
 185
 186     /* Check PCI ID. */
 187     switch (ws->info.pci_id) {
 188 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 189 #include "pci_ids/r300_pci_ids.h"
 190 #undef CHIPSET
 191
 192 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 193 #include "pci_ids/r600_pci_ids.h"
 194 #undef CHIPSET
 195
 196 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 197 #include "pci_ids/radeonsi_pci_ids.h"
 198 #undef CHIPSET
 199
 200     default:
 201         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 202         return FALSE;
 203     }
 204
 205     switch (ws->info.family) {
 206     default:
 207     case CHIP_UNKNOWN:
 208         fprintf(stderr, "radeon: Unknown family.\n");
 209         return FALSE;
 210     case CHIP_R300:
 211     case CHIP_R350:
 212     case CHIP_RV350:
 213     case CHIP_RV370:
 214     case CHIP_RV380:
 215     case CHIP_RS400:
 216     case CHIP_RC410:
 217     case CHIP_RS480:
 218         ws->info.chip_class = R300;
 219         break;
 220     case CHIP_R420:     /* R4xx-based cores. */
 221     case CHIP_R423:
 222     case CHIP_R430:
 223     case CHIP_R480:
 224     case CHIP_R481:
 225     case CHIP_RV410:
 226     case CHIP_RS600:
 227     case CHIP_RS690:
 228     case CHIP_RS740:
 229         ws->info.chip_class = R400;
 230         break;
 231     case CHIP_RV515:    /* R5xx-based cores. */
 232     case CHIP_R520:
 233     case CHIP_RV530:
 234     case CHIP_R580:
 235     case CHIP_RV560:
 236     case CHIP_RV570:
 237         ws->info.chip_class = R500;
 238         break;
 239     case CHIP_R600:
 240     case CHIP_RV610:
 241     case CHIP_RV630:
 242     case CHIP_RV670:
 243     case CHIP_RV620:
 244     case CHIP_RV635:
 245     case CHIP_RS780:
 246     case CHIP_RS880:
 247         ws->info.chip_class = R600;
 248         break;
 249     case CHIP_RV770:
 250     case CHIP_RV730:
 251     case CHIP_RV710:
 252     case CHIP_RV740:
 253         ws->info.chip_class = R700;
 254         break;
 255     case CHIP_CEDAR:
 256     case CHIP_REDWOOD:
 257     case CHIP_JUNIPER:
 258     case CHIP_CYPRESS:
 259     case CHIP_HEMLOCK:
 260     case CHIP_PALM:
 261     case CHIP_SUMO:
 262     case CHIP_SUMO2:
 263     case CHIP_BARTS:
 264     case CHIP_TURKS:
 265     case CHIP_CAICOS:
 266         ws->info.chip_class = EVERGREEN;
 267         break;
 268     case CHIP_CAYMAN:
 269     case CHIP_ARUBA:
 270         ws->info.chip_class = CAYMAN;
 271         break;
 272     case CHIP_TAHITI:
 273     case CHIP_PITCAIRN:
 274     case CHIP_VERDE:
 275     case CHIP_OLAND:
 276     case CHIP_HAINAN:
 277         ws->info.chip_class = SI;
 278         break;
 279     case CHIP_BONAIRE:
 280     case CHIP_KAVERI:
 281     case CHIP_KABINI:
 282     case CHIP_HAWAII:
 283     case CHIP_MULLINS:
 284         ws->info.chip_class = CIK;
 285         break;
 286     }
 287
 288     /* Check for dma */
 289     ws->info.r600_has_dma = FALSE;
 290     /* DMA is disabled on R700. There is IB corruption and hangs. */
 291     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 292         ws->info.r600_has_dma = TRUE;
 293     }
 294
 295     /* Check for UVD and VCE */
 296     ws->info.has_uvd = FALSE;
 297     ws->info.vce_fw_version = 0x00000000;
 298     if (ws->info.drm_minor >= 32) {
 299         uint32_t value = RADEON_CS_RING_UVD;
 300         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 301                                  "UVD Ring working", &value))
 302             ws->info.has_uvd = value;
 303
 304         value = RADEON_CS_RING_VCE;
 305         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 306                                  NULL, &value) && value) {
 307
 308             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 309                                      "VCE FW version", &value))
 310                 ws->info.vce_fw_version = value;
 311         }
 312     }
 313
 314     /* Get GEM info. */
 315     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 316             &gem_info, sizeof(gem_info));
 317     if (retval) {
 318         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 319                 retval);
 320         return FALSE;
 321     }
 322     ws->info.gart_size = gem_info.gart_size;
 323     ws->info.vram_size = gem_info.vram_size;
 324
 325     /* Get max clock frequency info and convert it to MHz */
 326     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 327                          &ws->info.max_sclk);
 328     ws->info.max_sclk /= 1000;
 329
 330     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 331
 332     /* Generation-specific queries. */
 333     if (ws->gen == DRV_R300) {
 334         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 335                                   "GB pipe count",
 336                                   &ws->info.r300_num_gb_pipes))
 337             return FALSE;
 338
 339         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 340                                   "Z pipe count",
 341                                   &ws->info.r300_num_z_pipes))
 342             return FALSE;
 343     }
 344     else if (ws->gen >= DRV_R600) {
 345         if (ws->info.drm_minor >= 9 &&
 346             !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 347                                   "num backends",
 348                                   &ws->info.r600_num_backends))
 349             return FALSE;
 350
 351         /* get the GPU counter frequency, failure is not fatal */
 352         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 353                              &ws->info.r600_clock_crystal_freq);
 354
 355         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 356                              &ws->info.r600_tiling_config);
 357
 358         if (ws->info.drm_minor >= 11) {
 359             radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 360                                  &ws->info.r600_num_tile_pipes);
 361
 362             if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 363                                       &ws->info.r600_backend_map))
 364                 ws->info.r600_backend_map_valid = TRUE;
 365         }
 366
 367         ws->info.r600_virtual_address = FALSE;
 368         if (ws->info.drm_minor >= 13) {
 369             uint32_t ib_vm_max_size;
 370
 371             ws->info.r600_virtual_address = TRUE;
 372             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 373                                       &ws->va_start))
 374                 ws->info.r600_virtual_address = FALSE;
 375             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 376                                       &ib_vm_max_size))
 377                 ws->info.r600_virtual_address = FALSE;
 378         }
 379         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", FALSE))
 380                 ws->info.r600_virtual_address = FALSE;
 381     }
 382
 383     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 384      * chips have at least 2 pipes, so we use 2 as a default. */
 385     ws->info.r600_max_pipes = 2;
 386     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 387                          &ws->info.r600_max_pipes);
 388
 389     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 390                          &ws->info.max_compute_units);
 391
 392     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 393                          &ws->info.max_se);
 394
 395     if (!ws->info.max_se) {
 396         switch (ws->info.family) {
 397         default:
 398             ws->info.max_se = 1;
 399             break;
 400         case CHIP_CYPRESS:
 401         case CHIP_HEMLOCK:
 402         case CHIP_BARTS:
 403         case CHIP_CAYMAN:
 404         case CHIP_TAHITI:
 405         case CHIP_PITCAIRN:
 406         case CHIP_BONAIRE:
 407             ws->info.max_se = 2;
 408             break;
 409         case CHIP_HAWAII:
 410             ws->info.max_se = 4;
 411             break;
 412         }
 413     }
 414
 415     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 416                          &ws->info.max_sh_per_se);
 417
 418     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 419                          &ws->accel_working2);
 420     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 421         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 422                 "returned accel_working2 value %u is smaller than 2. "
 423                 "Please install a newer kernel.\n",
 424                 ws->accel_working2);
 425         return FALSE;
 426     }
 427
 428     if (radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 429                              ws->info.si_tile_mode_array)) {
 430         ws->info.si_tile_mode_array_valid = TRUE;
 431     }
 432
 433     if (radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 434                              ws->info.cik_macrotile_mode_array)) {
 435         ws->info.cik_macrotile_mode_array_valid = TRUE;
 436     }
 437
 438     return TRUE;
 439 }
 440
 441 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 442 {
 443     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 444
 445     if (ws->thread) {
 446         ws->kill_thread = 1;
 447         pipe_semaphore_signal(&ws->cs_queued);
 448         pipe_thread_wait(ws->thread);
 449     }
 450     pipe_semaphore_destroy(&ws->cs_queued);
 451
 452     pipe_mutex_destroy(ws->hyperz_owner_mutex);
 453     pipe_mutex_destroy(ws->cmask_owner_mutex);
 454     pipe_mutex_destroy(ws->cs_stack_lock);
 455
 456     ws->cman_vram->destroy(ws->cman_vram);
 457     ws->cman_vram_gtt_wc->destroy(ws->cman_vram_gtt_wc);
 458     ws->cman_gtt->destroy(ws->cman_gtt);
 459     ws->cman_gtt_wc->destroy(ws->cman_gtt_wc);
 460     ws->kman->destroy(ws->kman);
 461     if (ws->gen >= DRV_R600) {
 462         radeon_surface_manager_free(ws->surf_man);
 463     }
 464     FREE(rws);
 465 }
 466
 467 static void radeon_query_info(struct radeon_winsys *rws,
 468                               struct radeon_info *info)
 469 {
 470     *info = ((struct radeon_drm_winsys *)rws)->info;
 471 }
 472
 473 static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 474                                          enum radeon_feature_id fid,
 475                                          boolean enable)
 476 {
 477     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 478
 479     switch (fid) {
 480     case RADEON_FID_R300_HYPERZ_ACCESS:
 481         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 482                                     &cs->ws->hyperz_owner_mutex,
 483                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 484                                     enable);
 485
 486     case RADEON_FID_R300_CMASK_ACCESS:
 487         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 488                                     &cs->ws->cmask_owner_mutex,
 489                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 490                                     enable);
 491     }
 492     return FALSE;
 493 }
 494
 495 static int radeon_drm_winsys_surface_init(struct radeon_winsys *rws,
 496                                           struct radeon_surface *surf)
 497 {
 498     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 499
 500     return radeon_surface_init(ws->surf_man, surf);
 501 }
 502
 503 static int radeon_drm_winsys_surface_best(struct radeon_winsys *rws,
 504                                           struct radeon_surface *surf)
 505 {
 506     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 507
 508     return radeon_surface_best(ws->surf_man, surf);
 509 }
 510
 511 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 512                                    enum radeon_value_id value)
 513 {
 514     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 515     uint64_t retval = 0;
 516
 517     switch (value) {
 518     case RADEON_REQUESTED_VRAM_MEMORY:
 519         return ws->allocated_vram;
 520     case RADEON_REQUESTED_GTT_MEMORY:
 521         return ws->allocated_gtt;
 522     case RADEON_BUFFER_WAIT_TIME_NS:
 523         return ws->buffer_wait_time;
 524     case RADEON_TIMESTAMP:
 525         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 526             assert(0);
 527             return 0;
 528         }
 529
 530         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 531                              (uint32_t*)&retval);
 532         return retval;
 533     case RADEON_NUM_CS_FLUSHES:
 534         return ws->num_cs_flushes;
 535     case RADEON_NUM_BYTES_MOVED:
 536         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 537                              "num-bytes-moved", (uint32_t*)&retval);
 538         return retval;
 539     case RADEON_VRAM_USAGE:
 540         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 541                              "vram-usage", (uint32_t*)&retval);
 542         return retval;
 543     case RADEON_GTT_USAGE:
 544         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 545                              "gtt-usage", (uint32_t*)&retval);
 546         return retval;
 547     }
 548     return 0;
 549 }
 550
 551 static unsigned hash_fd(void *key)
 552 {
 553     int fd = pointer_to_intptr(key);
 554     struct stat stat;
 555     fstat(fd, &stat);
 556
 557     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 558 }
 559
 560 static int compare_fd(void *key1, void *key2)
 561 {
 562     int fd1 = pointer_to_intptr(key1);
 563     int fd2 = pointer_to_intptr(key2);
 564     struct stat stat1, stat2;
 565     fstat(fd1, &stat1);
 566     fstat(fd2, &stat2);
 567
 568     return stat1.st_dev != stat2.st_dev ||
 569            stat1.st_ino != stat2.st_ino ||
 570            stat1.st_rdev != stat2.st_rdev;
 571 }
 572
 573 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys *ws, struct radeon_drm_cs *cs)
 574 {
 575 retry:
 576     pipe_mutex_lock(ws->cs_stack_lock);
 577     if (ws->ncs >= RING_LAST) {
 578         /* no room left for a flush */
 579         pipe_mutex_unlock(ws->cs_stack_lock);
 580         goto retry;
 581     }
 582     ws->cs_stack[ws->ncs++] = cs;
 583     pipe_mutex_unlock(ws->cs_stack_lock);
 584     pipe_semaphore_signal(&ws->cs_queued);
 585 }
 586
 587 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param)
 588 {
 589     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys *)param;
 590     struct radeon_drm_cs *cs;
 591     unsigned i;
 592
 593     while (1) {
 594         pipe_semaphore_wait(&ws->cs_queued);
 595         if (ws->kill_thread)
 596             break;
 597
 598         pipe_mutex_lock(ws->cs_stack_lock);
 599         cs = ws->cs_stack[0];
 600         for (i = 1; i < ws->ncs; i++)
 601             ws->cs_stack[i - 1] = ws->cs_stack[i];
 602         ws->cs_stack[--ws->ncs] = NULL;
 603         pipe_mutex_unlock(ws->cs_stack_lock);
 604
 605         if (cs) {
 606             radeon_drm_cs_emit_ioctl_oneshot(cs, cs->cst);
 607             pipe_semaphore_signal(&cs->flush_completed);
 608         }
 609     }
 610     pipe_mutex_lock(ws->cs_stack_lock);
 611     for (i = 0; i < ws->ncs; i++) {
 612         pipe_semaphore_signal(&ws->cs_stack[i]->flush_completed);
 613         ws->cs_stack[i] = NULL;
 614     }
 615     ws->ncs = 0;
 616     pipe_mutex_unlock(ws->cs_stack_lock);
 617     return 0;
 618 }
 619
 620 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", TRUE)
 621 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param);
 622
 623 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 624 {
 625     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 626     bool destroy;
 627
 628     /* When the reference counter drops to zero, remove the fd from the table.
 629      * This must happen while the mutex is locked, so that
 630      * radeon_drm_winsys_create in another thread doesn't get the winsys
 631      * from the table when the counter drops to 0. */
 632     pipe_mutex_lock(fd_tab_mutex);
 633
 634     destroy = pipe_reference(&rws->reference, NULL);
 635     if (destroy && fd_tab)
 636         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 637
 638     pipe_mutex_unlock(fd_tab_mutex);
 639     return destroy;
 640 }
 641
 642 PUBLIC struct radeon_winsys *
 643 radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
 644 {
 645     struct radeon_drm_winsys *ws;
 646
 647     pipe_mutex_lock(fd_tab_mutex);
 648     if (!fd_tab) {
 649         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 650     }
 651
 652     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 653     if (ws) {
 654         pipe_reference(NULL, &ws->reference);
 655         pipe_mutex_unlock(fd_tab_mutex);
 656         return &ws->base;
 657     }
 658
 659     ws = CALLOC_STRUCT(radeon_drm_winsys);
 660     if (!ws) {
 661         pipe_mutex_unlock(fd_tab_mutex);
 662         return NULL;
 663     }
 664
 665     ws->fd = fd;
 666
 667     if (!do_winsys_init(ws))
 668         goto fail;
 669
 670     /* Create managers. */
 671     ws->kman = radeon_bomgr_create(ws);
 672     if (!ws->kman)
 673         goto fail;
 674     ws->cman_vram = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0);
 675     if (!ws->cman_vram)
 676         goto fail;
 677     ws->cman_vram_gtt_wc = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0);
 678     if (!ws->cman_vram_gtt_wc)
 679         goto fail;
 680     ws->cman_gtt = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0);
 681     if (!ws->cman_gtt)
 682         goto fail;
 683     ws->cman_gtt_wc = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0);
 684     if (!ws->cman_gtt_wc)
 685         goto fail;
 686
 687     if (ws->gen >= DRV_R600) {
 688         ws->surf_man = radeon_surface_manager_new(fd);
 689         if (!ws->surf_man)
 690             goto fail;
 691     }
 692
 693     /* init reference */
 694     pipe_reference_init(&ws->reference, 1);
 695
 696     /* Set functions. */
 697     ws->base.unref = radeon_winsys_unref;
 698     ws->base.destroy = radeon_winsys_destroy;
 699     ws->base.query_info = radeon_query_info;
 700     ws->base.cs_request_feature = radeon_cs_request_feature;
 701     ws->base.surface_init = radeon_drm_winsys_surface_init;
 702     ws->base.surface_best = radeon_drm_winsys_surface_best;
 703     ws->base.query_value = radeon_query_value;
 704
 705     radeon_bomgr_init_functions(ws);
 706     radeon_drm_cs_init_functions(ws);
 707
 708     pipe_mutex_init(ws->hyperz_owner_mutex);
 709     pipe_mutex_init(ws->cmask_owner_mutex);
 710     pipe_mutex_init(ws->cs_stack_lock);
 711
 712     ws->ncs = 0;
 713     pipe_semaphore_init(&ws->cs_queued, 0);
 714     if (ws->num_cpus > 1 && debug_get_option_thread())
 715         ws->thread = pipe_thread_create(radeon_drm_cs_emit_ioctl, ws);
 716
 717     /* Create the screen at the end. The winsys must be initialized
 718      * completely.
 719      *
 720      * Alternatively, we could create the screen based on "ws->gen"
 721      * and link all drivers into one binary blob. */
 722     ws->base.screen = screen_create(&ws->base);
 723     if (!ws->base.screen) {
 724         radeon_winsys_destroy(&ws->base);
 725         pipe_mutex_unlock(fd_tab_mutex);
 726         return NULL;
 727     }
 728
 729     util_hash_table_set(fd_tab, intptr_to_pointer(fd), ws);
 730
 731     /* We must unlock the mutex once the winsys is fully initialized, so that
 732      * other threads attempting to create the winsys from the same fd will
 733      * get a fully initialized winsys and not just half-way initialized. */
 734     pipe_mutex_unlock(fd_tab_mutex);
 735
 736     return &ws->base;
 737
 738 fail:
 739     pipe_mutex_unlock(fd_tab_mutex);
 740     if (ws->cman_gtt)
 741         ws->cman_gtt->destroy(ws->cman_gtt);
 742     if (ws->cman_gtt_wc)
 743         ws->cman_gtt_wc->destroy(ws->cman_gtt_wc);
 744     if (ws->cman_vram)
 745         ws->cman_vram->destroy(ws->cman_vram);
 746     if (ws->cman_vram_gtt_wc)
 747         ws->cman_vram_gtt_wc->destroy(ws->cman_vram_gtt_wc);
 748     if (ws->kman)
 749         ws->kman->destroy(ws->kman);
 750     if (ws->surf_man)
 751         radeon_surface_manager_free(ws->surf_man);
 752     FREE(ws);
 753     return NULL;
 754 }