2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "radeon_drm_bo.h"
29 #include "radeon_drm_cs.h"
30 #include "radeon_drm_public.h"
32 #include "util/u_cpu_detect.h"
33 #include "util/u_memory.h"
34 #include "util/u_hash_table.h"
38 #include <sys/types.h>
42 #include <radeon_surface.h>
44 static struct util_hash_table
*fd_tab
= NULL
;
45 static mtx_t fd_tab_mutex
= _MTX_INITIALIZER_NP
;
47 /* Enable/disable feature access for one command stream.
48 * If enable == true, return true on success.
49 * Otherwise, return false.
51 * We basically do the same thing kernel does, because we have to deal
52 * with multiple contexts (here command streams) backed by one winsys. */
53 static bool radeon_set_fd_access(struct radeon_drm_cs
*applier
,
54 struct radeon_drm_cs
**owner
,
56 unsigned request
, const char *request_name
,
59 struct drm_radeon_info info
;
60 unsigned value
= enable
? 1 : 0;
62 memset(&info
, 0, sizeof(info
));
66 /* Early exit if we are sure the request will fail. */
73 if (*owner
!= applier
) {
79 /* Pass through the request to the kernel. */
80 info
.value
= (unsigned long)&value
;
81 info
.request
= request
;
82 if (drmCommandWriteRead(applier
->ws
->fd
, DRM_RADEON_INFO
,
83 &info
, sizeof(info
)) != 0) {
88 /* Update the rights in the winsys. */
103 static bool radeon_get_drm_value(int fd
, unsigned request
,
104 const char *errname
, uint32_t *out
)
106 struct drm_radeon_info info
;
109 memset(&info
, 0, sizeof(info
));
111 info
.value
= (unsigned long)out
;
112 info
.request
= request
;
114 retval
= drmCommandWriteRead(fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
117 fprintf(stderr
, "radeon: Failed to get %s, error number %d\n",
125 /* Helper function to do the ioctls needed for setup and init. */
126 static bool do_winsys_init(struct radeon_drm_winsys
*ws
)
128 struct drm_radeon_gem_info gem_info
;
130 drmVersionPtr version
;
132 memset(&gem_info
, 0, sizeof(gem_info
));
134 /* We do things in a specific order here.
136 * DRM version first. We need to be sure we're running on a KMS chipset.
137 * This is also for some features.
139 * Then, the PCI ID. This is essential and should return usable numbers
140 * for all Radeons. If this fails, we probably got handed an FD for some
143 * The GEM info is actually bogus on the kernel side, as well as our side
144 * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
145 * we don't actually use the info for anything yet.
147 * The GB and Z pipe requests should always succeed, but they might not
148 * return sensical values for all chipsets, but that's alright because
149 * the pipe drivers already know that.
152 /* Get DRM version. */
153 version
= drmGetVersion(ws
->fd
);
154 if (version
->version_major
!= 2 ||
155 version
->version_minor
< 12) {
156 fprintf(stderr
, "%s: DRM version is %d.%d.%d but this driver is "
157 "only compatible with 2.12.0 (kernel 3.2) or later.\n",
159 version
->version_major
,
160 version
->version_minor
,
161 version
->version_patchlevel
);
162 drmFreeVersion(version
);
166 ws
->info
.drm_major
= version
->version_major
;
167 ws
->info
.drm_minor
= version
->version_minor
;
168 ws
->info
.drm_patchlevel
= version
->version_patchlevel
;
169 drmFreeVersion(version
);
172 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_DEVICE_ID
, "PCI ID",
177 switch (ws
->info
.pci_id
) {
178 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
179 #include "pci_ids/r300_pci_ids.h"
182 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
183 #include "pci_ids/r600_pci_ids.h"
186 #define CHIPSET(pci_id, cfamily) \
188 ws->info.family = CHIP_##cfamily; \
189 ws->info.name = #cfamily; \
192 #include "pci_ids/radeonsi_pci_ids.h"
196 fprintf(stderr
, "radeon: Invalid PCI ID.\n");
200 switch (ws
->info
.family
) {
203 fprintf(stderr
, "radeon: Unknown family.\n");
213 ws
->info
.chip_class
= R300
;
215 case CHIP_R420
: /* R4xx-based cores. */
224 ws
->info
.chip_class
= R400
;
226 case CHIP_RV515
: /* R5xx-based cores. */
232 ws
->info
.chip_class
= R500
;
242 ws
->info
.chip_class
= R600
;
248 ws
->info
.chip_class
= R700
;
261 ws
->info
.chip_class
= EVERGREEN
;
265 ws
->info
.chip_class
= CAYMAN
;
272 ws
->info
.chip_class
= GFX6
;
279 ws
->info
.chip_class
= GFX7
;
283 /* Set which chips don't have dedicated VRAM. */
284 switch (ws
->info
.family
) {
300 ws
->info
.has_dedicated_vram
= false;
304 ws
->info
.has_dedicated_vram
= true;
308 ws
->info
.num_sdma_rings
= 0;
309 /* DMA is disabled on R700. There is IB corruption and hangs. */
310 if (ws
->info
.chip_class
>= EVERGREEN
&& ws
->info
.drm_minor
>= 27) {
311 ws
->info
.num_sdma_rings
= 1;
314 /* Check for UVD and VCE */
315 ws
->info
.has_hw_decode
= false;
316 ws
->info
.vce_fw_version
= 0x00000000;
317 if (ws
->info
.drm_minor
>= 32) {
318 uint32_t value
= RADEON_CS_RING_UVD
;
319 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_RING_WORKING
,
320 "UVD Ring working", &value
))
321 ws
->info
.has_hw_decode
= value
;
323 value
= RADEON_CS_RING_VCE
;
324 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_RING_WORKING
,
325 NULL
, &value
) && value
) {
327 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_VCE_FW_VERSION
,
328 "VCE FW version", &value
))
329 ws
->info
.vce_fw_version
= value
;
333 /* Check for userptr support. */
335 struct drm_radeon_gem_userptr args
= {0};
337 /* If the ioctl doesn't exist, -EINVAL is returned.
339 * If the ioctl exists, it should return -EACCES
340 * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
343 ws
->info
.has_userptr
=
344 drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_USERPTR
,
345 &args
, sizeof(args
)) == -EACCES
;
349 retval
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_INFO
,
350 &gem_info
, sizeof(gem_info
));
352 fprintf(stderr
, "radeon: Failed to get MM info, error number %d\n",
356 ws
->info
.gart_size
= gem_info
.gart_size
;
357 ws
->info
.vram_size
= gem_info
.vram_size
;
358 ws
->info
.vram_vis_size
= gem_info
.vram_visible
;
359 /* Older versions of the kernel driver reported incorrect values, and
360 * didn't support more than 256MB of visible VRAM anyway
362 if (ws
->info
.drm_minor
< 49)
363 ws
->info
.vram_vis_size
= MIN2(ws
->info
.vram_vis_size
, 256*1024*1024);
365 /* Radeon allocates all buffers contiguously, which makes large allocations
366 * unlikely to succeed. */
367 if (ws
->info
.has_dedicated_vram
)
368 ws
->info
.max_alloc_size
= ws
->info
.vram_size
* 0.7;
370 ws
->info
.max_alloc_size
= ws
->info
.gart_size
* 0.7;
372 if (ws
->info
.drm_minor
< 40)
373 ws
->info
.max_alloc_size
= MIN2(ws
->info
.max_alloc_size
, 256*1024*1024);
374 /* Both 32-bit and 64-bit address spaces only have 4GB. */
375 ws
->info
.max_alloc_size
= MIN2(ws
->info
.max_alloc_size
, 3ull*1024*1024*1024);
377 /* Get max clock frequency info and convert it to MHz */
378 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SCLK
, NULL
,
379 &ws
->info
.max_shader_clock
);
380 ws
->info
.max_shader_clock
/= 1000;
382 ws
->num_cpus
= sysconf(_SC_NPROCESSORS_ONLN
);
384 /* Generation-specific queries. */
385 if (ws
->gen
== DRV_R300
) {
386 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_GB_PIPES
,
388 &ws
->info
.r300_num_gb_pipes
))
391 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_Z_PIPES
,
393 &ws
->info
.r300_num_z_pipes
))
396 else if (ws
->gen
>= DRV_R600
) {
397 uint32_t tiling_config
= 0;
399 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BACKENDS
,
401 &ws
->info
.num_render_backends
))
404 /* get the GPU counter frequency, failure is not fatal */
405 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CLOCK_CRYSTAL_FREQ
, NULL
,
406 &ws
->info
.clock_crystal_freq
);
408 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TILING_CONFIG
, NULL
,
411 ws
->info
.r600_num_banks
=
412 ws
->info
.chip_class
>= EVERGREEN
?
413 4 << ((tiling_config
& 0xf0) >> 4) :
414 4 << ((tiling_config
& 0x30) >> 4);
416 ws
->info
.pipe_interleave_bytes
=
417 ws
->info
.chip_class
>= EVERGREEN
?
418 256 << ((tiling_config
& 0xf00) >> 8) :
419 256 << ((tiling_config
& 0xc0) >> 6);
421 if (!ws
->info
.pipe_interleave_bytes
)
422 ws
->info
.pipe_interleave_bytes
=
423 ws
->info
.chip_class
>= EVERGREEN
? 512 : 256;
425 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_TILE_PIPES
, NULL
,
426 &ws
->info
.num_tile_pipes
);
428 /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
429 * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
430 * reports a different value (12). Fix it by setting what's in the
431 * GB_TILE_MODE array (8).
433 if (ws
->gen
== DRV_SI
&& ws
->info
.num_tile_pipes
== 12)
434 ws
->info
.num_tile_pipes
= 8;
436 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_BACKEND_MAP
, NULL
,
437 &ws
->info
.r600_gb_backend_map
))
438 ws
->info
.r600_gb_backend_map_valid
= true;
441 ws
->info
.enabled_rb_mask
= u_bit_consecutive(0, ws
->info
.num_render_backends
);
443 * This fails (silently) on non-GCN or older kernels, overwriting the
444 * default enabled_rb_mask with the result of the last query.
446 if (ws
->gen
>= DRV_SI
)
447 radeon_get_drm_value(ws
->fd
, RADEON_INFO_SI_BACKEND_ENABLED_MASK
, NULL
,
448 &ws
->info
.enabled_rb_mask
);
450 ws
->info
.r600_has_virtual_memory
= false;
451 if (ws
->info
.drm_minor
>= 13) {
452 uint32_t ib_vm_max_size
;
454 ws
->info
.r600_has_virtual_memory
= true;
455 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_VA_START
, NULL
,
457 ws
->info
.r600_has_virtual_memory
= false;
458 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_IB_VM_MAX_SIZE
, NULL
,
460 ws
->info
.r600_has_virtual_memory
= false;
461 radeon_get_drm_value(ws
->fd
, RADEON_INFO_VA_UNMAP_WORKING
, NULL
,
462 &ws
->va_unmap_working
);
464 if (ws
->gen
== DRV_R600
&& !debug_get_bool_option("RADEON_VA", false))
465 ws
->info
.r600_has_virtual_memory
= false;
468 /* Get max pipes, this is only needed for compute shaders. All evergreen+
469 * chips have at least 2 pipes, so we use 2 as a default. */
470 ws
->info
.r600_max_quad_pipes
= 2;
471 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_PIPES
, NULL
,
472 &ws
->info
.r600_max_quad_pipes
);
474 /* All GPUs have at least one compute unit */
475 ws
->info
.num_good_compute_units
= 1;
476 radeon_get_drm_value(ws
->fd
, RADEON_INFO_ACTIVE_CU_COUNT
, NULL
,
477 &ws
->info
.num_good_compute_units
);
479 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SE
, NULL
,
482 switch (ws
->info
.family
) {
486 ws
->info
.num_tcc_blocks
= 2;
492 ws
->info
.num_tcc_blocks
= 4;
495 ws
->info
.num_tcc_blocks
= 8;
498 ws
->info
.num_tcc_blocks
= 12;
501 ws
->info
.num_tcc_blocks
= 16;
504 ws
->info
.num_tcc_blocks
= 0;
508 if (!ws
->info
.max_se
) {
509 switch (ws
->info
.family
) {
528 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SH_PER_SE
, NULL
,
529 &ws
->info
.max_sh_per_se
);
530 if (ws
->gen
== DRV_SI
) {
531 ws
->info
.num_good_cu_per_sh
= ws
->info
.num_good_compute_units
/
532 (ws
->info
.max_se
* ws
->info
.max_sh_per_se
);
535 radeon_get_drm_value(ws
->fd
, RADEON_INFO_ACCEL_WORKING2
, NULL
,
536 &ws
->accel_working2
);
537 if (ws
->info
.family
== CHIP_HAWAII
&& ws
->accel_working2
< 2) {
538 fprintf(stderr
, "radeon: GPU acceleration for Hawaii disabled, "
539 "returned accel_working2 value %u is smaller than 2. "
540 "Please install a newer kernel.\n",
545 if (ws
->info
.chip_class
== GFX7
) {
546 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY
, NULL
,
547 ws
->info
.cik_macrotile_mode_array
)) {
548 fprintf(stderr
, "radeon: Kernel 3.13 is required for Sea Islands support.\n");
553 if (ws
->info
.chip_class
>= GFX6
) {
554 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_SI_TILE_MODE_ARRAY
, NULL
,
555 ws
->info
.si_tile_mode_array
)) {
556 fprintf(stderr
, "radeon: Kernel 3.10 is required for Southern Islands support.\n");
561 /* Hawaii with old firmware needs type2 nop packet.
562 * accel_working2 with value 3 indicates the new firmware.
564 ws
->info
.gfx_ib_pad_with_type2
= ws
->info
.chip_class
<= GFX6
||
565 (ws
->info
.family
== CHIP_HAWAII
&&
566 ws
->accel_working2
< 3);
567 ws
->info
.tcc_cache_line_size
= 64; /* TC L2 line size on GCN */
568 ws
->info
.ib_start_alignment
= 4096;
569 ws
->info
.kernel_flushes_hdp_before_ib
= ws
->info
.drm_minor
>= 40;
570 /* HTILE is broken with 1D tiling on old kernels and GFX7. */
571 ws
->info
.htile_cmask_support_1d_tiling
= ws
->info
.chip_class
!= GFX7
||
572 ws
->info
.drm_minor
>= 38;
573 ws
->info
.si_TA_CS_BC_BASE_ADDR_allowed
= ws
->info
.drm_minor
>= 48;
574 ws
->info
.has_bo_metadata
= false;
575 ws
->info
.has_gpu_reset_status_query
= ws
->info
.drm_minor
>= 43;
576 ws
->info
.has_gpu_reset_counter_query
= ws
->info
.drm_minor
>= 43;
577 ws
->info
.has_eqaa_surface_allocator
= false;
578 ws
->info
.has_format_bc1_through_bc7
= ws
->info
.drm_minor
>= 31;
579 ws
->info
.kernel_flushes_tc_l2_after_ib
= true;
580 /* Old kernels disallowed register writes via COPY_DATA
581 * that are used for indirect compute dispatches. */
582 ws
->info
.has_indirect_compute_dispatch
= ws
->info
.chip_class
== GFX7
||
583 (ws
->info
.chip_class
== GFX6
&&
584 ws
->info
.drm_minor
>= 45);
585 /* GFX6 doesn't support unaligned loads. */
586 ws
->info
.has_unaligned_shader_loads
= ws
->info
.chip_class
== GFX7
&&
587 ws
->info
.drm_minor
>= 50;
588 ws
->info
.has_sparse_vm_mappings
= false;
589 /* 2D tiling on GFX7 is supported since DRM 2.35.0 */
590 ws
->info
.has_2d_tiling
= ws
->info
.chip_class
<= GFX6
|| ws
->info
.drm_minor
>= 35;
591 ws
->info
.has_read_registers_query
= ws
->info
.drm_minor
>= 42;
592 ws
->info
.max_alignment
= 1024*1024;
594 ws
->check_vm
= strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL
;
599 static void radeon_winsys_destroy(struct radeon_winsys
*rws
)
601 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
603 if (util_queue_is_initialized(&ws
->cs_queue
))
604 util_queue_destroy(&ws
->cs_queue
);
606 mtx_destroy(&ws
->hyperz_owner_mutex
);
607 mtx_destroy(&ws
->cmask_owner_mutex
);
609 if (ws
->info
.r600_has_virtual_memory
)
610 pb_slabs_deinit(&ws
->bo_slabs
);
611 pb_cache_deinit(&ws
->bo_cache
);
613 if (ws
->gen
>= DRV_R600
) {
614 radeon_surface_manager_free(ws
->surf_man
);
617 util_hash_table_destroy(ws
->bo_names
);
618 util_hash_table_destroy(ws
->bo_handles
);
619 util_hash_table_destroy(ws
->bo_vas
);
620 mtx_destroy(&ws
->bo_handles_mutex
);
621 mtx_destroy(&ws
->vm32
.mutex
);
622 mtx_destroy(&ws
->vm64
.mutex
);
623 mtx_destroy(&ws
->bo_fence_lock
);
631 static void radeon_query_info(struct radeon_winsys
*rws
,
632 struct radeon_info
*info
)
634 *info
= ((struct radeon_drm_winsys
*)rws
)->info
;
637 static bool radeon_cs_request_feature(struct radeon_cmdbuf
*rcs
,
638 enum radeon_feature_id fid
,
641 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
644 case RADEON_FID_R300_HYPERZ_ACCESS
:
645 return radeon_set_fd_access(cs
, &cs
->ws
->hyperz_owner
,
646 &cs
->ws
->hyperz_owner_mutex
,
647 RADEON_INFO_WANT_HYPERZ
, "Hyper-Z",
650 case RADEON_FID_R300_CMASK_ACCESS
:
651 return radeon_set_fd_access(cs
, &cs
->ws
->cmask_owner
,
652 &cs
->ws
->cmask_owner_mutex
,
653 RADEON_INFO_WANT_CMASK
, "AA optimizations",
659 uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys
*ws
)
663 if (!ws
->info
.has_gpu_reset_status_query
)
666 radeon_get_drm_value(ws
->fd
, RADEON_INFO_GPU_RESET_COUNTER
,
667 "gpu-reset-counter", (uint32_t*)&retval
);
671 static uint64_t radeon_query_value(struct radeon_winsys
*rws
,
672 enum radeon_value_id value
)
674 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
678 case RADEON_REQUESTED_VRAM_MEMORY
:
679 return ws
->allocated_vram
;
680 case RADEON_REQUESTED_GTT_MEMORY
:
681 return ws
->allocated_gtt
;
682 case RADEON_MAPPED_VRAM
:
683 return ws
->mapped_vram
;
684 case RADEON_MAPPED_GTT
:
685 return ws
->mapped_gtt
;
686 case RADEON_BUFFER_WAIT_TIME_NS
:
687 return ws
->buffer_wait_time
;
688 case RADEON_NUM_MAPPED_BUFFERS
:
689 return ws
->num_mapped_buffers
;
690 case RADEON_TIMESTAMP
:
691 if (ws
->info
.drm_minor
< 20 || ws
->gen
< DRV_R600
) {
696 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TIMESTAMP
, "timestamp",
699 case RADEON_NUM_GFX_IBS
:
700 return ws
->num_gfx_IBs
;
701 case RADEON_NUM_SDMA_IBS
:
702 return ws
->num_sdma_IBs
;
703 case RADEON_NUM_BYTES_MOVED
:
704 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BYTES_MOVED
,
705 "num-bytes-moved", (uint32_t*)&retval
);
707 case RADEON_NUM_EVICTIONS
:
708 case RADEON_NUM_VRAM_CPU_PAGE_FAULTS
:
709 case RADEON_VRAM_VIS_USAGE
:
710 case RADEON_GFX_BO_LIST_COUNTER
:
711 case RADEON_GFX_IB_SIZE_COUNTER
:
712 return 0; /* unimplemented */
713 case RADEON_VRAM_USAGE
:
714 radeon_get_drm_value(ws
->fd
, RADEON_INFO_VRAM_USAGE
,
715 "vram-usage", (uint32_t*)&retval
);
717 case RADEON_GTT_USAGE
:
718 radeon_get_drm_value(ws
->fd
, RADEON_INFO_GTT_USAGE
,
719 "gtt-usage", (uint32_t*)&retval
);
721 case RADEON_GPU_TEMPERATURE
:
722 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CURRENT_GPU_TEMP
,
723 "gpu-temp", (uint32_t*)&retval
);
725 case RADEON_CURRENT_SCLK
:
726 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CURRENT_GPU_SCLK
,
727 "current-gpu-sclk", (uint32_t*)&retval
);
729 case RADEON_CURRENT_MCLK
:
730 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CURRENT_GPU_MCLK
,
731 "current-gpu-mclk", (uint32_t*)&retval
);
733 case RADEON_GPU_RESET_COUNTER
:
734 radeon_get_drm_value(ws
->fd
, RADEON_INFO_GPU_RESET_COUNTER
,
735 "gpu-reset-counter", (uint32_t*)&retval
);
737 case RADEON_CS_THREAD_TIME
:
738 return util_queue_get_thread_time_nano(&ws
->cs_queue
, 0);
743 static bool radeon_read_registers(struct radeon_winsys
*rws
,
745 unsigned num_registers
, uint32_t *out
)
747 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
750 for (i
= 0; i
< num_registers
; i
++) {
751 uint32_t reg
= reg_offset
+ i
*4;
753 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_READ_REG
, NULL
, ®
))
760 static unsigned hash_fd(void *key
)
762 int fd
= pointer_to_intptr(key
);
766 return stat
.st_dev
^ stat
.st_ino
^ stat
.st_rdev
;
769 static int compare_fd(void *key1
, void *key2
)
771 int fd1
= pointer_to_intptr(key1
);
772 int fd2
= pointer_to_intptr(key2
);
773 struct stat stat1
, stat2
;
777 return stat1
.st_dev
!= stat2
.st_dev
||
778 stat1
.st_ino
!= stat2
.st_ino
||
779 stat1
.st_rdev
!= stat2
.st_rdev
;
782 DEBUG_GET_ONCE_BOOL_OPTION(thread
, "RADEON_THREAD", true)
784 static bool radeon_winsys_unref(struct radeon_winsys
*ws
)
786 struct radeon_drm_winsys
*rws
= (struct radeon_drm_winsys
*)ws
;
789 /* When the reference counter drops to zero, remove the fd from the table.
790 * This must happen while the mutex is locked, so that
791 * radeon_drm_winsys_create in another thread doesn't get the winsys
792 * from the table when the counter drops to 0. */
793 mtx_lock(&fd_tab_mutex
);
795 destroy
= pipe_reference(&rws
->reference
, NULL
);
796 if (destroy
&& fd_tab
) {
797 util_hash_table_remove(fd_tab
, intptr_to_pointer(rws
->fd
));
798 if (util_hash_table_count(fd_tab
) == 0) {
799 util_hash_table_destroy(fd_tab
);
804 mtx_unlock(&fd_tab_mutex
);
808 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
810 static unsigned handle_hash(void *key
)
812 return PTR_TO_UINT(key
);
815 static int handle_compare(void *key1
, void *key2
)
817 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
820 static void radeon_pin_threads_to_L3_cache(struct radeon_winsys
*ws
,
823 struct radeon_drm_winsys
*rws
= (struct radeon_drm_winsys
*)ws
;
825 if (util_queue_is_initialized(&rws
->cs_queue
)) {
826 util_pin_thread_to_L3(rws
->cs_queue
.threads
[0], cache
,
827 util_cpu_caps
.cores_per_L3
);
831 PUBLIC
struct radeon_winsys
*
832 radeon_drm_winsys_create(int fd
, const struct pipe_screen_config
*config
,
833 radeon_screen_create_t screen_create
)
835 struct radeon_drm_winsys
*ws
;
837 mtx_lock(&fd_tab_mutex
);
839 fd_tab
= util_hash_table_create(hash_fd
, compare_fd
);
842 ws
= util_hash_table_get(fd_tab
, intptr_to_pointer(fd
));
844 pipe_reference(NULL
, &ws
->reference
);
845 mtx_unlock(&fd_tab_mutex
);
849 ws
= CALLOC_STRUCT(radeon_drm_winsys
);
851 mtx_unlock(&fd_tab_mutex
);
855 ws
->fd
= fcntl(fd
, F_DUPFD_CLOEXEC
, 3);
857 if (!do_winsys_init(ws
))
860 pb_cache_init(&ws
->bo_cache
, RADEON_MAX_CACHED_HEAPS
,
861 500000, ws
->check_vm
? 1.0f
: 2.0f
, 0,
862 MIN2(ws
->info
.vram_size
, ws
->info
.gart_size
),
864 radeon_bo_can_reclaim
);
866 if (ws
->info
.r600_has_virtual_memory
) {
867 /* There is no fundamental obstacle to using slab buffer allocation
868 * without GPUVM, but enabling it requires making sure that the drivers
869 * honor the address offset.
871 if (!pb_slabs_init(&ws
->bo_slabs
,
872 RADEON_SLAB_MIN_SIZE_LOG2
, RADEON_SLAB_MAX_SIZE_LOG2
,
873 RADEON_MAX_SLAB_HEAPS
,
875 radeon_bo_can_reclaim_slab
,
876 radeon_bo_slab_alloc
,
877 radeon_bo_slab_free
))
880 ws
->info
.min_alloc_size
= 1 << RADEON_SLAB_MIN_SIZE_LOG2
;
882 ws
->info
.min_alloc_size
= ws
->info
.gart_page_size
;
885 if (ws
->gen
>= DRV_R600
) {
886 ws
->surf_man
= radeon_surface_manager_new(ws
->fd
);
892 pipe_reference_init(&ws
->reference
, 1);
895 ws
->base
.unref
= radeon_winsys_unref
;
896 ws
->base
.destroy
= radeon_winsys_destroy
;
897 ws
->base
.query_info
= radeon_query_info
;
898 ws
->base
.pin_threads_to_L3_cache
= radeon_pin_threads_to_L3_cache
;
899 ws
->base
.cs_request_feature
= radeon_cs_request_feature
;
900 ws
->base
.query_value
= radeon_query_value
;
901 ws
->base
.read_registers
= radeon_read_registers
;
903 radeon_drm_bo_init_functions(ws
);
904 radeon_drm_cs_init_functions(ws
);
905 radeon_surface_init_functions(ws
);
907 (void) mtx_init(&ws
->hyperz_owner_mutex
, mtx_plain
);
908 (void) mtx_init(&ws
->cmask_owner_mutex
, mtx_plain
);
910 ws
->bo_names
= util_hash_table_create(handle_hash
, handle_compare
);
911 ws
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
912 ws
->bo_vas
= util_hash_table_create(handle_hash
, handle_compare
);
913 (void) mtx_init(&ws
->bo_handles_mutex
, mtx_plain
);
914 (void) mtx_init(&ws
->vm32
.mutex
, mtx_plain
);
915 (void) mtx_init(&ws
->vm64
.mutex
, mtx_plain
);
916 (void) mtx_init(&ws
->bo_fence_lock
, mtx_plain
);
917 list_inithead(&ws
->vm32
.holes
);
918 list_inithead(&ws
->vm64
.holes
);
920 /* The kernel currently returns 8MB. Make sure this doesn't change. */
921 if (ws
->va_start
> 8 * 1024 * 1024) {
922 /* Not enough 32-bit address space. */
923 radeon_winsys_destroy(&ws
->base
);
924 mtx_unlock(&fd_tab_mutex
);
928 ws
->vm32
.start
= ws
->va_start
;
929 ws
->vm32
.end
= 1ull << 32;
931 /* The maximum is 8GB of virtual address space limited by the kernel.
932 * It's obviously not enough for bigger cards, like Hawaiis with 4GB
933 * and 8GB of physical memory and 4GB of GART.
935 * Older kernels set the limit to 4GB, which is even worse, so they only
936 * have 32-bit address space.
938 if (ws
->info
.drm_minor
>= 41) {
939 ws
->vm64
.start
= 1ull << 32;
940 ws
->vm64
.end
= 1ull << 33;
943 /* TTM aligns the BO size to the CPU page size */
944 ws
->info
.gart_page_size
= sysconf(_SC_PAGESIZE
);
946 if (ws
->num_cpus
> 1 && debug_get_option_thread())
947 util_queue_init(&ws
->cs_queue
, "rcs", 8, 1, 0);
949 /* Create the screen at the end. The winsys must be initialized
952 * Alternatively, we could create the screen based on "ws->gen"
953 * and link all drivers into one binary blob. */
954 ws
->base
.screen
= screen_create(&ws
->base
, config
);
955 if (!ws
->base
.screen
) {
956 radeon_winsys_destroy(&ws
->base
);
957 mtx_unlock(&fd_tab_mutex
);
961 util_hash_table_set(fd_tab
, intptr_to_pointer(ws
->fd
), ws
);
963 /* We must unlock the mutex once the winsys is fully initialized, so that
964 * other threads attempting to create the winsys from the same fd will
965 * get a fully initialized winsys and not just half-way initialized. */
966 mtx_unlock(&fd_tab_mutex
);
971 if (ws
->info
.r600_has_virtual_memory
)
972 pb_slabs_deinit(&ws
->bo_slabs
);
974 pb_cache_deinit(&ws
->bo_cache
);
976 mtx_unlock(&fd_tab_mutex
);
978 radeon_surface_manager_free(ws
->surf_man
);