src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "pipebuffer/pb_bufmgr.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_hash_table.h"
  41
  42 #include <xf86drm.h>
  43 #include <stdio.h>
  44
  45 /*
  46  * this are copy from radeon_drm, once an updated libdrm is released
  47  * we should bump configure.ac requirement for it and remove the following
  48  * field
  49  */
  50 #ifndef RADEON_INFO_TILING_CONFIG
  51 #define RADEON_INFO_TILING_CONFIG 6
  52 #endif
  53
  54 #ifndef RADEON_INFO_WANT_HYPERZ
  55 #define RADEON_INFO_WANT_HYPERZ 7
  56 #endif
  57
  58 #ifndef RADEON_INFO_WANT_CMASK
  59 #define RADEON_INFO_WANT_CMASK 8
  60 #endif
  61
  62 #ifndef RADEON_INFO_CLOCK_CRYSTAL_FREQ
  63 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 9
  64 #endif
  65
  66 #ifndef RADEON_INFO_NUM_BACKENDS
  67 #define RADEON_INFO_NUM_BACKENDS 0xa
  68 #endif
  69
  70 #ifndef RADEON_INFO_NUM_TILE_PIPES
  71 #define RADEON_INFO_NUM_TILE_PIPES 0xb
  72 #endif
  73
  74 #ifndef RADEON_INFO_BACKEND_MAP
  75 #define RADEON_INFO_BACKEND_MAP 0xd
  76 #endif
  77
  78 #ifndef RADEON_INFO_VA_START
  79 /* virtual address start, va < start are reserved by the kernel */
  80 #define RADEON_INFO_VA_START        0x0e
  81 /* maximum size of ib using the virtual memory cs */
  82 #define RADEON_INFO_IB_VM_MAX_SIZE  0x0f
  83 #endif
  84
  85 #ifndef RADEON_INFO_MAX_PIPES
  86 #define RADEON_INFO_MAX_PIPES 0x10
  87 #endif
  88
  89 #ifndef RADEON_INFO_TIMESTAMP
  90 #define RADEON_INFO_TIMESTAMP 0x11
  91 #endif
  92
  93 static struct util_hash_table *fd_tab = NULL;
  94
  95 /* Enable/disable feature access for one command stream.
  96  * If enable == TRUE, return TRUE on success.
  97  * Otherwise, return FALSE.
  98  *
  99  * We basically do the same thing kernel does, because we have to deal
 100  * with multiple contexts (here command streams) backed by one winsys. */
 101 static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
 102                                     struct radeon_drm_cs **owner,
 103                                     pipe_mutex *mutex,
 104                                     unsigned request, const char *request_name,
 105                                     boolean enable)
 106 {
 107     struct drm_radeon_info info;
 108     unsigned value = enable ? 1 : 0;
 109
 110     memset(&info, 0, sizeof(info));
 111
 112     pipe_mutex_lock(*mutex);
 113
 114     /* Early exit if we are sure the request will fail. */
 115     if (enable) {
 116         if (*owner) {
 117             pipe_mutex_unlock(*mutex);
 118             return FALSE;
 119         }
 120     } else {
 121         if (*owner != applier) {
 122             pipe_mutex_unlock(*mutex);
 123             return FALSE;
 124         }
 125     }
 126
 127     /* Pass through the request to the kernel. */
 128     info.value = (unsigned long)&value;
 129     info.request = request;
 130     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
 131                             &info, sizeof(info)) != 0) {
 132         pipe_mutex_unlock(*mutex);
 133         return FALSE;
 134     }
 135
 136     /* Update the rights in the winsys. */
 137     if (enable) {
 138         if (value) {
 139             *owner = applier;
 140             printf("radeon: Acquired access to %s.\n", request_name);
 141             pipe_mutex_unlock(*mutex);
 142             return TRUE;
 143         }
 144     } else {
 145         *owner = NULL;
 146         printf("radeon: Released access to %s.\n", request_name);
 147     }
 148
 149     pipe_mutex_unlock(*mutex);
 150     return FALSE;
 151 }
 152
 153 static boolean radeon_get_drm_value(int fd, unsigned request,
 154                                     const char *errname, uint32_t *out)
 155 {
 156     struct drm_radeon_info info;
 157     int retval;
 158
 159     memset(&info, 0, sizeof(info));
 160
 161     info.value = (unsigned long)out;
 162     info.request = request;
 163
 164     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 165     if (retval) {
 166         if (errname) {
 167             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 168                     errname, retval);
 169         }
 170         return FALSE;
 171     }
 172     return TRUE;
 173 }
 174
 175 /* Helper function to do the ioctls needed for setup and init. */
 176 static boolean do_winsys_init(struct radeon_drm_winsys *ws)
 177 {
 178     struct drm_radeon_gem_info gem_info;
 179     int retval;
 180     drmVersionPtr version;
 181
 182     memset(&gem_info, 0, sizeof(gem_info));
 183
 184     /* We do things in a specific order here.
 185      *
 186      * DRM version first. We need to be sure we're running on a KMS chipset.
 187      * This is also for some features.
 188      *
 189      * Then, the PCI ID. This is essential and should return usable numbers
 190      * for all Radeons. If this fails, we probably got handed an FD for some
 191      * non-Radeon card.
 192      *
 193      * The GEM info is actually bogus on the kernel side, as well as our side
 194      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 195      * we don't actually use the info for anything yet.
 196      *
 197      * The GB and Z pipe requests should always succeed, but they might not
 198      * return sensical values for all chipsets, but that's alright because
 199      * the pipe drivers already know that.
 200      */
 201
 202     /* Get DRM version. */
 203     version = drmGetVersion(ws->fd);
 204     if (version->version_major != 2 ||
 205         version->version_minor < 3) {
 206         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 207                 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
 208                 __FUNCTION__,
 209                 version->version_major,
 210                 version->version_minor,
 211                 version->version_patchlevel);
 212         drmFreeVersion(version);
 213         return FALSE;
 214     }
 215
 216     ws->info.drm_major = version->version_major;
 217     ws->info.drm_minor = version->version_minor;
 218     ws->info.drm_patchlevel = version->version_patchlevel;
 219     drmFreeVersion(version);
 220
 221     /* Get PCI ID. */
 222     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 223                               &ws->info.pci_id))
 224         return FALSE;
 225
 226     /* Check PCI ID. */
 227     switch (ws->info.pci_id) {
 228 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 229 #include "pci_ids/r300_pci_ids.h"
 230 #undef CHIPSET
 231
 232 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 233 #include "pci_ids/r600_pci_ids.h"
 234 #undef CHIPSET
 235
 236 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 237 #include "pci_ids/radeonsi_pci_ids.h"
 238 #undef CHIPSET
 239
 240     default:
 241         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 242         return FALSE;
 243     }
 244
 245     switch (ws->info.family) {
 246     default:
 247     case CHIP_UNKNOWN:
 248         fprintf(stderr, "radeon: Unknown family.\n");
 249         return FALSE;
 250     case CHIP_R300:
 251     case CHIP_R350:
 252     case CHIP_RV350:
 253     case CHIP_RV370:
 254     case CHIP_RV380:
 255     case CHIP_RS400:
 256     case CHIP_RC410:
 257     case CHIP_RS480:
 258         ws->info.chip_class = R300;
 259         break;
 260     case CHIP_R420:     /* R4xx-based cores. */
 261     case CHIP_R423:
 262     case CHIP_R430:
 263     case CHIP_R480:
 264     case CHIP_R481:
 265     case CHIP_RV410:
 266     case CHIP_RS600:
 267     case CHIP_RS690:
 268     case CHIP_RS740:
 269         ws->info.chip_class = R400;
 270         break;
 271     case CHIP_RV515:    /* R5xx-based cores. */
 272     case CHIP_R520:
 273     case CHIP_RV530:
 274     case CHIP_R580:
 275     case CHIP_RV560:
 276     case CHIP_RV570:
 277         ws->info.chip_class = R500;
 278         break;
 279     case CHIP_R600:
 280     case CHIP_RV610:
 281     case CHIP_RV630:
 282     case CHIP_RV670:
 283     case CHIP_RV620:
 284     case CHIP_RV635:
 285     case CHIP_RS780:
 286     case CHIP_RS880:
 287         ws->info.chip_class = R600;
 288         break;
 289     case CHIP_RV770:
 290     case CHIP_RV730:
 291     case CHIP_RV710:
 292     case CHIP_RV740:
 293         ws->info.chip_class = R700;
 294         break;
 295     case CHIP_CEDAR:
 296     case CHIP_REDWOOD:
 297     case CHIP_JUNIPER:
 298     case CHIP_CYPRESS:
 299     case CHIP_HEMLOCK:
 300     case CHIP_PALM:
 301     case CHIP_SUMO:
 302     case CHIP_SUMO2:
 303     case CHIP_BARTS:
 304     case CHIP_TURKS:
 305     case CHIP_CAICOS:
 306         ws->info.chip_class = EVERGREEN;
 307         break;
 308     case CHIP_CAYMAN:
 309     case CHIP_ARUBA:
 310         ws->info.chip_class = CAYMAN;
 311         break;
 312     case CHIP_TAHITI:
 313     case CHIP_PITCAIRN:
 314     case CHIP_VERDE:
 315         ws->info.chip_class = TAHITI;
 316         break;
 317     }
 318
 319     /* Check for dma */
 320     ws->info.r600_has_dma = FALSE;
 321     if (ws->info.chip_class >= R700 && ws->info.drm_minor >= 27) {
 322         ws->info.r600_has_dma = TRUE;
 323     }
 324
 325     /* Get GEM info. */
 326     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 327             &gem_info, sizeof(gem_info));
 328     if (retval) {
 329         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 330                 retval);
 331         return FALSE;
 332     }
 333     ws->info.gart_size = gem_info.gart_size;
 334     ws->info.vram_size = gem_info.vram_size;
 335
 336     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 337
 338     /* Generation-specific queries. */
 339     if (ws->gen == DRV_R300) {
 340         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 341                                   "GB pipe count",
 342                                   &ws->info.r300_num_gb_pipes))
 343             return FALSE;
 344
 345         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 346                                   "Z pipe count",
 347                                   &ws->info.r300_num_z_pipes))
 348             return FALSE;
 349     }
 350     else if (ws->gen >= DRV_R600) {
 351         if (ws->info.drm_minor >= 9 &&
 352             !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 353                                   "num backends",
 354                                   &ws->info.r600_num_backends))
 355             return FALSE;
 356
 357         /* get the GPU counter frequency, failure is not fatal */
 358         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 359                              &ws->info.r600_clock_crystal_freq);
 360
 361         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 362                              &ws->info.r600_tiling_config);
 363
 364         if (ws->info.drm_minor >= 11) {
 365             radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 366                                  &ws->info.r600_num_tile_pipes);
 367
 368             if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 369                                       &ws->info.r600_backend_map))
 370                 ws->info.r600_backend_map_valid = TRUE;
 371         }
 372
 373         ws->info.r600_virtual_address = FALSE;
 374         if (ws->info.drm_minor >= 13) {
 375             ws->info.r600_virtual_address = TRUE;
 376             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 377                                       &ws->info.r600_va_start))
 378                 ws->info.r600_virtual_address = FALSE;
 379             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 380                                       &ws->info.r600_ib_vm_max_size))
 381                 ws->info.r600_virtual_address = FALSE;
 382         }
 383     }
 384
 385     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 386      * chips have at least 2 pipes, so we use 2 as a default. */
 387     ws->info.r600_max_pipes = 2;
 388     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 389                          &ws->info.r600_max_pipes);
 390
 391     return TRUE;
 392 }
 393
 394 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 395 {
 396     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 397
 398     if (ws->thread) {
 399         ws->kill_thread = 1;
 400         pipe_semaphore_signal(&ws->cs_queued);
 401         pipe_thread_wait(ws->thread);
 402     }
 403     pipe_semaphore_destroy(&ws->cs_queued);
 404     pipe_condvar_destroy(ws->cs_queue_empty);
 405
 406     if (!pipe_reference(&ws->base.reference, NULL)) {
 407         return;
 408     }
 409
 410     pipe_mutex_destroy(ws->hyperz_owner_mutex);
 411     pipe_mutex_destroy(ws->cmask_owner_mutex);
 412     pipe_mutex_destroy(ws->cs_stack_lock);
 413
 414     ws->cman->destroy(ws->cman);
 415     ws->kman->destroy(ws->kman);
 416     if (ws->gen >= DRV_R600) {
 417         radeon_surface_manager_free(ws->surf_man);
 418     }
 419     if (fd_tab) {
 420         util_hash_table_remove(fd_tab, intptr_to_pointer(ws->fd));
 421     }
 422     FREE(rws);
 423 }
 424
 425 static void radeon_query_info(struct radeon_winsys *rws,
 426                               struct radeon_info *info)
 427 {
 428     *info = ((struct radeon_drm_winsys *)rws)->info;
 429 }
 430
 431 static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 432                                          enum radeon_feature_id fid,
 433                                          boolean enable)
 434 {
 435     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 436
 437     switch (fid) {
 438     case RADEON_FID_R300_HYPERZ_ACCESS:
 439         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 440                                     &cs->ws->hyperz_owner_mutex,
 441                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 442                                     enable);
 443
 444     case RADEON_FID_R300_CMASK_ACCESS:
 445         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 446                                     &cs->ws->cmask_owner_mutex,
 447                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 448                                     enable);
 449     }
 450     return FALSE;
 451 }
 452
 453 static int radeon_drm_winsys_surface_init(struct radeon_winsys *rws,
 454                                           struct radeon_surface *surf)
 455 {
 456     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 457
 458     return radeon_surface_init(ws->surf_man, surf);
 459 }
 460
 461 static int radeon_drm_winsys_surface_best(struct radeon_winsys *rws,
 462                                           struct radeon_surface *surf)
 463 {
 464     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 465
 466     return radeon_surface_best(ws->surf_man, surf);
 467 }
 468
 469 static uint64_t radeon_query_timestamp(struct radeon_winsys *rws)
 470 {
 471     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 472     uint64_t ts = 0;
 473
 474     if (ws->info.drm_minor < 20 ||
 475         ws->gen < DRV_R600) {
 476         assert(0);
 477         return 0;
 478     }
 479
 480     radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 481                          (uint32_t*)&ts);
 482     return ts;
 483 }
 484
 485 static unsigned hash_fd(void *key)
 486 {
 487     return pointer_to_intptr(key);
 488 }
 489
 490 static int compare_fd(void *key1, void *key2)
 491 {
 492     return pointer_to_intptr(key1) != pointer_to_intptr(key2);
 493 }
 494
 495 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys *ws, struct radeon_drm_cs *cs)
 496 {
 497 retry:
 498     pipe_mutex_lock(ws->cs_stack_lock);
 499     if (p_atomic_read(&ws->ncs) >= RING_LAST) {
 500         /* no room left for a flush */
 501         pipe_mutex_unlock(ws->cs_stack_lock);
 502         goto retry;
 503     }
 504     ws->cs_stack[p_atomic_read(&ws->ncs)] = cs;
 505     p_atomic_inc(&ws->ncs);
 506     pipe_mutex_unlock(ws->cs_stack_lock);
 507     pipe_semaphore_signal(&ws->cs_queued);
 508 }
 509
 510 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param)
 511 {
 512     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys *)param;
 513     struct radeon_drm_cs *cs;
 514     unsigned i, empty_stack;
 515
 516     while (1) {
 517         pipe_semaphore_wait(&ws->cs_queued);
 518         if (ws->kill_thread)
 519             break;
 520 next:
 521         pipe_mutex_lock(ws->cs_stack_lock);
 522         cs = ws->cs_stack[0];
 523         pipe_mutex_unlock(ws->cs_stack_lock);
 524
 525         if (cs) {
 526             radeon_drm_cs_emit_ioctl_oneshot(cs->cst);
 527
 528             pipe_mutex_lock(ws->cs_stack_lock);
 529             for (i = 1; i < p_atomic_read(&ws->ncs); i++) {
 530                 ws->cs_stack[i - 1] = ws->cs_stack[i];
 531             }
 532             ws->cs_stack[p_atomic_read(&ws->ncs) - 1] = NULL;
 533             empty_stack = p_atomic_dec_zero(&ws->ncs);
 534             if (empty_stack) {
 535                 pipe_condvar_signal(ws->cs_queue_empty);
 536             }
 537             pipe_mutex_unlock(ws->cs_stack_lock);
 538
 539             pipe_semaphore_signal(&cs->flush_completed);
 540
 541             if (!empty_stack) {
 542                 goto next;
 543             }
 544         }
 545     }
 546     pipe_mutex_lock(ws->cs_stack_lock);
 547     for (i = 0; i < p_atomic_read(&ws->ncs); i++) {
 548         pipe_semaphore_signal(&ws->cs_stack[i]->flush_completed);
 549         ws->cs_stack[i] = NULL;
 550     }
 551     p_atomic_set(&ws->ncs, 0);
 552     pipe_condvar_signal(ws->cs_queue_empty);
 553     pipe_mutex_unlock(ws->cs_stack_lock);
 554     return NULL;
 555 }
 556
 557 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", TRUE)
 558 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param);
 559
 560 struct radeon_winsys *radeon_drm_winsys_create(int fd)
 561 {
 562     struct radeon_drm_winsys *ws;
 563
 564     if (!fd_tab) {
 565         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 566     }
 567
 568     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 569     if (ws) {
 570         pipe_reference(NULL, &ws->base.reference);
 571         return &ws->base;
 572     }
 573
 574     ws = CALLOC_STRUCT(radeon_drm_winsys);
 575     if (!ws) {
 576         return NULL;
 577     }
 578     ws->fd = fd;
 579     util_hash_table_set(fd_tab, intptr_to_pointer(fd), ws);
 580
 581     if (!do_winsys_init(ws))
 582         goto fail;
 583
 584     /* Create managers. */
 585     ws->kman = radeon_bomgr_create(ws);
 586     if (!ws->kman)
 587         goto fail;
 588     ws->cman = pb_cache_manager_create(ws->kman, 1000000);
 589     if (!ws->cman)
 590         goto fail;
 591
 592     if (ws->gen >= DRV_R600) {
 593         ws->surf_man = radeon_surface_manager_new(fd);
 594         if (!ws->surf_man)
 595             goto fail;
 596     }
 597
 598     /* init reference */
 599     pipe_reference_init(&ws->base.reference, 1);
 600
 601     /* Set functions. */
 602     ws->base.destroy = radeon_winsys_destroy;
 603     ws->base.query_info = radeon_query_info;
 604     ws->base.cs_request_feature = radeon_cs_request_feature;
 605     ws->base.surface_init = radeon_drm_winsys_surface_init;
 606     ws->base.surface_best = radeon_drm_winsys_surface_best;
 607     ws->base.query_timestamp = radeon_query_timestamp;
 608
 609     radeon_bomgr_init_functions(ws);
 610     radeon_drm_cs_init_functions(ws);
 611
 612     pipe_mutex_init(ws->hyperz_owner_mutex);
 613     pipe_mutex_init(ws->cmask_owner_mutex);
 614     pipe_mutex_init(ws->cs_stack_lock);
 615
 616     p_atomic_set(&ws->ncs, 0);
 617     pipe_semaphore_init(&ws->cs_queued, 0);
 618     pipe_condvar_init(ws->cs_queue_empty);
 619     if (ws->num_cpus > 1 && debug_get_option_thread())
 620         ws->thread = pipe_thread_create(radeon_drm_cs_emit_ioctl, ws);
 621
 622     return &ws->base;
 623
 624 fail:
 625     if (ws->cman)
 626         ws->cman->destroy(ws->cman);
 627     if (ws->kman)
 628         ws->kman->destroy(ws->kman);
 629     if (ws->surf_man)
 630         radeon_surface_manager_free(ws->surf_man);
 631     FREE(ws);
 632     return NULL;
 633 }