src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "pipebuffer/pb_bufmgr.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_hash_table.h"
  41
  42 #include <xf86drm.h>
  43 #include <stdio.h>
  44 #include <sys/types.h>
  45 #include <sys/stat.h>
  46 #include <unistd.h>
  47 #include <radeon_surface.h>
  48
  49 #ifndef RADEON_INFO_ACTIVE_CU_COUNT
  50 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
  51 #endif
  52
  53 #ifndef RADEON_INFO_CURRENT_GPU_TEMP
  54 #define RADEON_INFO_CURRENT_GPU_TEMP    0x21
  55 #define RADEON_INFO_CURRENT_GPU_SCLK    0x22
  56 #define RADEON_INFO_CURRENT_GPU_MCLK    0x23
  57 #define RADEON_INFO_READ_REG            0x24
  58 #endif
  59
  60 #define RADEON_INFO_VA_UNMAP_WORKING    0x25
  61
  62 static struct util_hash_table *fd_tab = NULL;
  63 pipe_static_mutex(fd_tab_mutex);
  64
  65 /* Enable/disable feature access for one command stream.
  66  * If enable == TRUE, return TRUE on success.
  67  * Otherwise, return FALSE.
  68  *
  69  * We basically do the same thing kernel does, because we have to deal
  70  * with multiple contexts (here command streams) backed by one winsys. */
  71 static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
  72                                     struct radeon_drm_cs **owner,
  73                                     pipe_mutex *mutex,
  74                                     unsigned request, const char *request_name,
  75                                     boolean enable)
  76 {
  77     struct drm_radeon_info info;
  78     unsigned value = enable ? 1 : 0;
  79
  80     memset(&info, 0, sizeof(info));
  81
  82     pipe_mutex_lock(*mutex);
  83
  84     /* Early exit if we are sure the request will fail. */
  85     if (enable) {
  86         if (*owner) {
  87             pipe_mutex_unlock(*mutex);
  88             return FALSE;
  89         }
  90     } else {
  91         if (*owner != applier) {
  92             pipe_mutex_unlock(*mutex);
  93             return FALSE;
  94         }
  95     }
  96
  97     /* Pass through the request to the kernel. */
  98     info.value = (unsigned long)&value;
  99     info.request = request;
 100     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
 101                             &info, sizeof(info)) != 0) {
 102         pipe_mutex_unlock(*mutex);
 103         return FALSE;
 104     }
 105
 106     /* Update the rights in the winsys. */
 107     if (enable) {
 108         if (value) {
 109             *owner = applier;
 110             pipe_mutex_unlock(*mutex);
 111             return TRUE;
 112         }
 113     } else {
 114         *owner = NULL;
 115     }
 116
 117     pipe_mutex_unlock(*mutex);
 118     return FALSE;
 119 }
 120
 121 static boolean radeon_get_drm_value(int fd, unsigned request,
 122                                     const char *errname, uint32_t *out)
 123 {
 124     struct drm_radeon_info info;
 125     int retval;
 126
 127     memset(&info, 0, sizeof(info));
 128
 129     info.value = (unsigned long)out;
 130     info.request = request;
 131
 132     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 133     if (retval) {
 134         if (errname) {
 135             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 136                     errname, retval);
 137         }
 138         return FALSE;
 139     }
 140     return TRUE;
 141 }
 142
 143 /* Helper function to do the ioctls needed for setup and init. */
 144 static boolean do_winsys_init(struct radeon_drm_winsys *ws)
 145 {
 146     struct drm_radeon_gem_info gem_info;
 147     int retval;
 148     drmVersionPtr version;
 149
 150     memset(&gem_info, 0, sizeof(gem_info));
 151
 152     /* We do things in a specific order here.
 153      *
 154      * DRM version first. We need to be sure we're running on a KMS chipset.
 155      * This is also for some features.
 156      *
 157      * Then, the PCI ID. This is essential and should return usable numbers
 158      * for all Radeons. If this fails, we probably got handed an FD for some
 159      * non-Radeon card.
 160      *
 161      * The GEM info is actually bogus on the kernel side, as well as our side
 162      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 163      * we don't actually use the info for anything yet.
 164      *
 165      * The GB and Z pipe requests should always succeed, but they might not
 166      * return sensical values for all chipsets, but that's alright because
 167      * the pipe drivers already know that.
 168      */
 169
 170     /* Get DRM version. */
 171     version = drmGetVersion(ws->fd);
 172     if (version->version_major != 2 ||
 173         version->version_minor < 3) {
 174         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 175                 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
 176                 __FUNCTION__,
 177                 version->version_major,
 178                 version->version_minor,
 179                 version->version_patchlevel);
 180         drmFreeVersion(version);
 181         return FALSE;
 182     }
 183
 184     ws->info.drm_major = version->version_major;
 185     ws->info.drm_minor = version->version_minor;
 186     ws->info.drm_patchlevel = version->version_patchlevel;
 187     drmFreeVersion(version);
 188
 189     /* Get PCI ID. */
 190     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 191                               &ws->info.pci_id))
 192         return FALSE;
 193
 194     /* Check PCI ID. */
 195     switch (ws->info.pci_id) {
 196 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 197 #include "pci_ids/r300_pci_ids.h"
 198 #undef CHIPSET
 199
 200 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 201 #include "pci_ids/r600_pci_ids.h"
 202 #undef CHIPSET
 203
 204 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 205 #include "pci_ids/radeonsi_pci_ids.h"
 206 #undef CHIPSET
 207
 208     default:
 209         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 210         return FALSE;
 211     }
 212
 213     switch (ws->info.family) {
 214     default:
 215     case CHIP_UNKNOWN:
 216         fprintf(stderr, "radeon: Unknown family.\n");
 217         return FALSE;
 218     case CHIP_R300:
 219     case CHIP_R350:
 220     case CHIP_RV350:
 221     case CHIP_RV370:
 222     case CHIP_RV380:
 223     case CHIP_RS400:
 224     case CHIP_RC410:
 225     case CHIP_RS480:
 226         ws->info.chip_class = R300;
 227         break;
 228     case CHIP_R420:     /* R4xx-based cores. */
 229     case CHIP_R423:
 230     case CHIP_R430:
 231     case CHIP_R480:
 232     case CHIP_R481:
 233     case CHIP_RV410:
 234     case CHIP_RS600:
 235     case CHIP_RS690:
 236     case CHIP_RS740:
 237         ws->info.chip_class = R400;
 238         break;
 239     case CHIP_RV515:    /* R5xx-based cores. */
 240     case CHIP_R520:
 241     case CHIP_RV530:
 242     case CHIP_R580:
 243     case CHIP_RV560:
 244     case CHIP_RV570:
 245         ws->info.chip_class = R500;
 246         break;
 247     case CHIP_R600:
 248     case CHIP_RV610:
 249     case CHIP_RV630:
 250     case CHIP_RV670:
 251     case CHIP_RV620:
 252     case CHIP_RV635:
 253     case CHIP_RS780:
 254     case CHIP_RS880:
 255         ws->info.chip_class = R600;
 256         break;
 257     case CHIP_RV770:
 258     case CHIP_RV730:
 259     case CHIP_RV710:
 260     case CHIP_RV740:
 261         ws->info.chip_class = R700;
 262         break;
 263     case CHIP_CEDAR:
 264     case CHIP_REDWOOD:
 265     case CHIP_JUNIPER:
 266     case CHIP_CYPRESS:
 267     case CHIP_HEMLOCK:
 268     case CHIP_PALM:
 269     case CHIP_SUMO:
 270     case CHIP_SUMO2:
 271     case CHIP_BARTS:
 272     case CHIP_TURKS:
 273     case CHIP_CAICOS:
 274         ws->info.chip_class = EVERGREEN;
 275         break;
 276     case CHIP_CAYMAN:
 277     case CHIP_ARUBA:
 278         ws->info.chip_class = CAYMAN;
 279         break;
 280     case CHIP_TAHITI:
 281     case CHIP_PITCAIRN:
 282     case CHIP_VERDE:
 283     case CHIP_OLAND:
 284     case CHIP_HAINAN:
 285         ws->info.chip_class = SI;
 286         break;
 287     case CHIP_BONAIRE:
 288     case CHIP_KAVERI:
 289     case CHIP_KABINI:
 290     case CHIP_HAWAII:
 291     case CHIP_MULLINS:
 292         ws->info.chip_class = CIK;
 293         break;
 294     }
 295
 296     /* Check for dma */
 297     ws->info.r600_has_dma = FALSE;
 298     /* DMA is disabled on R700. There is IB corruption and hangs. */
 299     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 300         ws->info.r600_has_dma = TRUE;
 301     }
 302
 303     /* Check for UVD and VCE */
 304     ws->info.has_uvd = FALSE;
 305     ws->info.vce_fw_version = 0x00000000;
 306     if (ws->info.drm_minor >= 32) {
 307         uint32_t value = RADEON_CS_RING_UVD;
 308         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 309                                  "UVD Ring working", &value))
 310             ws->info.has_uvd = value;
 311
 312         value = RADEON_CS_RING_VCE;
 313         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 314                                  NULL, &value) && value) {
 315
 316             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 317                                      "VCE FW version", &value))
 318                 ws->info.vce_fw_version = value;
 319         }
 320     }
 321
 322     /* Check for userptr support. */
 323     {
 324         struct drm_radeon_gem_userptr args = {0};
 325
 326         /* If the ioctl doesn't exist, -EINVAL is returned.
 327          *
 328          * If the ioctl exists, it should return -EACCES
 329          * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
 330          * aren't set.
 331          */
 332         ws->info.has_userptr =
 333             drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
 334                                 &args, sizeof(args)) == -EACCES;
 335     }
 336
 337     /* Get GEM info. */
 338     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 339             &gem_info, sizeof(gem_info));
 340     if (retval) {
 341         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 342                 retval);
 343         return FALSE;
 344     }
 345     ws->info.gart_size = gem_info.gart_size;
 346     ws->info.vram_size = gem_info.vram_size;
 347
 348     /* Get max clock frequency info and convert it to MHz */
 349     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 350                          &ws->info.max_sclk);
 351     ws->info.max_sclk /= 1000;
 352
 353     radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
 354                          &ws->info.si_backend_enabled_mask);
 355
 356     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 357
 358     /* Generation-specific queries. */
 359     if (ws->gen == DRV_R300) {
 360         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 361                                   "GB pipe count",
 362                                   &ws->info.r300_num_gb_pipes))
 363             return FALSE;
 364
 365         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 366                                   "Z pipe count",
 367                                   &ws->info.r300_num_z_pipes))
 368             return FALSE;
 369     }
 370     else if (ws->gen >= DRV_R600) {
 371         if (ws->info.drm_minor >= 9 &&
 372             !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 373                                   "num backends",
 374                                   &ws->info.r600_num_backends))
 375             return FALSE;
 376
 377         /* get the GPU counter frequency, failure is not fatal */
 378         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 379                              &ws->info.r600_clock_crystal_freq);
 380
 381         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 382                              &ws->info.r600_tiling_config);
 383
 384         if (ws->info.drm_minor >= 11) {
 385             radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 386                                  &ws->info.r600_num_tile_pipes);
 387
 388             if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 389                                       &ws->info.r600_backend_map))
 390                 ws->info.r600_backend_map_valid = TRUE;
 391         }
 392
 393         ws->info.r600_virtual_address = FALSE;
 394         if (ws->info.drm_minor >= 13) {
 395             uint32_t ib_vm_max_size;
 396
 397             ws->info.r600_virtual_address = TRUE;
 398             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 399                                       &ws->va_start))
 400                 ws->info.r600_virtual_address = FALSE;
 401             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 402                                       &ib_vm_max_size))
 403                 ws->info.r600_virtual_address = FALSE;
 404             radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
 405                                  &ws->va_unmap_working);
 406         }
 407         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", FALSE))
 408                 ws->info.r600_virtual_address = FALSE;
 409     }
 410
 411     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 412      * chips have at least 2 pipes, so we use 2 as a default. */
 413     ws->info.r600_max_pipes = 2;
 414     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 415                          &ws->info.r600_max_pipes);
 416
 417     /* All GPUs have at least one compute unit */
 418     ws->info.max_compute_units = 1;
 419     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 420                          &ws->info.max_compute_units);
 421
 422     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 423                          &ws->info.max_se);
 424
 425     if (!ws->info.max_se) {
 426         switch (ws->info.family) {
 427         default:
 428             ws->info.max_se = 1;
 429             break;
 430         case CHIP_CYPRESS:
 431         case CHIP_HEMLOCK:
 432         case CHIP_BARTS:
 433         case CHIP_CAYMAN:
 434         case CHIP_TAHITI:
 435         case CHIP_PITCAIRN:
 436         case CHIP_BONAIRE:
 437             ws->info.max_se = 2;
 438             break;
 439         case CHIP_HAWAII:
 440             ws->info.max_se = 4;
 441             break;
 442         }
 443     }
 444
 445     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 446                          &ws->info.max_sh_per_se);
 447
 448     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 449                          &ws->accel_working2);
 450     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 451         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 452                 "returned accel_working2 value %u is smaller than 2. "
 453                 "Please install a newer kernel.\n",
 454                 ws->accel_working2);
 455         return FALSE;
 456     }
 457
 458     if (radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 459                              ws->info.si_tile_mode_array)) {
 460         ws->info.si_tile_mode_array_valid = TRUE;
 461     }
 462
 463     if (radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 464                              ws->info.cik_macrotile_mode_array)) {
 465         ws->info.cik_macrotile_mode_array_valid = TRUE;
 466     }
 467
 468     return TRUE;
 469 }
 470
 471 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 472 {
 473     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 474
 475     if (ws->thread) {
 476         ws->kill_thread = 1;
 477         pipe_semaphore_signal(&ws->cs_queued);
 478         pipe_thread_wait(ws->thread);
 479     }
 480     pipe_semaphore_destroy(&ws->cs_queued);
 481
 482     pipe_mutex_destroy(ws->hyperz_owner_mutex);
 483     pipe_mutex_destroy(ws->cmask_owner_mutex);
 484     pipe_mutex_destroy(ws->cs_stack_lock);
 485
 486     ws->cman->destroy(ws->cman);
 487     ws->kman->destroy(ws->kman);
 488     if (ws->gen >= DRV_R600) {
 489         radeon_surface_manager_free(ws->surf_man);
 490     }
 491     FREE(rws);
 492 }
 493
 494 static void radeon_query_info(struct radeon_winsys *rws,
 495                               struct radeon_info *info)
 496 {
 497     *info = ((struct radeon_drm_winsys *)rws)->info;
 498 }
 499
 500 static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 501                                          enum radeon_feature_id fid,
 502                                          boolean enable)
 503 {
 504     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 505
 506     switch (fid) {
 507     case RADEON_FID_R300_HYPERZ_ACCESS:
 508         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 509                                     &cs->ws->hyperz_owner_mutex,
 510                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 511                                     enable);
 512
 513     case RADEON_FID_R300_CMASK_ACCESS:
 514         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 515                                     &cs->ws->cmask_owner_mutex,
 516                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 517                                     enable);
 518     }
 519     return FALSE;
 520 }
 521
 522 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 523                                    enum radeon_value_id value)
 524 {
 525     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 526     uint64_t retval = 0;
 527
 528     switch (value) {
 529     case RADEON_REQUESTED_VRAM_MEMORY:
 530         return ws->allocated_vram;
 531     case RADEON_REQUESTED_GTT_MEMORY:
 532         return ws->allocated_gtt;
 533     case RADEON_BUFFER_WAIT_TIME_NS:
 534         return ws->buffer_wait_time;
 535     case RADEON_TIMESTAMP:
 536         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 537             assert(0);
 538             return 0;
 539         }
 540
 541         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 542                              (uint32_t*)&retval);
 543         return retval;
 544     case RADEON_NUM_CS_FLUSHES:
 545         return ws->num_cs_flushes;
 546     case RADEON_NUM_BYTES_MOVED:
 547         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 548                              "num-bytes-moved", (uint32_t*)&retval);
 549         return retval;
 550     case RADEON_VRAM_USAGE:
 551         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 552                              "vram-usage", (uint32_t*)&retval);
 553         return retval;
 554     case RADEON_GTT_USAGE:
 555         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 556                              "gtt-usage", (uint32_t*)&retval);
 557         return retval;
 558     case RADEON_GPU_TEMPERATURE:
 559         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
 560                              "gpu-temp", (uint32_t*)&retval);
 561         return retval;
 562     case RADEON_CURRENT_SCLK:
 563         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
 564                              "current-gpu-sclk", (uint32_t*)&retval);
 565         return retval;
 566     case RADEON_CURRENT_MCLK:
 567         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
 568                              "current-gpu-mclk", (uint32_t*)&retval);
 569         return retval;
 570     }
 571     return 0;
 572 }
 573
 574 static void radeon_read_registers(struct radeon_winsys *rws,
 575                                   unsigned reg_offset,
 576                                   unsigned num_registers, uint32_t *out)
 577 {
 578     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 579     unsigned i;
 580
 581     for (i = 0; i < num_registers; i++) {
 582         uint32_t reg = reg_offset + i*4;
 583
 584         radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, "read-reg", &reg);
 585         out[i] = reg;
 586     }
 587 }
 588
 589 static unsigned hash_fd(void *key)
 590 {
 591     int fd = pointer_to_intptr(key);
 592     struct stat stat;
 593     fstat(fd, &stat);
 594
 595     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 596 }
 597
 598 static int compare_fd(void *key1, void *key2)
 599 {
 600     int fd1 = pointer_to_intptr(key1);
 601     int fd2 = pointer_to_intptr(key2);
 602     struct stat stat1, stat2;
 603     fstat(fd1, &stat1);
 604     fstat(fd2, &stat2);
 605
 606     return stat1.st_dev != stat2.st_dev ||
 607            stat1.st_ino != stat2.st_ino ||
 608            stat1.st_rdev != stat2.st_rdev;
 609 }
 610
 611 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys *ws, struct radeon_drm_cs *cs)
 612 {
 613 retry:
 614     pipe_mutex_lock(ws->cs_stack_lock);
 615     if (ws->ncs >= RING_LAST) {
 616         /* no room left for a flush */
 617         pipe_mutex_unlock(ws->cs_stack_lock);
 618         goto retry;
 619     }
 620     ws->cs_stack[ws->ncs++] = cs;
 621     pipe_mutex_unlock(ws->cs_stack_lock);
 622     pipe_semaphore_signal(&ws->cs_queued);
 623 }
 624
 625 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param)
 626 {
 627     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys *)param;
 628     struct radeon_drm_cs *cs;
 629     unsigned i;
 630
 631     while (1) {
 632         pipe_semaphore_wait(&ws->cs_queued);
 633         if (ws->kill_thread)
 634             break;
 635
 636         pipe_mutex_lock(ws->cs_stack_lock);
 637         cs = ws->cs_stack[0];
 638         for (i = 1; i < ws->ncs; i++)
 639             ws->cs_stack[i - 1] = ws->cs_stack[i];
 640         ws->cs_stack[--ws->ncs] = NULL;
 641         pipe_mutex_unlock(ws->cs_stack_lock);
 642
 643         if (cs) {
 644             radeon_drm_cs_emit_ioctl_oneshot(cs, cs->cst);
 645             pipe_semaphore_signal(&cs->flush_completed);
 646         }
 647     }
 648     pipe_mutex_lock(ws->cs_stack_lock);
 649     for (i = 0; i < ws->ncs; i++) {
 650         pipe_semaphore_signal(&ws->cs_stack[i]->flush_completed);
 651         ws->cs_stack[i] = NULL;
 652     }
 653     ws->ncs = 0;
 654     pipe_mutex_unlock(ws->cs_stack_lock);
 655     return 0;
 656 }
 657
 658 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", TRUE)
 659 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param);
 660
 661 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 662 {
 663     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 664     bool destroy;
 665
 666     /* When the reference counter drops to zero, remove the fd from the table.
 667      * This must happen while the mutex is locked, so that
 668      * radeon_drm_winsys_create in another thread doesn't get the winsys
 669      * from the table when the counter drops to 0. */
 670     pipe_mutex_lock(fd_tab_mutex);
 671
 672     destroy = pipe_reference(&rws->reference, NULL);
 673     if (destroy && fd_tab)
 674         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 675
 676     pipe_mutex_unlock(fd_tab_mutex);
 677     return destroy;
 678 }
 679
 680 PUBLIC struct radeon_winsys *
 681 radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
 682 {
 683     struct radeon_drm_winsys *ws;
 684
 685     pipe_mutex_lock(fd_tab_mutex);
 686     if (!fd_tab) {
 687         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 688     }
 689
 690     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 691     if (ws) {
 692         pipe_reference(NULL, &ws->reference);
 693         pipe_mutex_unlock(fd_tab_mutex);
 694         return &ws->base;
 695     }
 696
 697     ws = CALLOC_STRUCT(radeon_drm_winsys);
 698     if (!ws) {
 699         pipe_mutex_unlock(fd_tab_mutex);
 700         return NULL;
 701     }
 702
 703     ws->fd = fd;
 704
 705     if (!do_winsys_init(ws))
 706         goto fail;
 707
 708     /* Create managers. */
 709     ws->kman = radeon_bomgr_create(ws);
 710     if (!ws->kman)
 711         goto fail;
 712
 713     ws->cman = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0,
 714                                        MIN2(ws->info.vram_size, ws->info.gart_size));
 715     if (!ws->cman)
 716         goto fail;
 717
 718     if (ws->gen >= DRV_R600) {
 719         ws->surf_man = radeon_surface_manager_new(fd);
 720         if (!ws->surf_man)
 721             goto fail;
 722     }
 723
 724     /* init reference */
 725     pipe_reference_init(&ws->reference, 1);
 726
 727     /* Set functions. */
 728     ws->base.unref = radeon_winsys_unref;
 729     ws->base.destroy = radeon_winsys_destroy;
 730     ws->base.query_info = radeon_query_info;
 731     ws->base.cs_request_feature = radeon_cs_request_feature;
 732     ws->base.query_value = radeon_query_value;
 733     ws->base.read_registers = radeon_read_registers;
 734
 735     radeon_bomgr_init_functions(ws);
 736     radeon_drm_cs_init_functions(ws);
 737     radeon_surface_init_functions(ws);
 738
 739     pipe_mutex_init(ws->hyperz_owner_mutex);
 740     pipe_mutex_init(ws->cmask_owner_mutex);
 741     pipe_mutex_init(ws->cs_stack_lock);
 742
 743     ws->ncs = 0;
 744     pipe_semaphore_init(&ws->cs_queued, 0);
 745     if (ws->num_cpus > 1 && debug_get_option_thread())
 746         ws->thread = pipe_thread_create(radeon_drm_cs_emit_ioctl, ws);
 747
 748     /* Create the screen at the end. The winsys must be initialized
 749      * completely.
 750      *
 751      * Alternatively, we could create the screen based on "ws->gen"
 752      * and link all drivers into one binary blob. */
 753     ws->base.screen = screen_create(&ws->base);
 754     if (!ws->base.screen) {
 755         radeon_winsys_destroy(&ws->base);
 756         pipe_mutex_unlock(fd_tab_mutex);
 757         return NULL;
 758     }
 759
 760     util_hash_table_set(fd_tab, intptr_to_pointer(fd), ws);
 761
 762     /* We must unlock the mutex once the winsys is fully initialized, so that
 763      * other threads attempting to create the winsys from the same fd will
 764      * get a fully initialized winsys and not just half-way initialized. */
 765     pipe_mutex_unlock(fd_tab_mutex);
 766
 767     return &ws->base;
 768
 769 fail:
 770     pipe_mutex_unlock(fd_tab_mutex);
 771     if (ws->cman)
 772         ws->cman->destroy(ws->cman);
 773     if (ws->kman)
 774         ws->kman->destroy(ws->kman);
 775     if (ws->surf_man)
 776         radeon_surface_manager_free(ws->surf_man);
 777     FREE(ws);
 778     return NULL;
 779 }