src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 #include "radeon_drm_bo.h"
  29 #include "radeon_drm_cs.h"
  30 #include "radeon_drm_public.h"
  31
  32 #include "util/u_memory.h"
  33 #include "util/u_hash_table.h"
  34
  35 #include <xf86drm.h>
  36 #include <stdio.h>
  37 #include <sys/types.h>
  38 #include <sys/stat.h>
  39 #include <unistd.h>
  40 #include <fcntl.h>
  41 #include <radeon_surface.h>
  42
  43 static struct util_hash_table *fd_tab = NULL;
  44 static mtx_t fd_tab_mutex = _MTX_INITIALIZER_NP;
  45
  46 /* Enable/disable feature access for one command stream.
  47  * If enable == true, return true on success.
  48  * Otherwise, return false.
  49  *
  50  * We basically do the same thing kernel does, because we have to deal
  51  * with multiple contexts (here command streams) backed by one winsys. */
  52 static bool radeon_set_fd_access(struct radeon_drm_cs *applier,
  53                                  struct radeon_drm_cs **owner,
  54                                  mtx_t *mutex,
  55                                  unsigned request, const char *request_name,
  56                                  bool enable)
  57 {
  58     struct drm_radeon_info info;
  59     unsigned value = enable ? 1 : 0;
  60
  61     memset(&info, 0, sizeof(info));
  62
  63     mtx_lock(&*mutex);
  64
  65     /* Early exit if we are sure the request will fail. */
  66     if (enable) {
  67         if (*owner) {
  68             mtx_unlock(&*mutex);
  69             return false;
  70         }
  71     } else {
  72         if (*owner != applier) {
  73             mtx_unlock(&*mutex);
  74             return false;
  75         }
  76     }
  77
  78     /* Pass through the request to the kernel. */
  79     info.value = (unsigned long)&value;
  80     info.request = request;
  81     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
  82                             &info, sizeof(info)) != 0) {
  83         mtx_unlock(&*mutex);
  84         return false;
  85     }
  86
  87     /* Update the rights in the winsys. */
  88     if (enable) {
  89         if (value) {
  90             *owner = applier;
  91             mtx_unlock(&*mutex);
  92             return true;
  93         }
  94     } else {
  95         *owner = NULL;
  96     }
  97
  98     mtx_unlock(&*mutex);
  99     return false;
 100 }
 101
 102 static bool radeon_get_drm_value(int fd, unsigned request,
 103                                  const char *errname, uint32_t *out)
 104 {
 105     struct drm_radeon_info info;
 106     int retval;
 107
 108     memset(&info, 0, sizeof(info));
 109
 110     info.value = (unsigned long)out;
 111     info.request = request;
 112
 113     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 114     if (retval) {
 115         if (errname) {
 116             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 117                     errname, retval);
 118         }
 119         return false;
 120     }
 121     return true;
 122 }
 123
 124 /* Helper function to do the ioctls needed for setup and init. */
 125 static bool do_winsys_init(struct radeon_drm_winsys *ws)
 126 {
 127     struct drm_radeon_gem_info gem_info;
 128     int retval;
 129     drmVersionPtr version;
 130
 131     memset(&gem_info, 0, sizeof(gem_info));
 132
 133     /* We do things in a specific order here.
 134      *
 135      * DRM version first. We need to be sure we're running on a KMS chipset.
 136      * This is also for some features.
 137      *
 138      * Then, the PCI ID. This is essential and should return usable numbers
 139      * for all Radeons. If this fails, we probably got handed an FD for some
 140      * non-Radeon card.
 141      *
 142      * The GEM info is actually bogus on the kernel side, as well as our side
 143      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 144      * we don't actually use the info for anything yet.
 145      *
 146      * The GB and Z pipe requests should always succeed, but they might not
 147      * return sensical values for all chipsets, but that's alright because
 148      * the pipe drivers already know that.
 149      */
 150
 151     /* Get DRM version. */
 152     version = drmGetVersion(ws->fd);
 153     if (version->version_major != 2 ||
 154         version->version_minor < 12) {
 155         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 156                 "only compatible with 2.12.0 (kernel 3.2) or later.\n",
 157                 __FUNCTION__,
 158                 version->version_major,
 159                 version->version_minor,
 160                 version->version_patchlevel);
 161         drmFreeVersion(version);
 162         return false;
 163     }
 164
 165     ws->info.drm_major = version->version_major;
 166     ws->info.drm_minor = version->version_minor;
 167     ws->info.drm_patchlevel = version->version_patchlevel;
 168     drmFreeVersion(version);
 169
 170     /* Get PCI ID. */
 171     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 172                               &ws->info.pci_id))
 173         return false;
 174
 175     /* Check PCI ID. */
 176     switch (ws->info.pci_id) {
 177 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 178 #include "pci_ids/r300_pci_ids.h"
 179 #undef CHIPSET
 180
 181 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 182 #include "pci_ids/r600_pci_ids.h"
 183 #undef CHIPSET
 184
 185 #define CHIPSET(pci_id, cfamily) \
 186     case pci_id: \
 187         ws->info.family = CHIP_##cfamily; \
 188         ws->info.name = #cfamily; \
 189         ws->gen = DRV_SI; \
 190         break;
 191 #include "pci_ids/radeonsi_pci_ids.h"
 192 #undef CHIPSET
 193
 194     default:
 195         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 196         return false;
 197     }
 198
 199     switch (ws->info.family) {
 200     default:
 201     case CHIP_UNKNOWN:
 202         fprintf(stderr, "radeon: Unknown family.\n");
 203         return false;
 204     case CHIP_R300:
 205     case CHIP_R350:
 206     case CHIP_RV350:
 207     case CHIP_RV370:
 208     case CHIP_RV380:
 209     case CHIP_RS400:
 210     case CHIP_RC410:
 211     case CHIP_RS480:
 212         ws->info.chip_class = R300;
 213         break;
 214     case CHIP_R420:     /* R4xx-based cores. */
 215     case CHIP_R423:
 216     case CHIP_R430:
 217     case CHIP_R480:
 218     case CHIP_R481:
 219     case CHIP_RV410:
 220     case CHIP_RS600:
 221     case CHIP_RS690:
 222     case CHIP_RS740:
 223         ws->info.chip_class = R400;
 224         break;
 225     case CHIP_RV515:    /* R5xx-based cores. */
 226     case CHIP_R520:
 227     case CHIP_RV530:
 228     case CHIP_R580:
 229     case CHIP_RV560:
 230     case CHIP_RV570:
 231         ws->info.chip_class = R500;
 232         break;
 233     case CHIP_R600:
 234     case CHIP_RV610:
 235     case CHIP_RV630:
 236     case CHIP_RV670:
 237     case CHIP_RV620:
 238     case CHIP_RV635:
 239     case CHIP_RS780:
 240     case CHIP_RS880:
 241         ws->info.chip_class = R600;
 242         break;
 243     case CHIP_RV770:
 244     case CHIP_RV730:
 245     case CHIP_RV710:
 246     case CHIP_RV740:
 247         ws->info.chip_class = R700;
 248         break;
 249     case CHIP_CEDAR:
 250     case CHIP_REDWOOD:
 251     case CHIP_JUNIPER:
 252     case CHIP_CYPRESS:
 253     case CHIP_HEMLOCK:
 254     case CHIP_PALM:
 255     case CHIP_SUMO:
 256     case CHIP_SUMO2:
 257     case CHIP_BARTS:
 258     case CHIP_TURKS:
 259     case CHIP_CAICOS:
 260         ws->info.chip_class = EVERGREEN;
 261         break;
 262     case CHIP_CAYMAN:
 263     case CHIP_ARUBA:
 264         ws->info.chip_class = CAYMAN;
 265         break;
 266     case CHIP_TAHITI:
 267     case CHIP_PITCAIRN:
 268     case CHIP_VERDE:
 269     case CHIP_OLAND:
 270     case CHIP_HAINAN:
 271         ws->info.chip_class = SI;
 272         break;
 273     case CHIP_BONAIRE:
 274     case CHIP_KAVERI:
 275     case CHIP_KABINI:
 276     case CHIP_HAWAII:
 277     case CHIP_MULLINS:
 278         ws->info.chip_class = CIK;
 279         break;
 280     }
 281
 282     /* Set which chips don't have dedicated VRAM. */
 283     switch (ws->info.family) {
 284     case CHIP_RS400:
 285     case CHIP_RC410:
 286     case CHIP_RS480:
 287     case CHIP_RS600:
 288     case CHIP_RS690:
 289     case CHIP_RS740:
 290     case CHIP_RS780:
 291     case CHIP_RS880:
 292     case CHIP_PALM:
 293     case CHIP_SUMO:
 294     case CHIP_SUMO2:
 295     case CHIP_ARUBA:
 296     case CHIP_KAVERI:
 297     case CHIP_KABINI:
 298     case CHIP_MULLINS:
 299        ws->info.has_dedicated_vram = false;
 300        break;
 301
 302     default:
 303        ws->info.has_dedicated_vram = true;
 304     }
 305
 306     /* Check for dma */
 307     ws->info.num_sdma_rings = 0;
 308     /* DMA is disabled on R700. There is IB corruption and hangs. */
 309     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 310         ws->info.num_sdma_rings = 1;
 311     }
 312
 313     /* Check for UVD and VCE */
 314     ws->info.has_hw_decode = false;
 315     ws->info.vce_fw_version = 0x00000000;
 316     if (ws->info.drm_minor >= 32) {
 317         uint32_t value = RADEON_CS_RING_UVD;
 318         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 319                                  "UVD Ring working", &value))
 320             ws->info.has_hw_decode = value;
 321
 322         value = RADEON_CS_RING_VCE;
 323         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 324                                  NULL, &value) && value) {
 325
 326             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 327                                      "VCE FW version", &value))
 328                 ws->info.vce_fw_version = value;
 329         }
 330     }
 331
 332     /* Check for userptr support. */
 333     {
 334         struct drm_radeon_gem_userptr args = {0};
 335
 336         /* If the ioctl doesn't exist, -EINVAL is returned.
 337          *
 338          * If the ioctl exists, it should return -EACCES
 339          * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
 340          * aren't set.
 341          */
 342         ws->info.has_userptr =
 343             drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
 344                                 &args, sizeof(args)) == -EACCES;
 345     }
 346
 347     /* Get GEM info. */
 348     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 349             &gem_info, sizeof(gem_info));
 350     if (retval) {
 351         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 352                 retval);
 353         return false;
 354     }
 355     ws->info.gart_size = gem_info.gart_size;
 356     ws->info.vram_size = gem_info.vram_size;
 357     ws->info.vram_vis_size = gem_info.vram_visible;
 358     /* Older versions of the kernel driver reported incorrect values, and
 359      * didn't support more than 256MB of visible VRAM anyway
 360      */
 361     if (ws->info.drm_minor < 49)
 362         ws->info.vram_vis_size = MIN2(ws->info.vram_vis_size, 256*1024*1024);
 363
 364     /* Radeon allocates all buffers as contigous, which makes large allocations
 365      * unlikely to succeed. */
 366     ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 0.7;
 367     if (ws->info.has_dedicated_vram)
 368         ws->info.max_alloc_size = MIN2(ws->info.vram_size * 0.7, ws->info.max_alloc_size);
 369     if (ws->info.drm_minor < 40)
 370         ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
 371     /* Both 32-bit and 64-bit address spaces only have 4GB. */
 372     ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 3ull*1024*1024*1024);
 373
 374     /* Get max clock frequency info and convert it to MHz */
 375     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 376                          &ws->info.max_shader_clock);
 377     ws->info.max_shader_clock /= 1000;
 378
 379     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 380
 381     /* Generation-specific queries. */
 382     if (ws->gen == DRV_R300) {
 383         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 384                                   "GB pipe count",
 385                                   &ws->info.r300_num_gb_pipes))
 386             return false;
 387
 388         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 389                                   "Z pipe count",
 390                                   &ws->info.r300_num_z_pipes))
 391             return false;
 392     }
 393     else if (ws->gen >= DRV_R600) {
 394         uint32_t tiling_config = 0;
 395
 396         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 397                                   "num backends",
 398                                   &ws->info.num_render_backends))
 399             return false;
 400
 401         /* get the GPU counter frequency, failure is not fatal */
 402         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 403                              &ws->info.clock_crystal_freq);
 404
 405         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 406                              &tiling_config);
 407
 408         ws->info.r600_num_banks =
 409             ws->info.chip_class >= EVERGREEN ?
 410                 4 << ((tiling_config & 0xf0) >> 4) :
 411                 4 << ((tiling_config & 0x30) >> 4);
 412
 413         ws->info.pipe_interleave_bytes =
 414             ws->info.chip_class >= EVERGREEN ?
 415                 256 << ((tiling_config & 0xf00) >> 8) :
 416                 256 << ((tiling_config & 0xc0) >> 6);
 417
 418         if (!ws->info.pipe_interleave_bytes)
 419             ws->info.pipe_interleave_bytes =
 420                 ws->info.chip_class >= EVERGREEN ? 512 : 256;
 421
 422         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 423                              &ws->info.num_tile_pipes);
 424
 425         /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
 426          * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
 427          * reports a different value (12). Fix it by setting what's in the
 428          * GB_TILE_MODE array (8).
 429          */
 430         if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
 431             ws->info.num_tile_pipes = 8;
 432
 433         if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 434                                   &ws->info.r600_gb_backend_map))
 435             ws->info.r600_gb_backend_map_valid = true;
 436
 437         /* Default value. */
 438         ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.num_render_backends);
 439         /*
 440          * This fails (silently) on non-GCN or older kernels, overwriting the
 441          * default enabled_rb_mask with the result of the last query.
 442         */
 443         if (ws->gen >= DRV_SI)
 444             radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
 445                                  &ws->info.enabled_rb_mask);
 446
 447         ws->info.r600_has_virtual_memory = false;
 448         if (ws->info.drm_minor >= 13) {
 449             uint32_t ib_vm_max_size;
 450
 451             ws->info.r600_has_virtual_memory = true;
 452             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 453                                       &ws->va_start))
 454                 ws->info.r600_has_virtual_memory = false;
 455             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 456                                       &ib_vm_max_size))
 457                 ws->info.r600_has_virtual_memory = false;
 458             radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
 459                                  &ws->va_unmap_working);
 460         }
 461         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false))
 462                 ws->info.r600_has_virtual_memory = false;
 463     }
 464
 465     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 466      * chips have at least 2 pipes, so we use 2 as a default. */
 467     ws->info.r600_max_quad_pipes = 2;
 468     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 469                          &ws->info.r600_max_quad_pipes);
 470
 471     /* All GPUs have at least one compute unit */
 472     ws->info.num_good_compute_units = 1;
 473     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 474                          &ws->info.num_good_compute_units);
 475
 476     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 477                          &ws->info.max_se);
 478
 479     switch (ws->info.family) {
 480     case CHIP_HAINAN:
 481     case CHIP_KABINI:
 482     case CHIP_MULLINS:
 483         ws->info.num_tcc_blocks = 2;
 484         break;
 485     case CHIP_VERDE:
 486     case CHIP_OLAND:
 487     case CHIP_BONAIRE:
 488     case CHIP_KAVERI:
 489         ws->info.num_tcc_blocks = 4;
 490         break;
 491     case CHIP_PITCAIRN:
 492         ws->info.num_tcc_blocks = 8;
 493         break;
 494     case CHIP_TAHITI:
 495         ws->info.num_tcc_blocks = 12;
 496         break;
 497     case CHIP_HAWAII:
 498         ws->info.num_tcc_blocks = 16;
 499         break;
 500     default:
 501         ws->info.num_tcc_blocks = 0;
 502         break;
 503     }
 504
 505     if (!ws->info.max_se) {
 506         switch (ws->info.family) {
 507         default:
 508             ws->info.max_se = 1;
 509             break;
 510         case CHIP_CYPRESS:
 511         case CHIP_HEMLOCK:
 512         case CHIP_BARTS:
 513         case CHIP_CAYMAN:
 514         case CHIP_TAHITI:
 515         case CHIP_PITCAIRN:
 516         case CHIP_BONAIRE:
 517             ws->info.max_se = 2;
 518             break;
 519         case CHIP_HAWAII:
 520             ws->info.max_se = 4;
 521             break;
 522         }
 523     }
 524
 525     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 526                          &ws->info.max_sh_per_se);
 527
 528     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 529                          &ws->accel_working2);
 530     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 531         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 532                 "returned accel_working2 value %u is smaller than 2. "
 533                 "Please install a newer kernel.\n",
 534                 ws->accel_working2);
 535         return false;
 536     }
 537
 538     if (ws->info.chip_class == CIK) {
 539         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 540                                   ws->info.cik_macrotile_mode_array)) {
 541             fprintf(stderr, "radeon: Kernel 3.13 is required for CIK support.\n");
 542             return false;
 543         }
 544     }
 545
 546     if (ws->info.chip_class >= SI) {
 547         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 548                                   ws->info.si_tile_mode_array)) {
 549             fprintf(stderr, "radeon: Kernel 3.10 is required for SI support.\n");
 550             return false;
 551         }
 552     }
 553
 554     /* Hawaii with old firmware needs type2 nop packet.
 555      * accel_working2 with value 3 indicates the new firmware.
 556      */
 557     ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI ||
 558                                      (ws->info.family == CHIP_HAWAII &&
 559                                       ws->accel_working2 < 3);
 560     ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
 561     ws->info.ib_start_alignment = 4096;
 562     ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
 563     /* HTILE is broken with 1D tiling on old kernels and CIK. */
 564     ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
 565                                              ws->info.drm_minor >= 38;
 566     ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
 567     ws->info.has_bo_metadata = false;
 568     ws->info.has_gpu_reset_status_query = false;
 569     ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
 570     ws->info.has_eqaa_surface_allocator = false;
 571     ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
 572     ws->info.kernel_flushes_tc_l2_after_ib = true;
 573     /* Old kernels disallowed register writes via COPY_DATA
 574      * that are used for indirect compute dispatches. */
 575     ws->info.has_indirect_compute_dispatch = ws->info.chip_class == CIK ||
 576                                              (ws->info.chip_class == SI &&
 577                                               ws->info.drm_minor >= 45);
 578     /* SI doesn't support unaligned loads. */
 579     ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK &&
 580                                           ws->info.drm_minor >= 50;
 581     ws->info.has_sparse_vm_mappings = false;
 582     /* 2D tiling on CIK is supported since DRM 2.35.0 */
 583     ws->info.has_2d_tiling = ws->info.chip_class <= SI || ws->info.drm_minor >= 35;
 584     ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
 585
 586     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
 587
 588     return true;
 589 }
 590
 591 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 592 {
 593     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 594
 595     if (util_queue_is_initialized(&ws->cs_queue))
 596         util_queue_destroy(&ws->cs_queue);
 597
 598     mtx_destroy(&ws->hyperz_owner_mutex);
 599     mtx_destroy(&ws->cmask_owner_mutex);
 600
 601     if (ws->info.r600_has_virtual_memory)
 602         pb_slabs_deinit(&ws->bo_slabs);
 603     pb_cache_deinit(&ws->bo_cache);
 604
 605     if (ws->gen >= DRV_R600) {
 606         radeon_surface_manager_free(ws->surf_man);
 607     }
 608
 609     util_hash_table_destroy(ws->bo_names);
 610     util_hash_table_destroy(ws->bo_handles);
 611     util_hash_table_destroy(ws->bo_vas);
 612     mtx_destroy(&ws->bo_handles_mutex);
 613     mtx_destroy(&ws->vm32.mutex);
 614     mtx_destroy(&ws->vm64.mutex);
 615     mtx_destroy(&ws->bo_fence_lock);
 616
 617     if (ws->fd >= 0)
 618         close(ws->fd);
 619
 620     FREE(rws);
 621 }
 622
 623 static void radeon_query_info(struct radeon_winsys *rws,
 624                               struct radeon_info *info)
 625 {
 626     *info = ((struct radeon_drm_winsys *)rws)->info;
 627 }
 628
 629 static bool radeon_cs_request_feature(struct radeon_cmdbuf *rcs,
 630                                       enum radeon_feature_id fid,
 631                                       bool enable)
 632 {
 633     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 634
 635     switch (fid) {
 636     case RADEON_FID_R300_HYPERZ_ACCESS:
 637         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 638                                     &cs->ws->hyperz_owner_mutex,
 639                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 640                                     enable);
 641
 642     case RADEON_FID_R300_CMASK_ACCESS:
 643         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 644                                     &cs->ws->cmask_owner_mutex,
 645                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 646                                     enable);
 647     }
 648     return false;
 649 }
 650
 651 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 652                                    enum radeon_value_id value)
 653 {
 654     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 655     uint64_t retval = 0;
 656
 657     switch (value) {
 658     case RADEON_REQUESTED_VRAM_MEMORY:
 659         return ws->allocated_vram;
 660     case RADEON_REQUESTED_GTT_MEMORY:
 661         return ws->allocated_gtt;
 662     case RADEON_MAPPED_VRAM:
 663        return ws->mapped_vram;
 664     case RADEON_MAPPED_GTT:
 665        return ws->mapped_gtt;
 666     case RADEON_BUFFER_WAIT_TIME_NS:
 667         return ws->buffer_wait_time;
 668     case RADEON_NUM_MAPPED_BUFFERS:
 669         return ws->num_mapped_buffers;
 670     case RADEON_TIMESTAMP:
 671         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 672             assert(0);
 673             return 0;
 674         }
 675
 676         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 677                              (uint32_t*)&retval);
 678         return retval;
 679     case RADEON_NUM_GFX_IBS:
 680         return ws->num_gfx_IBs;
 681     case RADEON_NUM_SDMA_IBS:
 682         return ws->num_sdma_IBs;
 683     case RADEON_NUM_BYTES_MOVED:
 684         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 685                              "num-bytes-moved", (uint32_t*)&retval);
 686         return retval;
 687     case RADEON_NUM_EVICTIONS:
 688     case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 689     case RADEON_VRAM_VIS_USAGE:
 690     case RADEON_GFX_BO_LIST_COUNTER:
 691     case RADEON_GFX_IB_SIZE_COUNTER:
 692         return 0; /* unimplemented */
 693     case RADEON_VRAM_USAGE:
 694         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 695                              "vram-usage", (uint32_t*)&retval);
 696         return retval;
 697     case RADEON_GTT_USAGE:
 698         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 699                              "gtt-usage", (uint32_t*)&retval);
 700         return retval;
 701     case RADEON_GPU_TEMPERATURE:
 702         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
 703                              "gpu-temp", (uint32_t*)&retval);
 704         return retval;
 705     case RADEON_CURRENT_SCLK:
 706         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
 707                              "current-gpu-sclk", (uint32_t*)&retval);
 708         return retval;
 709     case RADEON_CURRENT_MCLK:
 710         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
 711                              "current-gpu-mclk", (uint32_t*)&retval);
 712         return retval;
 713     case RADEON_GPU_RESET_COUNTER:
 714         radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
 715                              "gpu-reset-counter", (uint32_t*)&retval);
 716         return retval;
 717     case RADEON_CS_THREAD_TIME:
 718         return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 719     }
 720     return 0;
 721 }
 722
 723 static bool radeon_read_registers(struct radeon_winsys *rws,
 724                                   unsigned reg_offset,
 725                                   unsigned num_registers, uint32_t *out)
 726 {
 727     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 728     unsigned i;
 729
 730     for (i = 0; i < num_registers; i++) {
 731         uint32_t reg = reg_offset + i*4;
 732
 733         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg))
 734             return false;
 735         out[i] = reg;
 736     }
 737     return true;
 738 }
 739
 740 static unsigned hash_fd(void *key)
 741 {
 742     int fd = pointer_to_intptr(key);
 743     struct stat stat;
 744     fstat(fd, &stat);
 745
 746     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 747 }
 748
 749 static int compare_fd(void *key1, void *key2)
 750 {
 751     int fd1 = pointer_to_intptr(key1);
 752     int fd2 = pointer_to_intptr(key2);
 753     struct stat stat1, stat2;
 754     fstat(fd1, &stat1);
 755     fstat(fd2, &stat2);
 756
 757     return stat1.st_dev != stat2.st_dev ||
 758            stat1.st_ino != stat2.st_ino ||
 759            stat1.st_rdev != stat2.st_rdev;
 760 }
 761
 762 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", true)
 763
 764 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 765 {
 766     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 767     bool destroy;
 768
 769     /* When the reference counter drops to zero, remove the fd from the table.
 770      * This must happen while the mutex is locked, so that
 771      * radeon_drm_winsys_create in another thread doesn't get the winsys
 772      * from the table when the counter drops to 0. */
 773     mtx_lock(&fd_tab_mutex);
 774
 775     destroy = pipe_reference(&rws->reference, NULL);
 776     if (destroy && fd_tab) {
 777         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 778         if (util_hash_table_count(fd_tab) == 0) {
 779            util_hash_table_destroy(fd_tab);
 780            fd_tab = NULL;
 781         }
 782     }
 783
 784     mtx_unlock(&fd_tab_mutex);
 785     return destroy;
 786 }
 787
 788 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 789
 790 static unsigned handle_hash(void *key)
 791 {
 792     return PTR_TO_UINT(key);
 793 }
 794
 795 static int handle_compare(void *key1, void *key2)
 796 {
 797     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 798 }
 799
 800 PUBLIC struct radeon_winsys *
 801 radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
 802                          radeon_screen_create_t screen_create)
 803 {
 804     struct radeon_drm_winsys *ws;
 805
 806     mtx_lock(&fd_tab_mutex);
 807     if (!fd_tab) {
 808         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 809     }
 810
 811     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 812     if (ws) {
 813         pipe_reference(NULL, &ws->reference);
 814         mtx_unlock(&fd_tab_mutex);
 815         return &ws->base;
 816     }
 817
 818     ws = CALLOC_STRUCT(radeon_drm_winsys);
 819     if (!ws) {
 820         mtx_unlock(&fd_tab_mutex);
 821         return NULL;
 822     }
 823
 824     ws->fd = fcntl(fd, F_DUPFD_CLOEXEC, 3);
 825
 826     if (!do_winsys_init(ws))
 827         goto fail1;
 828
 829     pb_cache_init(&ws->bo_cache, RADEON_MAX_CACHED_HEAPS,
 830                   500000, ws->check_vm ? 1.0f : 2.0f, 0,
 831                   MIN2(ws->info.vram_size, ws->info.gart_size),
 832                   radeon_bo_destroy,
 833                   radeon_bo_can_reclaim);
 834
 835     if (ws->info.r600_has_virtual_memory) {
 836         /* There is no fundamental obstacle to using slab buffer allocation
 837          * without GPUVM, but enabling it requires making sure that the drivers
 838          * honor the address offset.
 839          */
 840         if (!pb_slabs_init(&ws->bo_slabs,
 841                            RADEON_SLAB_MIN_SIZE_LOG2, RADEON_SLAB_MAX_SIZE_LOG2,
 842                            RADEON_MAX_SLAB_HEAPS,
 843                            ws,
 844                            radeon_bo_can_reclaim_slab,
 845                            radeon_bo_slab_alloc,
 846                            radeon_bo_slab_free))
 847             goto fail_cache;
 848
 849         ws->info.min_alloc_size = 1 << RADEON_SLAB_MIN_SIZE_LOG2;
 850     } else {
 851         ws->info.min_alloc_size = ws->info.gart_page_size;
 852     }
 853
 854     if (ws->gen >= DRV_R600) {
 855         ws->surf_man = radeon_surface_manager_new(ws->fd);
 856         if (!ws->surf_man)
 857             goto fail_slab;
 858     }
 859
 860     /* init reference */
 861     pipe_reference_init(&ws->reference, 1);
 862
 863     /* Set functions. */
 864     ws->base.unref = radeon_winsys_unref;
 865     ws->base.destroy = radeon_winsys_destroy;
 866     ws->base.query_info = radeon_query_info;
 867     ws->base.cs_request_feature = radeon_cs_request_feature;
 868     ws->base.query_value = radeon_query_value;
 869     ws->base.read_registers = radeon_read_registers;
 870
 871     radeon_drm_bo_init_functions(ws);
 872     radeon_drm_cs_init_functions(ws);
 873     radeon_surface_init_functions(ws);
 874
 875     (void) mtx_init(&ws->hyperz_owner_mutex, mtx_plain);
 876     (void) mtx_init(&ws->cmask_owner_mutex, mtx_plain);
 877
 878     ws->bo_names = util_hash_table_create(handle_hash, handle_compare);
 879     ws->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 880     ws->bo_vas = util_hash_table_create(handle_hash, handle_compare);
 881     (void) mtx_init(&ws->bo_handles_mutex, mtx_plain);
 882     (void) mtx_init(&ws->vm32.mutex, mtx_plain);
 883     (void) mtx_init(&ws->vm64.mutex, mtx_plain);
 884     (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
 885     list_inithead(&ws->vm32.holes);
 886     list_inithead(&ws->vm64.holes);
 887
 888     /* The kernel currently returns 8MB. Make sure this doesn't change. */
 889     if (ws->va_start > 8 * 1024 * 1024) {
 890         /* Not enough 32-bit address space. */
 891         radeon_winsys_destroy(&ws->base);
 892         mtx_unlock(&fd_tab_mutex);
 893         return NULL;
 894     }
 895
 896     ws->vm32.start = ws->va_start;
 897     ws->vm32.end = 1ull << 32;
 898
 899     /* The maximum is 8GB of virtual address space limited by the kernel.
 900      * It's obviously not enough for bigger cards, like Hawaiis with 4GB
 901      * and 8GB of physical memory and 4GB of GART.
 902      *
 903      * Older kernels set the limit to 4GB, which is even worse, so they only
 904      * have 32-bit address space.
 905      */
 906     if (ws->info.drm_minor >= 41) {
 907         ws->vm64.start = 1ull << 32;
 908         ws->vm64.end = 1ull << 33;
 909     }
 910
 911     /* TTM aligns the BO size to the CPU page size */
 912     ws->info.gart_page_size = sysconf(_SC_PAGESIZE);
 913
 914     if (ws->num_cpus > 1 && debug_get_option_thread())
 915         util_queue_init(&ws->cs_queue, "rcs", 8, 1, 0);
 916
 917     /* Create the screen at the end. The winsys must be initialized
 918      * completely.
 919      *
 920      * Alternatively, we could create the screen based on "ws->gen"
 921      * and link all drivers into one binary blob. */
 922     ws->base.screen = screen_create(&ws->base, config);
 923     if (!ws->base.screen) {
 924         radeon_winsys_destroy(&ws->base);
 925         mtx_unlock(&fd_tab_mutex);
 926         return NULL;
 927     }
 928
 929     util_hash_table_set(fd_tab, intptr_to_pointer(ws->fd), ws);
 930
 931     /* We must unlock the mutex once the winsys is fully initialized, so that
 932      * other threads attempting to create the winsys from the same fd will
 933      * get a fully initialized winsys and not just half-way initialized. */
 934     mtx_unlock(&fd_tab_mutex);
 935
 936     return &ws->base;
 937
 938 fail_slab:
 939     if (ws->info.r600_has_virtual_memory)
 940         pb_slabs_deinit(&ws->bo_slabs);
 941 fail_cache:
 942     pb_cache_deinit(&ws->bo_cache);
 943 fail1:
 944     mtx_unlock(&fd_tab_mutex);
 945     if (ws->surf_man)
 946         radeon_surface_manager_free(ws->surf_man);
 947     if (ws->fd >= 0)
 948         close(ws->fd);
 949
 950     FREE(ws);
 951     return NULL;
 952 }