src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "pipebuffer/pb_bufmgr.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_hash_table.h"
  41
  42 #include <xf86drm.h>
  43 #include <stdio.h>
  44 #include <sys/types.h>
  45 #include <sys/stat.h>
  46 #include <unistd.h>
  47 #include <radeon_surface.h>
  48
  49 #ifndef RADEON_INFO_ACTIVE_CU_COUNT
  50 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
  51 #endif
  52
  53 #ifndef RADEON_INFO_CURRENT_GPU_TEMP
  54 #define RADEON_INFO_CURRENT_GPU_TEMP    0x21
  55 #define RADEON_INFO_CURRENT_GPU_SCLK    0x22
  56 #define RADEON_INFO_CURRENT_GPU_MCLK    0x23
  57 #define RADEON_INFO_READ_REG            0x24
  58 #endif
  59
  60 #define RADEON_INFO_VA_UNMAP_WORKING    0x25
  61
  62 #ifndef RADEON_INFO_GPU_RESET_COUNTER
  63 #define RADEON_INFO_GPU_RESET_COUNTER   0x26
  64 #endif
  65
  66 static struct util_hash_table *fd_tab = NULL;
  67 pipe_static_mutex(fd_tab_mutex);
  68
  69 /* Enable/disable feature access for one command stream.
  70  * If enable == TRUE, return TRUE on success.
  71  * Otherwise, return FALSE.
  72  *
  73  * We basically do the same thing kernel does, because we have to deal
  74  * with multiple contexts (here command streams) backed by one winsys. */
  75 static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
  76                                     struct radeon_drm_cs **owner,
  77                                     pipe_mutex *mutex,
  78                                     unsigned request, const char *request_name,
  79                                     boolean enable)
  80 {
  81     struct drm_radeon_info info;
  82     unsigned value = enable ? 1 : 0;
  83
  84     memset(&info, 0, sizeof(info));
  85
  86     pipe_mutex_lock(*mutex);
  87
  88     /* Early exit if we are sure the request will fail. */
  89     if (enable) {
  90         if (*owner) {
  91             pipe_mutex_unlock(*mutex);
  92             return FALSE;
  93         }
  94     } else {
  95         if (*owner != applier) {
  96             pipe_mutex_unlock(*mutex);
  97             return FALSE;
  98         }
  99     }
 100
 101     /* Pass through the request to the kernel. */
 102     info.value = (unsigned long)&value;
 103     info.request = request;
 104     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
 105                             &info, sizeof(info)) != 0) {
 106         pipe_mutex_unlock(*mutex);
 107         return FALSE;
 108     }
 109
 110     /* Update the rights in the winsys. */
 111     if (enable) {
 112         if (value) {
 113             *owner = applier;
 114             pipe_mutex_unlock(*mutex);
 115             return TRUE;
 116         }
 117     } else {
 118         *owner = NULL;
 119     }
 120
 121     pipe_mutex_unlock(*mutex);
 122     return FALSE;
 123 }
 124
 125 static boolean radeon_get_drm_value(int fd, unsigned request,
 126                                     const char *errname, uint32_t *out)
 127 {
 128     struct drm_radeon_info info;
 129     int retval;
 130
 131     memset(&info, 0, sizeof(info));
 132
 133     info.value = (unsigned long)out;
 134     info.request = request;
 135
 136     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 137     if (retval) {
 138         if (errname) {
 139             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 140                     errname, retval);
 141         }
 142         return FALSE;
 143     }
 144     return TRUE;
 145 }
 146
 147 /* Helper function to do the ioctls needed for setup and init. */
 148 static boolean do_winsys_init(struct radeon_drm_winsys *ws)
 149 {
 150     struct drm_radeon_gem_info gem_info;
 151     int retval;
 152     drmVersionPtr version;
 153
 154     memset(&gem_info, 0, sizeof(gem_info));
 155
 156     /* We do things in a specific order here.
 157      *
 158      * DRM version first. We need to be sure we're running on a KMS chipset.
 159      * This is also for some features.
 160      *
 161      * Then, the PCI ID. This is essential and should return usable numbers
 162      * for all Radeons. If this fails, we probably got handed an FD for some
 163      * non-Radeon card.
 164      *
 165      * The GEM info is actually bogus on the kernel side, as well as our side
 166      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 167      * we don't actually use the info for anything yet.
 168      *
 169      * The GB and Z pipe requests should always succeed, but they might not
 170      * return sensical values for all chipsets, but that's alright because
 171      * the pipe drivers already know that.
 172      */
 173
 174     /* Get DRM version. */
 175     version = drmGetVersion(ws->fd);
 176     if (version->version_major != 2 ||
 177         version->version_minor < 12) {
 178         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 179                 "only compatible with 2.12.0 (kernel 3.2) or later.\n",
 180                 __FUNCTION__,
 181                 version->version_major,
 182                 version->version_minor,
 183                 version->version_patchlevel);
 184         drmFreeVersion(version);
 185         return FALSE;
 186     }
 187
 188     ws->info.drm_major = version->version_major;
 189     ws->info.drm_minor = version->version_minor;
 190     ws->info.drm_patchlevel = version->version_patchlevel;
 191     drmFreeVersion(version);
 192
 193     /* Get PCI ID. */
 194     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 195                               &ws->info.pci_id))
 196         return FALSE;
 197
 198     /* Check PCI ID. */
 199     switch (ws->info.pci_id) {
 200 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 201 #include "pci_ids/r300_pci_ids.h"
 202 #undef CHIPSET
 203
 204 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 205 #include "pci_ids/r600_pci_ids.h"
 206 #undef CHIPSET
 207
 208 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 209 #include "pci_ids/radeonsi_pci_ids.h"
 210 #undef CHIPSET
 211
 212     default:
 213         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 214         return FALSE;
 215     }
 216
 217     switch (ws->info.family) {
 218     default:
 219     case CHIP_UNKNOWN:
 220         fprintf(stderr, "radeon: Unknown family.\n");
 221         return FALSE;
 222     case CHIP_R300:
 223     case CHIP_R350:
 224     case CHIP_RV350:
 225     case CHIP_RV370:
 226     case CHIP_RV380:
 227     case CHIP_RS400:
 228     case CHIP_RC410:
 229     case CHIP_RS480:
 230         ws->info.chip_class = R300;
 231         break;
 232     case CHIP_R420:     /* R4xx-based cores. */
 233     case CHIP_R423:
 234     case CHIP_R430:
 235     case CHIP_R480:
 236     case CHIP_R481:
 237     case CHIP_RV410:
 238     case CHIP_RS600:
 239     case CHIP_RS690:
 240     case CHIP_RS740:
 241         ws->info.chip_class = R400;
 242         break;
 243     case CHIP_RV515:    /* R5xx-based cores. */
 244     case CHIP_R520:
 245     case CHIP_RV530:
 246     case CHIP_R580:
 247     case CHIP_RV560:
 248     case CHIP_RV570:
 249         ws->info.chip_class = R500;
 250         break;
 251     case CHIP_R600:
 252     case CHIP_RV610:
 253     case CHIP_RV630:
 254     case CHIP_RV670:
 255     case CHIP_RV620:
 256     case CHIP_RV635:
 257     case CHIP_RS780:
 258     case CHIP_RS880:
 259         ws->info.chip_class = R600;
 260         break;
 261     case CHIP_RV770:
 262     case CHIP_RV730:
 263     case CHIP_RV710:
 264     case CHIP_RV740:
 265         ws->info.chip_class = R700;
 266         break;
 267     case CHIP_CEDAR:
 268     case CHIP_REDWOOD:
 269     case CHIP_JUNIPER:
 270     case CHIP_CYPRESS:
 271     case CHIP_HEMLOCK:
 272     case CHIP_PALM:
 273     case CHIP_SUMO:
 274     case CHIP_SUMO2:
 275     case CHIP_BARTS:
 276     case CHIP_TURKS:
 277     case CHIP_CAICOS:
 278         ws->info.chip_class = EVERGREEN;
 279         break;
 280     case CHIP_CAYMAN:
 281     case CHIP_ARUBA:
 282         ws->info.chip_class = CAYMAN;
 283         break;
 284     case CHIP_TAHITI:
 285     case CHIP_PITCAIRN:
 286     case CHIP_VERDE:
 287     case CHIP_OLAND:
 288     case CHIP_HAINAN:
 289         ws->info.chip_class = SI;
 290         break;
 291     case CHIP_BONAIRE:
 292     case CHIP_KAVERI:
 293     case CHIP_KABINI:
 294     case CHIP_HAWAII:
 295     case CHIP_MULLINS:
 296         ws->info.chip_class = CIK;
 297         break;
 298     }
 299
 300     /* Check for dma */
 301     ws->info.has_sdma = FALSE;
 302     /* DMA is disabled on R700. There is IB corruption and hangs. */
 303     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 304         ws->info.has_sdma = TRUE;
 305     }
 306
 307     /* Check for UVD and VCE */
 308     ws->info.has_uvd = FALSE;
 309     ws->info.vce_fw_version = 0x00000000;
 310     if (ws->info.drm_minor >= 32) {
 311         uint32_t value = RADEON_CS_RING_UVD;
 312         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 313                                  "UVD Ring working", &value))
 314             ws->info.has_uvd = value;
 315
 316         value = RADEON_CS_RING_VCE;
 317         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 318                                  NULL, &value) && value) {
 319
 320             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 321                                      "VCE FW version", &value))
 322                 ws->info.vce_fw_version = value;
 323         }
 324     }
 325
 326     /* Check for userptr support. */
 327     {
 328         struct drm_radeon_gem_userptr args = {0};
 329
 330         /* If the ioctl doesn't exist, -EINVAL is returned.
 331          *
 332          * If the ioctl exists, it should return -EACCES
 333          * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
 334          * aren't set.
 335          */
 336         ws->info.has_userptr =
 337             drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
 338                                 &args, sizeof(args)) == -EACCES;
 339     }
 340
 341     /* Get GEM info. */
 342     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 343             &gem_info, sizeof(gem_info));
 344     if (retval) {
 345         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 346                 retval);
 347         return FALSE;
 348     }
 349     ws->info.gart_size = gem_info.gart_size;
 350     ws->info.vram_size = gem_info.vram_size;
 351
 352     /* Get max clock frequency info and convert it to MHz */
 353     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 354                          &ws->info.max_shader_clock);
 355     ws->info.max_shader_clock /= 1000;
 356
 357     radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
 358                          &ws->info.enabled_rb_mask);
 359
 360     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 361
 362     /* Generation-specific queries. */
 363     if (ws->gen == DRV_R300) {
 364         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 365                                   "GB pipe count",
 366                                   &ws->info.r300_num_gb_pipes))
 367             return FALSE;
 368
 369         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 370                                   "Z pipe count",
 371                                   &ws->info.r300_num_z_pipes))
 372             return FALSE;
 373     }
 374     else if (ws->gen >= DRV_R600) {
 375         uint32_t tiling_config = 0;
 376
 377         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 378                                   "num backends",
 379                                   &ws->info.num_render_backends))
 380             return FALSE;
 381
 382         /* get the GPU counter frequency, failure is not fatal */
 383         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 384                              &ws->info.clock_crystal_freq);
 385
 386         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 387                              &tiling_config);
 388
 389         ws->info.r600_num_banks =
 390             ws->info.chip_class >= EVERGREEN ?
 391                 4 << ((tiling_config & 0xf0) >> 4) :
 392                 4 << ((tiling_config & 0x30) >> 4);
 393
 394         ws->info.pipe_interleave_bytes =
 395             ws->info.chip_class >= EVERGREEN ?
 396                 256 << ((tiling_config & 0xf00) >> 8) :
 397                 256 << ((tiling_config & 0xc0) >> 6);
 398
 399         if (!ws->info.pipe_interleave_bytes)
 400             ws->info.pipe_interleave_bytes =
 401                 ws->info.chip_class >= EVERGREEN ? 512 : 256;
 402
 403         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 404                              &ws->info.num_tile_pipes);
 405
 406         /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
 407          * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
 408          * reports a different value (12). Fix it by setting what's in the
 409          * GB_TILE_MODE array (8).
 410          */
 411         if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
 412             ws->info.num_tile_pipes = 8;
 413
 414         if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 415                                   &ws->info.r600_gb_backend_map))
 416             ws->info.r600_gb_backend_map_valid = TRUE;
 417
 418         ws->info.has_virtual_memory = FALSE;
 419         if (ws->info.drm_minor >= 13) {
 420             uint32_t ib_vm_max_size;
 421
 422             ws->info.has_virtual_memory = TRUE;
 423             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 424                                       &ws->va_start))
 425                 ws->info.has_virtual_memory = FALSE;
 426             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 427                                       &ib_vm_max_size))
 428                 ws->info.has_virtual_memory = FALSE;
 429             radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
 430                                  &ws->va_unmap_working);
 431         }
 432         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", FALSE))
 433                 ws->info.has_virtual_memory = FALSE;
 434     }
 435
 436     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 437      * chips have at least 2 pipes, so we use 2 as a default. */
 438     ws->info.r600_max_quad_pipes = 2;
 439     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 440                          &ws->info.r600_max_quad_pipes);
 441
 442     /* All GPUs have at least one compute unit */
 443     ws->info.num_good_compute_units = 1;
 444     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 445                          &ws->info.num_good_compute_units);
 446
 447     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 448                          &ws->info.max_se);
 449
 450     if (!ws->info.max_se) {
 451         switch (ws->info.family) {
 452         default:
 453             ws->info.max_se = 1;
 454             break;
 455         case CHIP_CYPRESS:
 456         case CHIP_HEMLOCK:
 457         case CHIP_BARTS:
 458         case CHIP_CAYMAN:
 459         case CHIP_TAHITI:
 460         case CHIP_PITCAIRN:
 461         case CHIP_BONAIRE:
 462             ws->info.max_se = 2;
 463             break;
 464         case CHIP_HAWAII:
 465             ws->info.max_se = 4;
 466             break;
 467         }
 468     }
 469
 470     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 471                          &ws->info.max_sh_per_se);
 472
 473     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 474                          &ws->accel_working2);
 475     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 476         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 477                 "returned accel_working2 value %u is smaller than 2. "
 478                 "Please install a newer kernel.\n",
 479                 ws->accel_working2);
 480         return FALSE;
 481     }
 482
 483     if (radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 484                              ws->info.si_tile_mode_array)) {
 485         ws->info.si_tile_mode_array_valid = TRUE;
 486     }
 487
 488     if (radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 489                              ws->info.cik_macrotile_mode_array)) {
 490         ws->info.cik_macrotile_mode_array_valid = TRUE;
 491     }
 492
 493     /* Hawaii with old firmware needs type2 nop packet.
 494      * accel_working2 with value 3 indicates the new firmware.
 495      */
 496     ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI ||
 497                                      (ws->info.family == CHIP_HAWAII &&
 498                                       ws->accel_working2 < 3);
 499
 500     return TRUE;
 501 }
 502
 503 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 504 {
 505     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 506
 507     if (ws->thread) {
 508         ws->kill_thread = 1;
 509         pipe_semaphore_signal(&ws->cs_queued);
 510         pipe_thread_wait(ws->thread);
 511     }
 512     pipe_semaphore_destroy(&ws->cs_queued);
 513
 514     pipe_mutex_destroy(ws->hyperz_owner_mutex);
 515     pipe_mutex_destroy(ws->cmask_owner_mutex);
 516     pipe_mutex_destroy(ws->cs_stack_lock);
 517
 518     pb_cache_deinit(&ws->bo_cache);
 519
 520     if (ws->gen >= DRV_R600) {
 521         radeon_surface_manager_free(ws->surf_man);
 522     }
 523
 524     util_hash_table_destroy(ws->bo_names);
 525     util_hash_table_destroy(ws->bo_handles);
 526     util_hash_table_destroy(ws->bo_vas);
 527     pipe_mutex_destroy(ws->bo_handles_mutex);
 528     pipe_mutex_destroy(ws->bo_va_mutex);
 529
 530     if (ws->fd >= 0)
 531         close(ws->fd);
 532
 533     FREE(rws);
 534 }
 535
 536 static void radeon_query_info(struct radeon_winsys *rws,
 537                               struct radeon_info *info)
 538 {
 539     *info = ((struct radeon_drm_winsys *)rws)->info;
 540 }
 541
 542 static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 543                                          enum radeon_feature_id fid,
 544                                          boolean enable)
 545 {
 546     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 547
 548     switch (fid) {
 549     case RADEON_FID_R300_HYPERZ_ACCESS:
 550         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 551                                     &cs->ws->hyperz_owner_mutex,
 552                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 553                                     enable);
 554
 555     case RADEON_FID_R300_CMASK_ACCESS:
 556         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 557                                     &cs->ws->cmask_owner_mutex,
 558                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 559                                     enable);
 560     }
 561     return FALSE;
 562 }
 563
 564 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 565                                    enum radeon_value_id value)
 566 {
 567     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 568     uint64_t retval = 0;
 569
 570     switch (value) {
 571     case RADEON_REQUESTED_VRAM_MEMORY:
 572         return ws->allocated_vram;
 573     case RADEON_REQUESTED_GTT_MEMORY:
 574         return ws->allocated_gtt;
 575     case RADEON_BUFFER_WAIT_TIME_NS:
 576         return ws->buffer_wait_time;
 577     case RADEON_TIMESTAMP:
 578         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 579             assert(0);
 580             return 0;
 581         }
 582
 583         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 584                              (uint32_t*)&retval);
 585         return retval;
 586     case RADEON_NUM_CS_FLUSHES:
 587         return ws->num_cs_flushes;
 588     case RADEON_NUM_BYTES_MOVED:
 589         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 590                              "num-bytes-moved", (uint32_t*)&retval);
 591         return retval;
 592     case RADEON_VRAM_USAGE:
 593         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 594                              "vram-usage", (uint32_t*)&retval);
 595         return retval;
 596     case RADEON_GTT_USAGE:
 597         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 598                              "gtt-usage", (uint32_t*)&retval);
 599         return retval;
 600     case RADEON_GPU_TEMPERATURE:
 601         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
 602                              "gpu-temp", (uint32_t*)&retval);
 603         return retval;
 604     case RADEON_CURRENT_SCLK:
 605         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
 606                              "current-gpu-sclk", (uint32_t*)&retval);
 607         return retval;
 608     case RADEON_CURRENT_MCLK:
 609         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
 610                              "current-gpu-mclk", (uint32_t*)&retval);
 611         return retval;
 612     case RADEON_GPU_RESET_COUNTER:
 613         radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
 614                              "gpu-reset-counter", (uint32_t*)&retval);
 615         return retval;
 616     }
 617     return 0;
 618 }
 619
 620 static bool radeon_read_registers(struct radeon_winsys *rws,
 621                                   unsigned reg_offset,
 622                                   unsigned num_registers, uint32_t *out)
 623 {
 624     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 625     unsigned i;
 626
 627     for (i = 0; i < num_registers; i++) {
 628         uint32_t reg = reg_offset + i*4;
 629
 630         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg))
 631             return false;
 632         out[i] = reg;
 633     }
 634     return true;
 635 }
 636
 637 static unsigned hash_fd(void *key)
 638 {
 639     int fd = pointer_to_intptr(key);
 640     struct stat stat;
 641     fstat(fd, &stat);
 642
 643     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 644 }
 645
 646 static int compare_fd(void *key1, void *key2)
 647 {
 648     int fd1 = pointer_to_intptr(key1);
 649     int fd2 = pointer_to_intptr(key2);
 650     struct stat stat1, stat2;
 651     fstat(fd1, &stat1);
 652     fstat(fd2, &stat2);
 653
 654     return stat1.st_dev != stat2.st_dev ||
 655            stat1.st_ino != stat2.st_ino ||
 656            stat1.st_rdev != stat2.st_rdev;
 657 }
 658
 659 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys *ws, struct radeon_drm_cs *cs)
 660 {
 661 retry:
 662     pipe_mutex_lock(ws->cs_stack_lock);
 663     if (ws->ncs >= RING_LAST) {
 664         /* no room left for a flush */
 665         pipe_mutex_unlock(ws->cs_stack_lock);
 666         goto retry;
 667     }
 668     ws->cs_stack[ws->ncs++] = cs;
 669     pipe_mutex_unlock(ws->cs_stack_lock);
 670     pipe_semaphore_signal(&ws->cs_queued);
 671 }
 672
 673 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param)
 674 {
 675     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys *)param;
 676     struct radeon_drm_cs *cs;
 677     unsigned i;
 678
 679     while (1) {
 680         pipe_semaphore_wait(&ws->cs_queued);
 681         if (ws->kill_thread)
 682             break;
 683
 684         pipe_mutex_lock(ws->cs_stack_lock);
 685         cs = ws->cs_stack[0];
 686         for (i = 1; i < ws->ncs; i++)
 687             ws->cs_stack[i - 1] = ws->cs_stack[i];
 688         ws->cs_stack[--ws->ncs] = NULL;
 689         pipe_mutex_unlock(ws->cs_stack_lock);
 690
 691         if (cs) {
 692             radeon_drm_cs_emit_ioctl_oneshot(cs, cs->cst);
 693             pipe_semaphore_signal(&cs->flush_completed);
 694         }
 695     }
 696     pipe_mutex_lock(ws->cs_stack_lock);
 697     for (i = 0; i < ws->ncs; i++) {
 698         pipe_semaphore_signal(&ws->cs_stack[i]->flush_completed);
 699         ws->cs_stack[i] = NULL;
 700     }
 701     ws->ncs = 0;
 702     pipe_mutex_unlock(ws->cs_stack_lock);
 703     return 0;
 704 }
 705
 706 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", TRUE)
 707 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param);
 708
 709 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 710 {
 711     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 712     bool destroy;
 713
 714     /* When the reference counter drops to zero, remove the fd from the table.
 715      * This must happen while the mutex is locked, so that
 716      * radeon_drm_winsys_create in another thread doesn't get the winsys
 717      * from the table when the counter drops to 0. */
 718     pipe_mutex_lock(fd_tab_mutex);
 719
 720     destroy = pipe_reference(&rws->reference, NULL);
 721     if (destroy && fd_tab)
 722         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 723
 724     pipe_mutex_unlock(fd_tab_mutex);
 725     return destroy;
 726 }
 727
 728 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 729
 730 static unsigned handle_hash(void *key)
 731 {
 732     return PTR_TO_UINT(key);
 733 }
 734
 735 static int handle_compare(void *key1, void *key2)
 736 {
 737     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 738 }
 739
 740 PUBLIC struct radeon_winsys *
 741 radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
 742 {
 743     struct radeon_drm_winsys *ws;
 744
 745     pipe_mutex_lock(fd_tab_mutex);
 746     if (!fd_tab) {
 747         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 748     }
 749
 750     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 751     if (ws) {
 752         pipe_reference(NULL, &ws->reference);
 753         pipe_mutex_unlock(fd_tab_mutex);
 754         return &ws->base;
 755     }
 756
 757     ws = CALLOC_STRUCT(radeon_drm_winsys);
 758     if (!ws) {
 759         pipe_mutex_unlock(fd_tab_mutex);
 760         return NULL;
 761     }
 762
 763     ws->fd = dup(fd);
 764
 765     if (!do_winsys_init(ws))
 766         goto fail1;
 767
 768     pb_cache_init(&ws->bo_cache, 500000, 2.0f, 0,
 769                   MIN2(ws->info.vram_size, ws->info.gart_size),
 770                   radeon_bo_destroy,
 771                   radeon_bo_can_reclaim);
 772
 773     if (ws->gen >= DRV_R600) {
 774         ws->surf_man = radeon_surface_manager_new(ws->fd);
 775         if (!ws->surf_man)
 776             goto fail;
 777     }
 778
 779     /* init reference */
 780     pipe_reference_init(&ws->reference, 1);
 781
 782     /* Set functions. */
 783     ws->base.unref = radeon_winsys_unref;
 784     ws->base.destroy = radeon_winsys_destroy;
 785     ws->base.query_info = radeon_query_info;
 786     ws->base.cs_request_feature = radeon_cs_request_feature;
 787     ws->base.query_value = radeon_query_value;
 788     ws->base.read_registers = radeon_read_registers;
 789
 790     radeon_drm_bo_init_functions(ws);
 791     radeon_drm_cs_init_functions(ws);
 792     radeon_surface_init_functions(ws);
 793
 794     pipe_mutex_init(ws->hyperz_owner_mutex);
 795     pipe_mutex_init(ws->cmask_owner_mutex);
 796     pipe_mutex_init(ws->cs_stack_lock);
 797
 798     ws->bo_names = util_hash_table_create(handle_hash, handle_compare);
 799     ws->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 800     ws->bo_vas = util_hash_table_create(handle_hash, handle_compare);
 801     pipe_mutex_init(ws->bo_handles_mutex);
 802     pipe_mutex_init(ws->bo_va_mutex);
 803     ws->va_offset = ws->va_start;
 804     list_inithead(&ws->va_holes);
 805
 806     /* TTM aligns the BO size to the CPU page size */
 807     ws->size_align = sysconf(_SC_PAGESIZE);
 808
 809     ws->ncs = 0;
 810     pipe_semaphore_init(&ws->cs_queued, 0);
 811     if (ws->num_cpus > 1 && debug_get_option_thread())
 812         ws->thread = pipe_thread_create(radeon_drm_cs_emit_ioctl, ws);
 813
 814     /* Create the screen at the end. The winsys must be initialized
 815      * completely.
 816      *
 817      * Alternatively, we could create the screen based on "ws->gen"
 818      * and link all drivers into one binary blob. */
 819     ws->base.screen = screen_create(&ws->base);
 820     if (!ws->base.screen) {
 821         radeon_winsys_destroy(&ws->base);
 822         pipe_mutex_unlock(fd_tab_mutex);
 823         return NULL;
 824     }
 825
 826     util_hash_table_set(fd_tab, intptr_to_pointer(ws->fd), ws);
 827
 828     /* We must unlock the mutex once the winsys is fully initialized, so that
 829      * other threads attempting to create the winsys from the same fd will
 830      * get a fully initialized winsys and not just half-way initialized. */
 831     pipe_mutex_unlock(fd_tab_mutex);
 832
 833     return &ws->base;
 834
 835 fail:
 836     pb_cache_deinit(&ws->bo_cache);
 837 fail1:
 838     pipe_mutex_unlock(fd_tab_mutex);
 839     if (ws->surf_man)
 840         radeon_surface_manager_free(ws->surf_man);
 841     if (ws->fd >= 0)
 842         close(ws->fd);
 843
 844     FREE(ws);
 845     return NULL;
 846 }