2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Corbin Simpson <MostAwesomeDude@gmail.com>
30 * Joakim Sindholt <opensource@zhasha.com>
31 * Marek Olšák <maraeo@gmail.com>
34 #include "radeon_drm_bo.h"
35 #include "radeon_drm_cs.h"
36 #include "radeon_drm_public.h"
38 #include "pipebuffer/pb_bufmgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_hash_table.h"
46 * this are copy from radeon_drm, once an updated libdrm is released
47 * we should bump configure.ac requirement for it and remove the following
50 #ifndef RADEON_INFO_TILING_CONFIG
51 #define RADEON_INFO_TILING_CONFIG 6
54 #ifndef RADEON_INFO_WANT_HYPERZ
55 #define RADEON_INFO_WANT_HYPERZ 7
58 #ifndef RADEON_INFO_WANT_CMASK
59 #define RADEON_INFO_WANT_CMASK 8
62 #ifndef RADEON_INFO_CLOCK_CRYSTAL_FREQ
63 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 9
66 #ifndef RADEON_INFO_NUM_BACKENDS
67 #define RADEON_INFO_NUM_BACKENDS 0xa
70 #ifndef RADEON_INFO_NUM_TILE_PIPES
71 #define RADEON_INFO_NUM_TILE_PIPES 0xb
74 #ifndef RADEON_INFO_BACKEND_MAP
75 #define RADEON_INFO_BACKEND_MAP 0xd
78 #ifndef RADEON_INFO_VA_START
79 /* virtual address start, va < start are reserved by the kernel */
80 #define RADEON_INFO_VA_START 0x0e
81 /* maximum size of ib using the virtual memory cs */
82 #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
85 #ifndef RADEON_INFO_MAX_PIPES
86 #define RADEON_INFO_MAX_PIPES 0x10
89 #ifndef RADEON_INFO_TIMESTAMP
90 #define RADEON_INFO_TIMESTAMP 0x11
93 static struct util_hash_table
*fd_tab
= NULL
;
95 /* Enable/disable feature access for one command stream.
96 * If enable == TRUE, return TRUE on success.
97 * Otherwise, return FALSE.
99 * We basically do the same thing kernel does, because we have to deal
100 * with multiple contexts (here command streams) backed by one winsys. */
101 static boolean
radeon_set_fd_access(struct radeon_drm_cs
*applier
,
102 struct radeon_drm_cs
**owner
,
104 unsigned request
, const char *request_name
,
107 struct drm_radeon_info info
;
108 unsigned value
= enable
? 1 : 0;
110 memset(&info
, 0, sizeof(info
));
112 pipe_mutex_lock(*mutex
);
114 /* Early exit if we are sure the request will fail. */
117 pipe_mutex_unlock(*mutex
);
121 if (*owner
!= applier
) {
122 pipe_mutex_unlock(*mutex
);
127 /* Pass through the request to the kernel. */
128 info
.value
= (unsigned long)&value
;
129 info
.request
= request
;
130 if (drmCommandWriteRead(applier
->ws
->fd
, DRM_RADEON_INFO
,
131 &info
, sizeof(info
)) != 0) {
132 pipe_mutex_unlock(*mutex
);
136 /* Update the rights in the winsys. */
140 printf("radeon: Acquired access to %s.\n", request_name
);
141 pipe_mutex_unlock(*mutex
);
146 printf("radeon: Released access to %s.\n", request_name
);
149 pipe_mutex_unlock(*mutex
);
153 static boolean
radeon_get_drm_value(int fd
, unsigned request
,
154 const char *errname
, uint32_t *out
)
156 struct drm_radeon_info info
;
159 memset(&info
, 0, sizeof(info
));
161 info
.value
= (unsigned long)out
;
162 info
.request
= request
;
164 retval
= drmCommandWriteRead(fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
167 fprintf(stderr
, "radeon: Failed to get %s, error number %d\n",
175 /* Helper function to do the ioctls needed for setup and init. */
176 static boolean
do_winsys_init(struct radeon_drm_winsys
*ws
)
178 struct drm_radeon_gem_info gem_info
;
180 drmVersionPtr version
;
182 memset(&gem_info
, 0, sizeof(gem_info
));
184 /* We do things in a specific order here.
186 * DRM version first. We need to be sure we're running on a KMS chipset.
187 * This is also for some features.
189 * Then, the PCI ID. This is essential and should return usable numbers
190 * for all Radeons. If this fails, we probably got handed an FD for some
193 * The GEM info is actually bogus on the kernel side, as well as our side
194 * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
195 * we don't actually use the info for anything yet.
197 * The GB and Z pipe requests should always succeed, but they might not
198 * return sensical values for all chipsets, but that's alright because
199 * the pipe drivers already know that.
202 /* Get DRM version. */
203 version
= drmGetVersion(ws
->fd
);
204 if (version
->version_major
!= 2 ||
205 version
->version_minor
< 3) {
206 fprintf(stderr
, "%s: DRM version is %d.%d.%d but this driver is "
207 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
209 version
->version_major
,
210 version
->version_minor
,
211 version
->version_patchlevel
);
212 drmFreeVersion(version
);
216 ws
->info
.drm_major
= version
->version_major
;
217 ws
->info
.drm_minor
= version
->version_minor
;
218 ws
->info
.drm_patchlevel
= version
->version_patchlevel
;
219 drmFreeVersion(version
);
222 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_DEVICE_ID
, "PCI ID",
227 switch (ws
->info
.pci_id
) {
228 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
229 #include "pci_ids/r300_pci_ids.h"
232 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
233 #include "pci_ids/r600_pci_ids.h"
236 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
237 #include "pci_ids/radeonsi_pci_ids.h"
241 fprintf(stderr
, "radeon: Invalid PCI ID.\n");
245 switch (ws
->info
.family
) {
248 fprintf(stderr
, "radeon: Unknown family.\n");
258 ws
->info
.chip_class
= R300
;
260 case CHIP_R420
: /* R4xx-based cores. */
269 ws
->info
.chip_class
= R400
;
271 case CHIP_RV515
: /* R5xx-based cores. */
277 ws
->info
.chip_class
= R500
;
287 ws
->info
.chip_class
= R600
;
293 ws
->info
.chip_class
= R700
;
306 ws
->info
.chip_class
= EVERGREEN
;
310 ws
->info
.chip_class
= CAYMAN
;
316 ws
->info
.chip_class
= TAHITI
;
321 ws
->info
.r600_has_dma
= FALSE
;
322 if (ws
->info
.chip_class
>= R700
&& ws
->info
.drm_minor
>= 27) {
323 ws
->info
.r600_has_dma
= TRUE
;
327 retval
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_INFO
,
328 &gem_info
, sizeof(gem_info
));
330 fprintf(stderr
, "radeon: Failed to get MM info, error number %d\n",
334 ws
->info
.gart_size
= gem_info
.gart_size
;
335 ws
->info
.vram_size
= gem_info
.vram_size
;
337 ws
->num_cpus
= sysconf(_SC_NPROCESSORS_ONLN
);
339 /* Generation-specific queries. */
340 if (ws
->gen
== DRV_R300
) {
341 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_GB_PIPES
,
343 &ws
->info
.r300_num_gb_pipes
))
346 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_Z_PIPES
,
348 &ws
->info
.r300_num_z_pipes
))
351 else if (ws
->gen
>= DRV_R600
) {
352 if (ws
->info
.drm_minor
>= 9 &&
353 !radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BACKENDS
,
355 &ws
->info
.r600_num_backends
))
358 /* get the GPU counter frequency, failure is not fatal */
359 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CLOCK_CRYSTAL_FREQ
, NULL
,
360 &ws
->info
.r600_clock_crystal_freq
);
362 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TILING_CONFIG
, NULL
,
363 &ws
->info
.r600_tiling_config
);
365 if (ws
->info
.drm_minor
>= 11) {
366 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_TILE_PIPES
, NULL
,
367 &ws
->info
.r600_num_tile_pipes
);
369 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_BACKEND_MAP
, NULL
,
370 &ws
->info
.r600_backend_map
))
371 ws
->info
.r600_backend_map_valid
= TRUE
;
374 ws
->info
.r600_virtual_address
= FALSE
;
375 if (ws
->info
.drm_minor
>= 13) {
376 ws
->info
.r600_virtual_address
= TRUE
;
377 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_VA_START
, NULL
,
378 &ws
->info
.r600_va_start
))
379 ws
->info
.r600_virtual_address
= FALSE
;
380 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_IB_VM_MAX_SIZE
, NULL
,
381 &ws
->info
.r600_ib_vm_max_size
))
382 ws
->info
.r600_virtual_address
= FALSE
;
386 /* Get max pipes, this is only needed for compute shaders. All evergreen+
387 * chips have at least 2 pipes, so we use 2 as a default. */
388 ws
->info
.r600_max_pipes
= 2;
389 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_PIPES
, NULL
,
390 &ws
->info
.r600_max_pipes
);
395 static void radeon_winsys_destroy(struct radeon_winsys
*rws
)
397 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
401 pipe_semaphore_signal(&ws
->cs_queued
);
402 pipe_thread_wait(ws
->thread
);
404 pipe_semaphore_destroy(&ws
->cs_queued
);
405 pipe_condvar_destroy(ws
->cs_queue_empty
);
407 if (!pipe_reference(&ws
->base
.reference
, NULL
)) {
411 pipe_mutex_destroy(ws
->hyperz_owner_mutex
);
412 pipe_mutex_destroy(ws
->cmask_owner_mutex
);
413 pipe_mutex_destroy(ws
->cs_stack_lock
);
415 ws
->cman
->destroy(ws
->cman
);
416 ws
->kman
->destroy(ws
->kman
);
417 if (ws
->gen
>= DRV_R600
) {
418 radeon_surface_manager_free(ws
->surf_man
);
421 util_hash_table_remove(fd_tab
, intptr_to_pointer(ws
->fd
));
426 static void radeon_query_info(struct radeon_winsys
*rws
,
427 struct radeon_info
*info
)
429 *info
= ((struct radeon_drm_winsys
*)rws
)->info
;
432 static boolean
radeon_cs_request_feature(struct radeon_winsys_cs
*rcs
,
433 enum radeon_feature_id fid
,
436 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
439 case RADEON_FID_R300_HYPERZ_ACCESS
:
440 return radeon_set_fd_access(cs
, &cs
->ws
->hyperz_owner
,
441 &cs
->ws
->hyperz_owner_mutex
,
442 RADEON_INFO_WANT_HYPERZ
, "Hyper-Z",
445 case RADEON_FID_R300_CMASK_ACCESS
:
446 return radeon_set_fd_access(cs
, &cs
->ws
->cmask_owner
,
447 &cs
->ws
->cmask_owner_mutex
,
448 RADEON_INFO_WANT_CMASK
, "AA optimizations",
454 static int radeon_drm_winsys_surface_init(struct radeon_winsys
*rws
,
455 struct radeon_surface
*surf
)
457 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
459 return radeon_surface_init(ws
->surf_man
, surf
);
462 static int radeon_drm_winsys_surface_best(struct radeon_winsys
*rws
,
463 struct radeon_surface
*surf
)
465 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
467 return radeon_surface_best(ws
->surf_man
, surf
);
470 static uint64_t radeon_query_timestamp(struct radeon_winsys
*rws
)
472 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
475 if (ws
->info
.drm_minor
< 20 ||
476 ws
->gen
< DRV_R600
) {
481 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TIMESTAMP
, "timestamp",
486 static uint64_t radeon_query_value(struct radeon_winsys
*rws
,
487 enum radeon_value_id value
)
489 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
492 case RADEON_REQUESTED_VRAM_MEMORY
:
493 return ws
->allocated_vram
;
494 case RADEON_REQUESTED_GTT_MEMORY
:
495 return ws
->allocated_gtt
;
500 static unsigned hash_fd(void *key
)
502 return pointer_to_intptr(key
);
505 static int compare_fd(void *key1
, void *key2
)
507 return pointer_to_intptr(key1
) != pointer_to_intptr(key2
);
510 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys
*ws
, struct radeon_drm_cs
*cs
)
513 pipe_mutex_lock(ws
->cs_stack_lock
);
514 if (p_atomic_read(&ws
->ncs
) >= RING_LAST
) {
515 /* no room left for a flush */
516 pipe_mutex_unlock(ws
->cs_stack_lock
);
519 ws
->cs_stack
[p_atomic_read(&ws
->ncs
)] = cs
;
520 p_atomic_inc(&ws
->ncs
);
521 pipe_mutex_unlock(ws
->cs_stack_lock
);
522 pipe_semaphore_signal(&ws
->cs_queued
);
525 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl
, param
)
527 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)param
;
528 struct radeon_drm_cs
*cs
;
529 unsigned i
, empty_stack
;
532 pipe_semaphore_wait(&ws
->cs_queued
);
536 pipe_mutex_lock(ws
->cs_stack_lock
);
537 cs
= ws
->cs_stack
[0];
538 pipe_mutex_unlock(ws
->cs_stack_lock
);
541 radeon_drm_cs_emit_ioctl_oneshot(cs
->cst
);
543 pipe_mutex_lock(ws
->cs_stack_lock
);
544 for (i
= 1; i
< p_atomic_read(&ws
->ncs
); i
++) {
545 ws
->cs_stack
[i
- 1] = ws
->cs_stack
[i
];
547 ws
->cs_stack
[p_atomic_read(&ws
->ncs
) - 1] = NULL
;
548 empty_stack
= p_atomic_dec_zero(&ws
->ncs
);
550 pipe_condvar_signal(ws
->cs_queue_empty
);
552 pipe_mutex_unlock(ws
->cs_stack_lock
);
554 pipe_semaphore_signal(&cs
->flush_completed
);
561 pipe_mutex_lock(ws
->cs_stack_lock
);
562 for (i
= 0; i
< p_atomic_read(&ws
->ncs
); i
++) {
563 pipe_semaphore_signal(&ws
->cs_stack
[i
]->flush_completed
);
564 ws
->cs_stack
[i
] = NULL
;
566 p_atomic_set(&ws
->ncs
, 0);
567 pipe_condvar_signal(ws
->cs_queue_empty
);
568 pipe_mutex_unlock(ws
->cs_stack_lock
);
572 DEBUG_GET_ONCE_BOOL_OPTION(thread
, "RADEON_THREAD", TRUE
)
573 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl
, param
);
575 struct radeon_winsys
*radeon_drm_winsys_create(int fd
)
577 struct radeon_drm_winsys
*ws
;
580 fd_tab
= util_hash_table_create(hash_fd
, compare_fd
);
583 ws
= util_hash_table_get(fd_tab
, intptr_to_pointer(fd
));
585 pipe_reference(NULL
, &ws
->base
.reference
);
589 ws
= CALLOC_STRUCT(radeon_drm_winsys
);
594 util_hash_table_set(fd_tab
, intptr_to_pointer(fd
), ws
);
596 if (!do_winsys_init(ws
))
599 /* Create managers. */
600 ws
->kman
= radeon_bomgr_create(ws
);
603 ws
->cman
= pb_cache_manager_create(ws
->kman
, 1000000);
607 if (ws
->gen
>= DRV_R600
) {
608 ws
->surf_man
= radeon_surface_manager_new(fd
);
614 pipe_reference_init(&ws
->base
.reference
, 1);
617 ws
->base
.destroy
= radeon_winsys_destroy
;
618 ws
->base
.query_info
= radeon_query_info
;
619 ws
->base
.cs_request_feature
= radeon_cs_request_feature
;
620 ws
->base
.surface_init
= radeon_drm_winsys_surface_init
;
621 ws
->base
.surface_best
= radeon_drm_winsys_surface_best
;
622 ws
->base
.query_timestamp
= radeon_query_timestamp
;
623 ws
->base
.query_value
= radeon_query_value
;
625 radeon_bomgr_init_functions(ws
);
626 radeon_drm_cs_init_functions(ws
);
628 pipe_mutex_init(ws
->hyperz_owner_mutex
);
629 pipe_mutex_init(ws
->cmask_owner_mutex
);
630 pipe_mutex_init(ws
->cs_stack_lock
);
632 p_atomic_set(&ws
->ncs
, 0);
633 pipe_semaphore_init(&ws
->cs_queued
, 0);
634 pipe_condvar_init(ws
->cs_queue_empty
);
635 if (ws
->num_cpus
> 1 && debug_get_option_thread())
636 ws
->thread
= pipe_thread_create(radeon_drm_cs_emit_ioctl
, ws
);
642 ws
->cman
->destroy(ws
->cman
);
644 ws
->kman
->destroy(ws
->kman
);
646 radeon_surface_manager_free(ws
->surf_man
);