src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "util/u_memory.h"
  39 #include "util/u_hash_table.h"
  40
  41 #include <xf86drm.h>
  42 #include <stdio.h>
  43 #include <sys/types.h>
  44 #include <sys/stat.h>
  45 #include <unistd.h>
  46 #include <radeon_surface.h>
  47
  48 #ifndef RADEON_INFO_ACTIVE_CU_COUNT
  49 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
  50 #endif
  51
  52 #ifndef RADEON_INFO_CURRENT_GPU_TEMP
  53 #define RADEON_INFO_CURRENT_GPU_TEMP    0x21
  54 #define RADEON_INFO_CURRENT_GPU_SCLK    0x22
  55 #define RADEON_INFO_CURRENT_GPU_MCLK    0x23
  56 #define RADEON_INFO_READ_REG            0x24
  57 #endif
  58
  59 #define RADEON_INFO_VA_UNMAP_WORKING    0x25
  60
  61 #ifndef RADEON_INFO_GPU_RESET_COUNTER
  62 #define RADEON_INFO_GPU_RESET_COUNTER   0x26
  63 #endif
  64
  65 static struct util_hash_table *fd_tab = NULL;
  66 pipe_static_mutex(fd_tab_mutex);
  67
  68 /* Enable/disable feature access for one command stream.
  69  * If enable == true, return true on success.
  70  * Otherwise, return false.
  71  *
  72  * We basically do the same thing kernel does, because we have to deal
  73  * with multiple contexts (here command streams) backed by one winsys. */
  74 static bool radeon_set_fd_access(struct radeon_drm_cs *applier,
  75                                  struct radeon_drm_cs **owner,
  76                                  pipe_mutex *mutex,
  77                                  unsigned request, const char *request_name,
  78                                  bool enable)
  79 {
  80     struct drm_radeon_info info;
  81     unsigned value = enable ? 1 : 0;
  82
  83     memset(&info, 0, sizeof(info));
  84
  85     pipe_mutex_lock(*mutex);
  86
  87     /* Early exit if we are sure the request will fail. */
  88     if (enable) {
  89         if (*owner) {
  90             pipe_mutex_unlock(*mutex);
  91             return false;
  92         }
  93     } else {
  94         if (*owner != applier) {
  95             pipe_mutex_unlock(*mutex);
  96             return false;
  97         }
  98     }
  99
 100     /* Pass through the request to the kernel. */
 101     info.value = (unsigned long)&value;
 102     info.request = request;
 103     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
 104                             &info, sizeof(info)) != 0) {
 105         pipe_mutex_unlock(*mutex);
 106         return false;
 107     }
 108
 109     /* Update the rights in the winsys. */
 110     if (enable) {
 111         if (value) {
 112             *owner = applier;
 113             pipe_mutex_unlock(*mutex);
 114             return true;
 115         }
 116     } else {
 117         *owner = NULL;
 118     }
 119
 120     pipe_mutex_unlock(*mutex);
 121     return false;
 122 }
 123
 124 static bool radeon_get_drm_value(int fd, unsigned request,
 125                                  const char *errname, uint32_t *out)
 126 {
 127     struct drm_radeon_info info;
 128     int retval;
 129
 130     memset(&info, 0, sizeof(info));
 131
 132     info.value = (unsigned long)out;
 133     info.request = request;
 134
 135     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 136     if (retval) {
 137         if (errname) {
 138             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 139                     errname, retval);
 140         }
 141         return false;
 142     }
 143     return true;
 144 }
 145
 146 /* Helper function to do the ioctls needed for setup and init. */
 147 static bool do_winsys_init(struct radeon_drm_winsys *ws)
 148 {
 149     struct drm_radeon_gem_info gem_info;
 150     int retval;
 151     drmVersionPtr version;
 152
 153     memset(&gem_info, 0, sizeof(gem_info));
 154
 155     /* We do things in a specific order here.
 156      *
 157      * DRM version first. We need to be sure we're running on a KMS chipset.
 158      * This is also for some features.
 159      *
 160      * Then, the PCI ID. This is essential and should return usable numbers
 161      * for all Radeons. If this fails, we probably got handed an FD for some
 162      * non-Radeon card.
 163      *
 164      * The GEM info is actually bogus on the kernel side, as well as our side
 165      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 166      * we don't actually use the info for anything yet.
 167      *
 168      * The GB and Z pipe requests should always succeed, but they might not
 169      * return sensical values for all chipsets, but that's alright because
 170      * the pipe drivers already know that.
 171      */
 172
 173     /* Get DRM version. */
 174     version = drmGetVersion(ws->fd);
 175     if (version->version_major != 2 ||
 176         version->version_minor < 12) {
 177         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 178                 "only compatible with 2.12.0 (kernel 3.2) or later.\n",
 179                 __FUNCTION__,
 180                 version->version_major,
 181                 version->version_minor,
 182                 version->version_patchlevel);
 183         drmFreeVersion(version);
 184         return false;
 185     }
 186
 187     ws->info.drm_major = version->version_major;
 188     ws->info.drm_minor = version->version_minor;
 189     ws->info.drm_patchlevel = version->version_patchlevel;
 190     drmFreeVersion(version);
 191
 192     /* Get PCI ID. */
 193     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 194                               &ws->info.pci_id))
 195         return false;
 196
 197     /* Check PCI ID. */
 198     switch (ws->info.pci_id) {
 199 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 200 #include "pci_ids/r300_pci_ids.h"
 201 #undef CHIPSET
 202
 203 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 204 #include "pci_ids/r600_pci_ids.h"
 205 #undef CHIPSET
 206
 207 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 208 #include "pci_ids/radeonsi_pci_ids.h"
 209 #undef CHIPSET
 210
 211     default:
 212         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 213         return false;
 214     }
 215
 216     switch (ws->info.family) {
 217     default:
 218     case CHIP_UNKNOWN:
 219         fprintf(stderr, "radeon: Unknown family.\n");
 220         return false;
 221     case CHIP_R300:
 222     case CHIP_R350:
 223     case CHIP_RV350:
 224     case CHIP_RV370:
 225     case CHIP_RV380:
 226     case CHIP_RS400:
 227     case CHIP_RC410:
 228     case CHIP_RS480:
 229         ws->info.chip_class = R300;
 230         break;
 231     case CHIP_R420:     /* R4xx-based cores. */
 232     case CHIP_R423:
 233     case CHIP_R430:
 234     case CHIP_R480:
 235     case CHIP_R481:
 236     case CHIP_RV410:
 237     case CHIP_RS600:
 238     case CHIP_RS690:
 239     case CHIP_RS740:
 240         ws->info.chip_class = R400;
 241         break;
 242     case CHIP_RV515:    /* R5xx-based cores. */
 243     case CHIP_R520:
 244     case CHIP_RV530:
 245     case CHIP_R580:
 246     case CHIP_RV560:
 247     case CHIP_RV570:
 248         ws->info.chip_class = R500;
 249         break;
 250     case CHIP_R600:
 251     case CHIP_RV610:
 252     case CHIP_RV630:
 253     case CHIP_RV670:
 254     case CHIP_RV620:
 255     case CHIP_RV635:
 256     case CHIP_RS780:
 257     case CHIP_RS880:
 258         ws->info.chip_class = R600;
 259         break;
 260     case CHIP_RV770:
 261     case CHIP_RV730:
 262     case CHIP_RV710:
 263     case CHIP_RV740:
 264         ws->info.chip_class = R700;
 265         break;
 266     case CHIP_CEDAR:
 267     case CHIP_REDWOOD:
 268     case CHIP_JUNIPER:
 269     case CHIP_CYPRESS:
 270     case CHIP_HEMLOCK:
 271     case CHIP_PALM:
 272     case CHIP_SUMO:
 273     case CHIP_SUMO2:
 274     case CHIP_BARTS:
 275     case CHIP_TURKS:
 276     case CHIP_CAICOS:
 277         ws->info.chip_class = EVERGREEN;
 278         break;
 279     case CHIP_CAYMAN:
 280     case CHIP_ARUBA:
 281         ws->info.chip_class = CAYMAN;
 282         break;
 283     case CHIP_TAHITI:
 284     case CHIP_PITCAIRN:
 285     case CHIP_VERDE:
 286     case CHIP_OLAND:
 287     case CHIP_HAINAN:
 288         ws->info.chip_class = SI;
 289         break;
 290     case CHIP_BONAIRE:
 291     case CHIP_KAVERI:
 292     case CHIP_KABINI:
 293     case CHIP_HAWAII:
 294     case CHIP_MULLINS:
 295         ws->info.chip_class = CIK;
 296         break;
 297     }
 298
 299     /* Set which chips don't have dedicated VRAM. */
 300     switch (ws->info.family) {
 301     case CHIP_RS400:
 302     case CHIP_RC410:
 303     case CHIP_RS480:
 304     case CHIP_RS600:
 305     case CHIP_RS690:
 306     case CHIP_RS740:
 307     case CHIP_RS780:
 308     case CHIP_RS880:
 309     case CHIP_PALM:
 310     case CHIP_SUMO:
 311     case CHIP_SUMO2:
 312     case CHIP_ARUBA:
 313     case CHIP_KAVERI:
 314     case CHIP_KABINI:
 315     case CHIP_MULLINS:
 316        ws->info.has_dedicated_vram = false;
 317        break;
 318
 319     default:
 320        ws->info.has_dedicated_vram = true;
 321     }
 322
 323     /* Check for dma */
 324     ws->info.has_sdma = false;
 325     /* DMA is disabled on R700. There is IB corruption and hangs. */
 326     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 327         ws->info.has_sdma = true;
 328     }
 329
 330     /* Check for UVD and VCE */
 331     ws->info.has_uvd = false;
 332     ws->info.vce_fw_version = 0x00000000;
 333     if (ws->info.drm_minor >= 32) {
 334         uint32_t value = RADEON_CS_RING_UVD;
 335         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 336                                  "UVD Ring working", &value))
 337             ws->info.has_uvd = value;
 338
 339         value = RADEON_CS_RING_VCE;
 340         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 341                                  NULL, &value) && value) {
 342
 343             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 344                                      "VCE FW version", &value))
 345                 ws->info.vce_fw_version = value;
 346         }
 347     }
 348
 349     /* Check for userptr support. */
 350     {
 351         struct drm_radeon_gem_userptr args = {0};
 352
 353         /* If the ioctl doesn't exist, -EINVAL is returned.
 354          *
 355          * If the ioctl exists, it should return -EACCES
 356          * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
 357          * aren't set.
 358          */
 359         ws->info.has_userptr =
 360             drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
 361                                 &args, sizeof(args)) == -EACCES;
 362     }
 363
 364     /* Get GEM info. */
 365     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 366             &gem_info, sizeof(gem_info));
 367     if (retval) {
 368         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 369                 retval);
 370         return false;
 371     }
 372     ws->info.gart_size = gem_info.gart_size;
 373     ws->info.vram_size = gem_info.vram_size;
 374
 375     ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size);
 376     if (ws->info.drm_minor < 40)
 377         ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
 378
 379     /* Get max clock frequency info and convert it to MHz */
 380     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 381                          &ws->info.max_shader_clock);
 382     ws->info.max_shader_clock /= 1000;
 383
 384     radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
 385                          &ws->info.enabled_rb_mask);
 386
 387     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 388
 389     /* Generation-specific queries. */
 390     if (ws->gen == DRV_R300) {
 391         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 392                                   "GB pipe count",
 393                                   &ws->info.r300_num_gb_pipes))
 394             return false;
 395
 396         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 397                                   "Z pipe count",
 398                                   &ws->info.r300_num_z_pipes))
 399             return false;
 400     }
 401     else if (ws->gen >= DRV_R600) {
 402         uint32_t tiling_config = 0;
 403
 404         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 405                                   "num backends",
 406                                   &ws->info.num_render_backends))
 407             return false;
 408
 409         /* get the GPU counter frequency, failure is not fatal */
 410         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 411                              &ws->info.clock_crystal_freq);
 412
 413         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 414                              &tiling_config);
 415
 416         ws->info.r600_num_banks =
 417             ws->info.chip_class >= EVERGREEN ?
 418                 4 << ((tiling_config & 0xf0) >> 4) :
 419                 4 << ((tiling_config & 0x30) >> 4);
 420
 421         ws->info.pipe_interleave_bytes =
 422             ws->info.chip_class >= EVERGREEN ?
 423                 256 << ((tiling_config & 0xf00) >> 8) :
 424                 256 << ((tiling_config & 0xc0) >> 6);
 425
 426         if (!ws->info.pipe_interleave_bytes)
 427             ws->info.pipe_interleave_bytes =
 428                 ws->info.chip_class >= EVERGREEN ? 512 : 256;
 429
 430         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 431                              &ws->info.num_tile_pipes);
 432
 433         /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
 434          * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
 435          * reports a different value (12). Fix it by setting what's in the
 436          * GB_TILE_MODE array (8).
 437          */
 438         if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
 439             ws->info.num_tile_pipes = 8;
 440
 441         if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 442                                   &ws->info.r600_gb_backend_map))
 443             ws->info.r600_gb_backend_map_valid = true;
 444
 445         ws->info.has_virtual_memory = false;
 446         if (ws->info.drm_minor >= 13) {
 447             uint32_t ib_vm_max_size;
 448
 449             ws->info.has_virtual_memory = true;
 450             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 451                                       &ws->va_start))
 452                 ws->info.has_virtual_memory = false;
 453             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 454                                       &ib_vm_max_size))
 455                 ws->info.has_virtual_memory = false;
 456             radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
 457                                  &ws->va_unmap_working);
 458         }
 459         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false))
 460                 ws->info.has_virtual_memory = false;
 461     }
 462
 463     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 464      * chips have at least 2 pipes, so we use 2 as a default. */
 465     ws->info.r600_max_quad_pipes = 2;
 466     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 467                          &ws->info.r600_max_quad_pipes);
 468
 469     /* All GPUs have at least one compute unit */
 470     ws->info.num_good_compute_units = 1;
 471     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 472                          &ws->info.num_good_compute_units);
 473
 474     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 475                          &ws->info.max_se);
 476
 477     if (!ws->info.max_se) {
 478         switch (ws->info.family) {
 479         default:
 480             ws->info.max_se = 1;
 481             break;
 482         case CHIP_CYPRESS:
 483         case CHIP_HEMLOCK:
 484         case CHIP_BARTS:
 485         case CHIP_CAYMAN:
 486         case CHIP_TAHITI:
 487         case CHIP_PITCAIRN:
 488         case CHIP_BONAIRE:
 489             ws->info.max_se = 2;
 490             break;
 491         case CHIP_HAWAII:
 492             ws->info.max_se = 4;
 493             break;
 494         }
 495     }
 496
 497     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 498                          &ws->info.max_sh_per_se);
 499
 500     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 501                          &ws->accel_working2);
 502     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 503         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 504                 "returned accel_working2 value %u is smaller than 2. "
 505                 "Please install a newer kernel.\n",
 506                 ws->accel_working2);
 507         return false;
 508     }
 509
 510     if (ws->info.chip_class == CIK) {
 511         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 512                                   ws->info.cik_macrotile_mode_array)) {
 513             fprintf(stderr, "radeon: Kernel 3.13 is required for CIK support.\n");
 514             return false;
 515         }
 516     }
 517
 518     if (ws->info.chip_class >= SI) {
 519         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 520                                   ws->info.si_tile_mode_array)) {
 521             fprintf(stderr, "radeon: Kernel 3.10 is required for SI support.\n");
 522             return false;
 523         }
 524     }
 525
 526     /* Hawaii with old firmware needs type2 nop packet.
 527      * accel_working2 with value 3 indicates the new firmware.
 528      */
 529     ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI ||
 530                                      (ws->info.family == CHIP_HAWAII &&
 531                                       ws->accel_working2 < 3);
 532
 533     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
 534
 535     return true;
 536 }
 537
 538 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 539 {
 540     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 541
 542     if (util_queue_is_initialized(&ws->cs_queue))
 543         util_queue_destroy(&ws->cs_queue);
 544
 545     pipe_mutex_destroy(ws->hyperz_owner_mutex);
 546     pipe_mutex_destroy(ws->cmask_owner_mutex);
 547
 548     pb_cache_deinit(&ws->bo_cache);
 549
 550     if (ws->gen >= DRV_R600) {
 551         radeon_surface_manager_free(ws->surf_man);
 552     }
 553
 554     util_hash_table_destroy(ws->bo_names);
 555     util_hash_table_destroy(ws->bo_handles);
 556     util_hash_table_destroy(ws->bo_vas);
 557     pipe_mutex_destroy(ws->bo_handles_mutex);
 558     pipe_mutex_destroy(ws->bo_va_mutex);
 559     pipe_mutex_destroy(ws->bo_fence_lock);
 560
 561     if (ws->fd >= 0)
 562         close(ws->fd);
 563
 564     FREE(rws);
 565 }
 566
 567 static void radeon_query_info(struct radeon_winsys *rws,
 568                               struct radeon_info *info)
 569 {
 570     *info = ((struct radeon_drm_winsys *)rws)->info;
 571 }
 572
 573 static bool radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 574                                       enum radeon_feature_id fid,
 575                                       bool enable)
 576 {
 577     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 578
 579     switch (fid) {
 580     case RADEON_FID_R300_HYPERZ_ACCESS:
 581         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 582                                     &cs->ws->hyperz_owner_mutex,
 583                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 584                                     enable);
 585
 586     case RADEON_FID_R300_CMASK_ACCESS:
 587         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 588                                     &cs->ws->cmask_owner_mutex,
 589                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 590                                     enable);
 591     }
 592     return false;
 593 }
 594
 595 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 596                                    enum radeon_value_id value)
 597 {
 598     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 599     uint64_t retval = 0;
 600
 601     switch (value) {
 602     case RADEON_REQUESTED_VRAM_MEMORY:
 603         return ws->allocated_vram;
 604     case RADEON_REQUESTED_GTT_MEMORY:
 605         return ws->allocated_gtt;
 606     case RADEON_MAPPED_VRAM:
 607        return ws->mapped_vram;
 608     case RADEON_MAPPED_GTT:
 609        return ws->mapped_gtt;
 610     case RADEON_BUFFER_WAIT_TIME_NS:
 611         return ws->buffer_wait_time;
 612     case RADEON_TIMESTAMP:
 613         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 614             assert(0);
 615             return 0;
 616         }
 617
 618         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 619                              (uint32_t*)&retval);
 620         return retval;
 621     case RADEON_NUM_CS_FLUSHES:
 622         return ws->num_cs_flushes;
 623     case RADEON_NUM_BYTES_MOVED:
 624         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 625                              "num-bytes-moved", (uint32_t*)&retval);
 626         return retval;
 627     case RADEON_NUM_EVICTIONS:
 628         return 0; /* unimplemented */
 629     case RADEON_VRAM_USAGE:
 630         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 631                              "vram-usage", (uint32_t*)&retval);
 632         return retval;
 633     case RADEON_GTT_USAGE:
 634         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 635                              "gtt-usage", (uint32_t*)&retval);
 636         return retval;
 637     case RADEON_GPU_TEMPERATURE:
 638         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
 639                              "gpu-temp", (uint32_t*)&retval);
 640         return retval;
 641     case RADEON_CURRENT_SCLK:
 642         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
 643                              "current-gpu-sclk", (uint32_t*)&retval);
 644         return retval;
 645     case RADEON_CURRENT_MCLK:
 646         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
 647                              "current-gpu-mclk", (uint32_t*)&retval);
 648         return retval;
 649     case RADEON_GPU_RESET_COUNTER:
 650         radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
 651                              "gpu-reset-counter", (uint32_t*)&retval);
 652         return retval;
 653     }
 654     return 0;
 655 }
 656
 657 static bool radeon_read_registers(struct radeon_winsys *rws,
 658                                   unsigned reg_offset,
 659                                   unsigned num_registers, uint32_t *out)
 660 {
 661     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 662     unsigned i;
 663
 664     for (i = 0; i < num_registers; i++) {
 665         uint32_t reg = reg_offset + i*4;
 666
 667         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg))
 668             return false;
 669         out[i] = reg;
 670     }
 671     return true;
 672 }
 673
 674 static unsigned hash_fd(void *key)
 675 {
 676     int fd = pointer_to_intptr(key);
 677     struct stat stat;
 678     fstat(fd, &stat);
 679
 680     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 681 }
 682
 683 static int compare_fd(void *key1, void *key2)
 684 {
 685     int fd1 = pointer_to_intptr(key1);
 686     int fd2 = pointer_to_intptr(key2);
 687     struct stat stat1, stat2;
 688     fstat(fd1, &stat1);
 689     fstat(fd2, &stat2);
 690
 691     return stat1.st_dev != stat2.st_dev ||
 692            stat1.st_ino != stat2.st_ino ||
 693            stat1.st_rdev != stat2.st_rdev;
 694 }
 695
 696 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", true)
 697
 698 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 699 {
 700     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 701     bool destroy;
 702
 703     /* When the reference counter drops to zero, remove the fd from the table.
 704      * This must happen while the mutex is locked, so that
 705      * radeon_drm_winsys_create in another thread doesn't get the winsys
 706      * from the table when the counter drops to 0. */
 707     pipe_mutex_lock(fd_tab_mutex);
 708
 709     destroy = pipe_reference(&rws->reference, NULL);
 710     if (destroy && fd_tab)
 711         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 712
 713     pipe_mutex_unlock(fd_tab_mutex);
 714     return destroy;
 715 }
 716
 717 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 718
 719 static unsigned handle_hash(void *key)
 720 {
 721     return PTR_TO_UINT(key);
 722 }
 723
 724 static int handle_compare(void *key1, void *key2)
 725 {
 726     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 727 }
 728
 729 PUBLIC struct radeon_winsys *
 730 radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
 731 {
 732     struct radeon_drm_winsys *ws;
 733
 734     pipe_mutex_lock(fd_tab_mutex);
 735     if (!fd_tab) {
 736         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 737     }
 738
 739     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 740     if (ws) {
 741         pipe_reference(NULL, &ws->reference);
 742         pipe_mutex_unlock(fd_tab_mutex);
 743         return &ws->base;
 744     }
 745
 746     ws = CALLOC_STRUCT(radeon_drm_winsys);
 747     if (!ws) {
 748         pipe_mutex_unlock(fd_tab_mutex);
 749         return NULL;
 750     }
 751
 752     ws->fd = dup(fd);
 753
 754     if (!do_winsys_init(ws))
 755         goto fail1;
 756
 757     pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
 758                   MIN2(ws->info.vram_size, ws->info.gart_size),
 759                   radeon_bo_destroy,
 760                   radeon_bo_can_reclaim);
 761
 762     if (ws->gen >= DRV_R600) {
 763         ws->surf_man = radeon_surface_manager_new(ws->fd);
 764         if (!ws->surf_man)
 765             goto fail;
 766     }
 767
 768     /* init reference */
 769     pipe_reference_init(&ws->reference, 1);
 770
 771     /* Set functions. */
 772     ws->base.unref = radeon_winsys_unref;
 773     ws->base.destroy = radeon_winsys_destroy;
 774     ws->base.query_info = radeon_query_info;
 775     ws->base.cs_request_feature = radeon_cs_request_feature;
 776     ws->base.query_value = radeon_query_value;
 777     ws->base.read_registers = radeon_read_registers;
 778
 779     radeon_drm_bo_init_functions(ws);
 780     radeon_drm_cs_init_functions(ws);
 781     radeon_surface_init_functions(ws);
 782
 783     pipe_mutex_init(ws->hyperz_owner_mutex);
 784     pipe_mutex_init(ws->cmask_owner_mutex);
 785
 786     ws->bo_names = util_hash_table_create(handle_hash, handle_compare);
 787     ws->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 788     ws->bo_vas = util_hash_table_create(handle_hash, handle_compare);
 789     pipe_mutex_init(ws->bo_handles_mutex);
 790     pipe_mutex_init(ws->bo_va_mutex);
 791     pipe_mutex_init(ws->bo_fence_lock);
 792     ws->va_offset = ws->va_start;
 793     list_inithead(&ws->va_holes);
 794
 795     /* TTM aligns the BO size to the CPU page size */
 796     ws->info.gart_page_size = sysconf(_SC_PAGESIZE);
 797
 798     if (ws->num_cpus > 1 && debug_get_option_thread())
 799         util_queue_init(&ws->cs_queue, "radeon_cs", 8, 1);
 800
 801     /* Create the screen at the end. The winsys must be initialized
 802      * completely.
 803      *
 804      * Alternatively, we could create the screen based on "ws->gen"
 805      * and link all drivers into one binary blob. */
 806     ws->base.screen = screen_create(&ws->base);
 807     if (!ws->base.screen) {
 808         radeon_winsys_destroy(&ws->base);
 809         pipe_mutex_unlock(fd_tab_mutex);
 810         return NULL;
 811     }
 812
 813     util_hash_table_set(fd_tab, intptr_to_pointer(ws->fd), ws);
 814
 815     /* We must unlock the mutex once the winsys is fully initialized, so that
 816      * other threads attempting to create the winsys from the same fd will
 817      * get a fully initialized winsys and not just half-way initialized. */
 818     pipe_mutex_unlock(fd_tab_mutex);
 819
 820     return &ws->base;
 821
 822 fail:
 823     pb_cache_deinit(&ws->bo_cache);
 824 fail1:
 825     pipe_mutex_unlock(fd_tab_mutex);
 826     if (ws->surf_man)
 827         radeon_surface_manager_free(ws->surf_man);
 828     if (ws->fd >= 0)
 829         close(ws->fd);
 830
 831     FREE(ws);
 832     return NULL;
 833 }