src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "pipebuffer/pb_bufmgr.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_hash_table.h"
  41
  42 #include <xf86drm.h>
  43 #include <stdio.h>
  44 #include <sys/types.h>
  45 #include <sys/stat.h>
  46 #include <unistd.h>
  47
  48 #ifndef RADEON_INFO_ACTIVE_CU_COUNT
  49 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
  50 #endif
  51
  52 static struct util_hash_table *fd_tab = NULL;
  53 pipe_static_mutex(fd_tab_mutex);
  54
  55 /* Enable/disable feature access for one command stream.
  56  * If enable == TRUE, return TRUE on success.
  57  * Otherwise, return FALSE.
  58  *
  59  * We basically do the same thing kernel does, because we have to deal
  60  * with multiple contexts (here command streams) backed by one winsys. */
  61 static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
  62                                     struct radeon_drm_cs **owner,
  63                                     pipe_mutex *mutex,
  64                                     unsigned request, const char *request_name,
  65                                     boolean enable)
  66 {
  67     struct drm_radeon_info info;
  68     unsigned value = enable ? 1 : 0;
  69
  70     memset(&info, 0, sizeof(info));
  71
  72     pipe_mutex_lock(*mutex);
  73
  74     /* Early exit if we are sure the request will fail. */
  75     if (enable) {
  76         if (*owner) {
  77             pipe_mutex_unlock(*mutex);
  78             return FALSE;
  79         }
  80     } else {
  81         if (*owner != applier) {
  82             pipe_mutex_unlock(*mutex);
  83             return FALSE;
  84         }
  85     }
  86
  87     /* Pass through the request to the kernel. */
  88     info.value = (unsigned long)&value;
  89     info.request = request;
  90     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
  91                             &info, sizeof(info)) != 0) {
  92         pipe_mutex_unlock(*mutex);
  93         return FALSE;
  94     }
  95
  96     /* Update the rights in the winsys. */
  97     if (enable) {
  98         if (value) {
  99             *owner = applier;
 100             pipe_mutex_unlock(*mutex);
 101             return TRUE;
 102         }
 103     } else {
 104         *owner = NULL;
 105     }
 106
 107     pipe_mutex_unlock(*mutex);
 108     return FALSE;
 109 }
 110
 111 static boolean radeon_get_drm_value(int fd, unsigned request,
 112                                     const char *errname, uint32_t *out)
 113 {
 114     struct drm_radeon_info info;
 115     int retval;
 116
 117     memset(&info, 0, sizeof(info));
 118
 119     info.value = (unsigned long)out;
 120     info.request = request;
 121
 122     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 123     if (retval) {
 124         if (errname) {
 125             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 126                     errname, retval);
 127         }
 128         return FALSE;
 129     }
 130     return TRUE;
 131 }
 132
 133 /* Helper function to do the ioctls needed for setup and init. */
 134 static boolean do_winsys_init(struct radeon_drm_winsys *ws)
 135 {
 136     struct drm_radeon_gem_info gem_info;
 137     int retval;
 138     drmVersionPtr version;
 139
 140     memset(&gem_info, 0, sizeof(gem_info));
 141
 142     /* We do things in a specific order here.
 143      *
 144      * DRM version first. We need to be sure we're running on a KMS chipset.
 145      * This is also for some features.
 146      *
 147      * Then, the PCI ID. This is essential and should return usable numbers
 148      * for all Radeons. If this fails, we probably got handed an FD for some
 149      * non-Radeon card.
 150      *
 151      * The GEM info is actually bogus on the kernel side, as well as our side
 152      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 153      * we don't actually use the info for anything yet.
 154      *
 155      * The GB and Z pipe requests should always succeed, but they might not
 156      * return sensical values for all chipsets, but that's alright because
 157      * the pipe drivers already know that.
 158      */
 159
 160     /* Get DRM version. */
 161     version = drmGetVersion(ws->fd);
 162     if (version->version_major != 2 ||
 163         version->version_minor < 3) {
 164         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 165                 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
 166                 __FUNCTION__,
 167                 version->version_major,
 168                 version->version_minor,
 169                 version->version_patchlevel);
 170         drmFreeVersion(version);
 171         return FALSE;
 172     }
 173
 174     ws->info.drm_major = version->version_major;
 175     ws->info.drm_minor = version->version_minor;
 176     ws->info.drm_patchlevel = version->version_patchlevel;
 177     drmFreeVersion(version);
 178
 179     /* Get PCI ID. */
 180     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 181                               &ws->info.pci_id))
 182         return FALSE;
 183
 184     /* Check PCI ID. */
 185     switch (ws->info.pci_id) {
 186 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 187 #include "pci_ids/r300_pci_ids.h"
 188 #undef CHIPSET
 189
 190 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 191 #include "pci_ids/r600_pci_ids.h"
 192 #undef CHIPSET
 193
 194 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 195 #include "pci_ids/radeonsi_pci_ids.h"
 196 #undef CHIPSET
 197
 198     default:
 199         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 200         return FALSE;
 201     }
 202
 203     switch (ws->info.family) {
 204     default:
 205     case CHIP_UNKNOWN:
 206         fprintf(stderr, "radeon: Unknown family.\n");
 207         return FALSE;
 208     case CHIP_R300:
 209     case CHIP_R350:
 210     case CHIP_RV350:
 211     case CHIP_RV370:
 212     case CHIP_RV380:
 213     case CHIP_RS400:
 214     case CHIP_RC410:
 215     case CHIP_RS480:
 216         ws->info.chip_class = R300;
 217         break;
 218     case CHIP_R420:     /* R4xx-based cores. */
 219     case CHIP_R423:
 220     case CHIP_R430:
 221     case CHIP_R480:
 222     case CHIP_R481:
 223     case CHIP_RV410:
 224     case CHIP_RS600:
 225     case CHIP_RS690:
 226     case CHIP_RS740:
 227         ws->info.chip_class = R400;
 228         break;
 229     case CHIP_RV515:    /* R5xx-based cores. */
 230     case CHIP_R520:
 231     case CHIP_RV530:
 232     case CHIP_R580:
 233     case CHIP_RV560:
 234     case CHIP_RV570:
 235         ws->info.chip_class = R500;
 236         break;
 237     case CHIP_R600:
 238     case CHIP_RV610:
 239     case CHIP_RV630:
 240     case CHIP_RV670:
 241     case CHIP_RV620:
 242     case CHIP_RV635:
 243     case CHIP_RS780:
 244     case CHIP_RS880:
 245         ws->info.chip_class = R600;
 246         break;
 247     case CHIP_RV770:
 248     case CHIP_RV730:
 249     case CHIP_RV710:
 250     case CHIP_RV740:
 251         ws->info.chip_class = R700;
 252         break;
 253     case CHIP_CEDAR:
 254     case CHIP_REDWOOD:
 255     case CHIP_JUNIPER:
 256     case CHIP_CYPRESS:
 257     case CHIP_HEMLOCK:
 258     case CHIP_PALM:
 259     case CHIP_SUMO:
 260     case CHIP_SUMO2:
 261     case CHIP_BARTS:
 262     case CHIP_TURKS:
 263     case CHIP_CAICOS:
 264         ws->info.chip_class = EVERGREEN;
 265         break;
 266     case CHIP_CAYMAN:
 267     case CHIP_ARUBA:
 268         ws->info.chip_class = CAYMAN;
 269         break;
 270     case CHIP_TAHITI:
 271     case CHIP_PITCAIRN:
 272     case CHIP_VERDE:
 273     case CHIP_OLAND:
 274     case CHIP_HAINAN:
 275         ws->info.chip_class = SI;
 276         break;
 277     case CHIP_BONAIRE:
 278     case CHIP_KAVERI:
 279     case CHIP_KABINI:
 280     case CHIP_HAWAII:
 281     case CHIP_MULLINS:
 282         ws->info.chip_class = CIK;
 283         break;
 284     }
 285
 286     /* Check for dma */
 287     ws->info.r600_has_dma = FALSE;
 288     /* DMA is disabled on R700. There is IB corruption and hangs. */
 289     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 290         ws->info.r600_has_dma = TRUE;
 291     }
 292
 293     /* Check for UVD and VCE */
 294     ws->info.has_uvd = FALSE;
 295     ws->info.vce_fw_version = 0x00000000;
 296     if (ws->info.drm_minor >= 32) {
 297         uint32_t value = RADEON_CS_RING_UVD;
 298         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 299                                  "UVD Ring working", &value))
 300             ws->info.has_uvd = value;
 301
 302         value = RADEON_CS_RING_VCE;
 303         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 304                                  NULL, &value) && value) {
 305
 306             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 307                                      "VCE FW version", &value))
 308                 ws->info.vce_fw_version = value;
 309         }
 310     }
 311
 312     /* Check for userptr support. */
 313     {
 314         struct drm_radeon_gem_userptr args = {0};
 315
 316         /* If the ioctl doesn't exist, -EINVAL is returned.
 317          *
 318          * If the ioctl exists, it should return -EACCES
 319          * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
 320          * aren't set.
 321          */
 322         ws->info.has_userptr =
 323             drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
 324                                 &args, sizeof(args)) == -EACCES;
 325     }
 326
 327     /* Get GEM info. */
 328     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 329             &gem_info, sizeof(gem_info));
 330     if (retval) {
 331         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 332                 retval);
 333         return FALSE;
 334     }
 335     ws->info.gart_size = gem_info.gart_size;
 336     ws->info.vram_size = gem_info.vram_size;
 337
 338     /* Get max clock frequency info and convert it to MHz */
 339     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 340                          &ws->info.max_sclk);
 341     ws->info.max_sclk /= 1000;
 342
 343     radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
 344                          &ws->info.si_backend_enabled_mask);
 345
 346     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 347
 348     /* Generation-specific queries. */
 349     if (ws->gen == DRV_R300) {
 350         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 351                                   "GB pipe count",
 352                                   &ws->info.r300_num_gb_pipes))
 353             return FALSE;
 354
 355         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 356                                   "Z pipe count",
 357                                   &ws->info.r300_num_z_pipes))
 358             return FALSE;
 359     }
 360     else if (ws->gen >= DRV_R600) {
 361         if (ws->info.drm_minor >= 9 &&
 362             !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 363                                   "num backends",
 364                                   &ws->info.r600_num_backends))
 365             return FALSE;
 366
 367         /* get the GPU counter frequency, failure is not fatal */
 368         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 369                              &ws->info.r600_clock_crystal_freq);
 370
 371         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 372                              &ws->info.r600_tiling_config);
 373
 374         if (ws->info.drm_minor >= 11) {
 375             radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 376                                  &ws->info.r600_num_tile_pipes);
 377
 378             if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 379                                       &ws->info.r600_backend_map))
 380                 ws->info.r600_backend_map_valid = TRUE;
 381         }
 382
 383         ws->info.r600_virtual_address = FALSE;
 384         if (ws->info.drm_minor >= 13) {
 385             uint32_t ib_vm_max_size;
 386
 387             ws->info.r600_virtual_address = TRUE;
 388             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 389                                       &ws->va_start))
 390                 ws->info.r600_virtual_address = FALSE;
 391             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 392                                       &ib_vm_max_size))
 393                 ws->info.r600_virtual_address = FALSE;
 394         }
 395         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", FALSE))
 396                 ws->info.r600_virtual_address = FALSE;
 397     }
 398
 399     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 400      * chips have at least 2 pipes, so we use 2 as a default. */
 401     ws->info.r600_max_pipes = 2;
 402     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 403                          &ws->info.r600_max_pipes);
 404
 405     /* All GPUs have at least one compute unit */
 406     ws->info.max_compute_units = 1;
 407     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 408                          &ws->info.max_compute_units);
 409
 410     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 411                          &ws->info.max_se);
 412
 413     if (!ws->info.max_se) {
 414         switch (ws->info.family) {
 415         default:
 416             ws->info.max_se = 1;
 417             break;
 418         case CHIP_CYPRESS:
 419         case CHIP_HEMLOCK:
 420         case CHIP_BARTS:
 421         case CHIP_CAYMAN:
 422         case CHIP_TAHITI:
 423         case CHIP_PITCAIRN:
 424         case CHIP_BONAIRE:
 425             ws->info.max_se = 2;
 426             break;
 427         case CHIP_HAWAII:
 428             ws->info.max_se = 4;
 429             break;
 430         }
 431     }
 432
 433     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 434                          &ws->info.max_sh_per_se);
 435
 436     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 437                          &ws->accel_working2);
 438     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 439         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 440                 "returned accel_working2 value %u is smaller than 2. "
 441                 "Please install a newer kernel.\n",
 442                 ws->accel_working2);
 443         return FALSE;
 444     }
 445
 446     if (radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 447                              ws->info.si_tile_mode_array)) {
 448         ws->info.si_tile_mode_array_valid = TRUE;
 449     }
 450
 451     if (radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 452                              ws->info.cik_macrotile_mode_array)) {
 453         ws->info.cik_macrotile_mode_array_valid = TRUE;
 454     }
 455
 456     return TRUE;
 457 }
 458
 459 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 460 {
 461     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 462
 463     if (ws->thread) {
 464         ws->kill_thread = 1;
 465         pipe_semaphore_signal(&ws->cs_queued);
 466         pipe_thread_wait(ws->thread);
 467     }
 468     pipe_semaphore_destroy(&ws->cs_queued);
 469
 470     pipe_mutex_destroy(ws->hyperz_owner_mutex);
 471     pipe_mutex_destroy(ws->cmask_owner_mutex);
 472     pipe_mutex_destroy(ws->cs_stack_lock);
 473
 474     ws->cman->destroy(ws->cman);
 475     ws->kman->destroy(ws->kman);
 476     if (ws->gen >= DRV_R600) {
 477         radeon_surface_manager_free(ws->surf_man);
 478     }
 479     FREE(rws);
 480 }
 481
 482 static void radeon_query_info(struct radeon_winsys *rws,
 483                               struct radeon_info *info)
 484 {
 485     *info = ((struct radeon_drm_winsys *)rws)->info;
 486 }
 487
 488 static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 489                                          enum radeon_feature_id fid,
 490                                          boolean enable)
 491 {
 492     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 493
 494     switch (fid) {
 495     case RADEON_FID_R300_HYPERZ_ACCESS:
 496         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 497                                     &cs->ws->hyperz_owner_mutex,
 498                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 499                                     enable);
 500
 501     case RADEON_FID_R300_CMASK_ACCESS:
 502         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 503                                     &cs->ws->cmask_owner_mutex,
 504                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 505                                     enable);
 506     }
 507     return FALSE;
 508 }
 509
 510 static int radeon_drm_winsys_surface_init(struct radeon_winsys *rws,
 511                                           struct radeon_surface *surf)
 512 {
 513     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 514
 515     return radeon_surface_init(ws->surf_man, surf);
 516 }
 517
 518 static int radeon_drm_winsys_surface_best(struct radeon_winsys *rws,
 519                                           struct radeon_surface *surf)
 520 {
 521     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 522
 523     return radeon_surface_best(ws->surf_man, surf);
 524 }
 525
 526 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 527                                    enum radeon_value_id value)
 528 {
 529     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 530     uint64_t retval = 0;
 531
 532     switch (value) {
 533     case RADEON_REQUESTED_VRAM_MEMORY:
 534         return ws->allocated_vram;
 535     case RADEON_REQUESTED_GTT_MEMORY:
 536         return ws->allocated_gtt;
 537     case RADEON_BUFFER_WAIT_TIME_NS:
 538         return ws->buffer_wait_time;
 539     case RADEON_TIMESTAMP:
 540         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 541             assert(0);
 542             return 0;
 543         }
 544
 545         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 546                              (uint32_t*)&retval);
 547         return retval;
 548     case RADEON_NUM_CS_FLUSHES:
 549         return ws->num_cs_flushes;
 550     case RADEON_NUM_BYTES_MOVED:
 551         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 552                              "num-bytes-moved", (uint32_t*)&retval);
 553         return retval;
 554     case RADEON_VRAM_USAGE:
 555         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 556                              "vram-usage", (uint32_t*)&retval);
 557         return retval;
 558     case RADEON_GTT_USAGE:
 559         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 560                              "gtt-usage", (uint32_t*)&retval);
 561         return retval;
 562     }
 563     return 0;
 564 }
 565
 566 static unsigned hash_fd(void *key)
 567 {
 568     int fd = pointer_to_intptr(key);
 569     struct stat stat;
 570     fstat(fd, &stat);
 571
 572     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 573 }
 574
 575 static int compare_fd(void *key1, void *key2)
 576 {
 577     int fd1 = pointer_to_intptr(key1);
 578     int fd2 = pointer_to_intptr(key2);
 579     struct stat stat1, stat2;
 580     fstat(fd1, &stat1);
 581     fstat(fd2, &stat2);
 582
 583     return stat1.st_dev != stat2.st_dev ||
 584            stat1.st_ino != stat2.st_ino ||
 585            stat1.st_rdev != stat2.st_rdev;
 586 }
 587
 588 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys *ws, struct radeon_drm_cs *cs)
 589 {
 590 retry:
 591     pipe_mutex_lock(ws->cs_stack_lock);
 592     if (ws->ncs >= RING_LAST) {
 593         /* no room left for a flush */
 594         pipe_mutex_unlock(ws->cs_stack_lock);
 595         goto retry;
 596     }
 597     ws->cs_stack[ws->ncs++] = cs;
 598     pipe_mutex_unlock(ws->cs_stack_lock);
 599     pipe_semaphore_signal(&ws->cs_queued);
 600 }
 601
 602 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param)
 603 {
 604     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys *)param;
 605     struct radeon_drm_cs *cs;
 606     unsigned i;
 607
 608     while (1) {
 609         pipe_semaphore_wait(&ws->cs_queued);
 610         if (ws->kill_thread)
 611             break;
 612
 613         pipe_mutex_lock(ws->cs_stack_lock);
 614         cs = ws->cs_stack[0];
 615         for (i = 1; i < ws->ncs; i++)
 616             ws->cs_stack[i - 1] = ws->cs_stack[i];
 617         ws->cs_stack[--ws->ncs] = NULL;
 618         pipe_mutex_unlock(ws->cs_stack_lock);
 619
 620         if (cs) {
 621             radeon_drm_cs_emit_ioctl_oneshot(cs, cs->cst);
 622             pipe_semaphore_signal(&cs->flush_completed);
 623         }
 624     }
 625     pipe_mutex_lock(ws->cs_stack_lock);
 626     for (i = 0; i < ws->ncs; i++) {
 627         pipe_semaphore_signal(&ws->cs_stack[i]->flush_completed);
 628         ws->cs_stack[i] = NULL;
 629     }
 630     ws->ncs = 0;
 631     pipe_mutex_unlock(ws->cs_stack_lock);
 632     return 0;
 633 }
 634
 635 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", TRUE)
 636 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param);
 637
 638 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 639 {
 640     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 641     bool destroy;
 642
 643     /* When the reference counter drops to zero, remove the fd from the table.
 644      * This must happen while the mutex is locked, so that
 645      * radeon_drm_winsys_create in another thread doesn't get the winsys
 646      * from the table when the counter drops to 0. */
 647     pipe_mutex_lock(fd_tab_mutex);
 648
 649     destroy = pipe_reference(&rws->reference, NULL);
 650     if (destroy && fd_tab)
 651         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 652
 653     pipe_mutex_unlock(fd_tab_mutex);
 654     return destroy;
 655 }
 656
 657 PUBLIC struct radeon_winsys *
 658 radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
 659 {
 660     struct radeon_drm_winsys *ws;
 661
 662     pipe_mutex_lock(fd_tab_mutex);
 663     if (!fd_tab) {
 664         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 665     }
 666
 667     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 668     if (ws) {
 669         pipe_reference(NULL, &ws->reference);
 670         pipe_mutex_unlock(fd_tab_mutex);
 671         return &ws->base;
 672     }
 673
 674     ws = CALLOC_STRUCT(radeon_drm_winsys);
 675     if (!ws) {
 676         pipe_mutex_unlock(fd_tab_mutex);
 677         return NULL;
 678     }
 679
 680     ws->fd = fd;
 681
 682     if (!do_winsys_init(ws))
 683         goto fail;
 684
 685     /* Create managers. */
 686     ws->kman = radeon_bomgr_create(ws);
 687     if (!ws->kman)
 688         goto fail;
 689
 690     ws->cman = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0,
 691                                        MIN2(ws->info.vram_size, ws->info.gart_size));
 692     if (!ws->cman)
 693         goto fail;
 694
 695     if (ws->gen >= DRV_R600) {
 696         ws->surf_man = radeon_surface_manager_new(fd);
 697         if (!ws->surf_man)
 698             goto fail;
 699     }
 700
 701     /* init reference */
 702     pipe_reference_init(&ws->reference, 1);
 703
 704     /* Set functions. */
 705     ws->base.unref = radeon_winsys_unref;
 706     ws->base.destroy = radeon_winsys_destroy;
 707     ws->base.query_info = radeon_query_info;
 708     ws->base.cs_request_feature = radeon_cs_request_feature;
 709     ws->base.surface_init = radeon_drm_winsys_surface_init;
 710     ws->base.surface_best = radeon_drm_winsys_surface_best;
 711     ws->base.query_value = radeon_query_value;
 712
 713     radeon_bomgr_init_functions(ws);
 714     radeon_drm_cs_init_functions(ws);
 715
 716     pipe_mutex_init(ws->hyperz_owner_mutex);
 717     pipe_mutex_init(ws->cmask_owner_mutex);
 718     pipe_mutex_init(ws->cs_stack_lock);
 719
 720     ws->ncs = 0;
 721     pipe_semaphore_init(&ws->cs_queued, 0);
 722     if (ws->num_cpus > 1 && debug_get_option_thread())
 723         ws->thread = pipe_thread_create(radeon_drm_cs_emit_ioctl, ws);
 724
 725     /* Create the screen at the end. The winsys must be initialized
 726      * completely.
 727      *
 728      * Alternatively, we could create the screen based on "ws->gen"
 729      * and link all drivers into one binary blob. */
 730     ws->base.screen = screen_create(&ws->base);
 731     if (!ws->base.screen) {
 732         radeon_winsys_destroy(&ws->base);
 733         pipe_mutex_unlock(fd_tab_mutex);
 734         return NULL;
 735     }
 736
 737     util_hash_table_set(fd_tab, intptr_to_pointer(fd), ws);
 738
 739     /* We must unlock the mutex once the winsys is fully initialized, so that
 740      * other threads attempting to create the winsys from the same fd will
 741      * get a fully initialized winsys and not just half-way initialized. */
 742     pipe_mutex_unlock(fd_tab_mutex);
 743
 744     return &ws->base;
 745
 746 fail:
 747     pipe_mutex_unlock(fd_tab_mutex);
 748     if (ws->cman)
 749         ws->cman->destroy(ws->cman);
 750     if (ws->kman)
 751         ws->kman->destroy(ws->kman);
 752     if (ws->surf_man)
 753         radeon_surface_manager_free(ws->surf_man);
 754     FREE(ws);
 755     return NULL;
 756 }