src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "pipebuffer/pb_bufmgr.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_hash_table.h"
  41
  42 #include <xf86drm.h>
  43 #include <stdio.h>
  44
  45 /*
  46  * this are copy from radeon_drm, once an updated libdrm is released
  47  * we should bump configure.ac requirement for it and remove the following
  48  * field
  49  */
  50 #ifndef RADEON_INFO_TILING_CONFIG
  51 #define RADEON_INFO_TILING_CONFIG 6
  52 #endif
  53
  54 #ifndef RADEON_INFO_WANT_HYPERZ
  55 #define RADEON_INFO_WANT_HYPERZ 7
  56 #endif
  57
  58 #ifndef RADEON_INFO_WANT_CMASK
  59 #define RADEON_INFO_WANT_CMASK 8
  60 #endif
  61
  62 #ifndef RADEON_INFO_CLOCK_CRYSTAL_FREQ
  63 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 9
  64 #endif
  65
  66 #ifndef RADEON_INFO_NUM_BACKENDS
  67 #define RADEON_INFO_NUM_BACKENDS 0xa
  68 #endif
  69
  70 #ifndef RADEON_INFO_NUM_TILE_PIPES
  71 #define RADEON_INFO_NUM_TILE_PIPES 0xb
  72 #endif
  73
  74 #ifndef RADEON_INFO_BACKEND_MAP
  75 #define RADEON_INFO_BACKEND_MAP 0xd
  76 #endif
  77
  78 #ifndef RADEON_INFO_VA_START
  79 /* virtual address start, va < start are reserved by the kernel */
  80 #define RADEON_INFO_VA_START        0x0e
  81 /* maximum size of ib using the virtual memory cs */
  82 #define RADEON_INFO_IB_VM_MAX_SIZE  0x0f
  83 #endif
  84
  85 #ifndef RADEON_INFO_MAX_PIPES
  86 #define RADEON_INFO_MAX_PIPES 0x10
  87 #endif
  88
  89 #ifndef RADEON_INFO_TIMESTAMP
  90 #define RADEON_INFO_TIMESTAMP 0x11
  91 #endif
  92
  93 static struct util_hash_table *fd_tab = NULL;
  94
  95 /* Enable/disable feature access for one command stream.
  96  * If enable == TRUE, return TRUE on success.
  97  * Otherwise, return FALSE.
  98  *
  99  * We basically do the same thing kernel does, because we have to deal
 100  * with multiple contexts (here command streams) backed by one winsys. */
 101 static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
 102                                     struct radeon_drm_cs **owner,
 103                                     pipe_mutex *mutex,
 104                                     unsigned request, boolean enable)
 105 {
 106     struct drm_radeon_info info;
 107     unsigned value = enable ? 1 : 0;
 108
 109     memset(&info, 0, sizeof(info));
 110
 111     pipe_mutex_lock(*mutex);
 112
 113     /* Early exit if we are sure the request will fail. */
 114     if (enable) {
 115         if (*owner) {
 116             pipe_mutex_unlock(*mutex);
 117             return FALSE;
 118         }
 119     } else {
 120         if (*owner != applier) {
 121             pipe_mutex_unlock(*mutex);
 122             return FALSE;
 123         }
 124     }
 125
 126     /* Pass through the request to the kernel. */
 127     info.value = (unsigned long)&value;
 128     info.request = request;
 129     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
 130                             &info, sizeof(info)) != 0) {
 131         pipe_mutex_unlock(*mutex);
 132         return FALSE;
 133     }
 134
 135     /* Update the rights in the winsys. */
 136     if (enable) {
 137         if (value) {
 138             *owner = applier;
 139             if (request == RADEON_INFO_WANT_HYPERZ) {
 140                 printf("radeon: Acquired Hyper-Z.\n");
 141             }
 142             pipe_mutex_unlock(*mutex);
 143             return TRUE;
 144         }
 145     } else {
 146         *owner = NULL;
 147         if (request == RADEON_INFO_WANT_HYPERZ) {
 148             printf("radeon: Released Hyper-Z.\n");
 149         }
 150     }
 151
 152     pipe_mutex_unlock(*mutex);
 153     return FALSE;
 154 }
 155
 156 static boolean radeon_get_drm_value(int fd, unsigned request,
 157                                     const char *errname, uint32_t *out)
 158 {
 159     struct drm_radeon_info info;
 160     int retval;
 161
 162     memset(&info, 0, sizeof(info));
 163
 164     info.value = (unsigned long)out;
 165     info.request = request;
 166
 167     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 168     if (retval) {
 169         if (errname) {
 170             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 171                     errname, retval);
 172         }
 173         return FALSE;
 174     }
 175     return TRUE;
 176 }
 177
 178 /* Helper function to do the ioctls needed for setup and init. */
 179 static boolean do_winsys_init(struct radeon_drm_winsys *ws)
 180 {
 181     struct drm_radeon_gem_info gem_info;
 182     int retval;
 183     drmVersionPtr version;
 184
 185     memset(&gem_info, 0, sizeof(gem_info));
 186
 187     /* We do things in a specific order here.
 188      *
 189      * DRM version first. We need to be sure we're running on a KMS chipset.
 190      * This is also for some features.
 191      *
 192      * Then, the PCI ID. This is essential and should return usable numbers
 193      * for all Radeons. If this fails, we probably got handed an FD for some
 194      * non-Radeon card.
 195      *
 196      * The GEM info is actually bogus on the kernel side, as well as our side
 197      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 198      * we don't actually use the info for anything yet.
 199      *
 200      * The GB and Z pipe requests should always succeed, but they might not
 201      * return sensical values for all chipsets, but that's alright because
 202      * the pipe drivers already know that.
 203      */
 204
 205     /* Get DRM version. */
 206     version = drmGetVersion(ws->fd);
 207     if (version->version_major != 2 ||
 208         version->version_minor < 3) {
 209         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 210                 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
 211                 __FUNCTION__,
 212                 version->version_major,
 213                 version->version_minor,
 214                 version->version_patchlevel);
 215         drmFreeVersion(version);
 216         return FALSE;
 217     }
 218
 219     ws->info.drm_major = version->version_major;
 220     ws->info.drm_minor = version->version_minor;
 221     ws->info.drm_patchlevel = version->version_patchlevel;
 222     drmFreeVersion(version);
 223
 224     /* Get PCI ID. */
 225     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 226                               &ws->info.pci_id))
 227         return FALSE;
 228
 229     /* Check PCI ID. */
 230     switch (ws->info.pci_id) {
 231 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 232 #include "pci_ids/r300_pci_ids.h"
 233 #undef CHIPSET
 234
 235 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 236 #include "pci_ids/r600_pci_ids.h"
 237 #undef CHIPSET
 238
 239 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 240 #include "pci_ids/radeonsi_pci_ids.h"
 241 #undef CHIPSET
 242
 243     default:
 244         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 245         return FALSE;
 246     }
 247
 248     switch (ws->info.family) {
 249     default:
 250     case CHIP_UNKNOWN:
 251         fprintf(stderr, "radeon: Unknown family.\n");
 252         return FALSE;
 253     case CHIP_R300:
 254     case CHIP_R350:
 255     case CHIP_RV350:
 256     case CHIP_RV370:
 257     case CHIP_RV380:
 258     case CHIP_RS400:
 259     case CHIP_RC410:
 260     case CHIP_RS480:
 261         ws->info.chip_class = R300;
 262         break;
 263     case CHIP_R420:     /* R4xx-based cores. */
 264     case CHIP_R423:
 265     case CHIP_R430:
 266     case CHIP_R480:
 267     case CHIP_R481:
 268     case CHIP_RV410:
 269     case CHIP_RS600:
 270     case CHIP_RS690:
 271     case CHIP_RS740:
 272         ws->info.chip_class = R400;
 273         break;
 274     case CHIP_RV515:    /* R5xx-based cores. */
 275     case CHIP_R520:
 276     case CHIP_RV530:
 277     case CHIP_R580:
 278     case CHIP_RV560:
 279     case CHIP_RV570:
 280         ws->info.chip_class = R500;
 281         break;
 282     case CHIP_R600:
 283     case CHIP_RV610:
 284     case CHIP_RV630:
 285     case CHIP_RV670:
 286     case CHIP_RV620:
 287     case CHIP_RV635:
 288     case CHIP_RS780:
 289     case CHIP_RS880:
 290         ws->info.chip_class = R600;
 291         break;
 292     case CHIP_RV770:
 293     case CHIP_RV730:
 294     case CHIP_RV710:
 295     case CHIP_RV740:
 296         ws->info.chip_class = R700;
 297         break;
 298     case CHIP_CEDAR:
 299     case CHIP_REDWOOD:
 300     case CHIP_JUNIPER:
 301     case CHIP_CYPRESS:
 302     case CHIP_HEMLOCK:
 303     case CHIP_PALM:
 304     case CHIP_SUMO:
 305     case CHIP_SUMO2:
 306     case CHIP_BARTS:
 307     case CHIP_TURKS:
 308     case CHIP_CAICOS:
 309         ws->info.chip_class = EVERGREEN;
 310         break;
 311     case CHIP_CAYMAN:
 312     case CHIP_ARUBA:
 313         ws->info.chip_class = CAYMAN;
 314         break;
 315     case CHIP_TAHITI:
 316     case CHIP_PITCAIRN:
 317     case CHIP_VERDE:
 318         ws->info.chip_class = TAHITI;
 319         break;
 320     }
 321
 322     /* Get GEM info. */
 323     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 324             &gem_info, sizeof(gem_info));
 325     if (retval) {
 326         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 327                 retval);
 328         return FALSE;
 329     }
 330     ws->info.gart_size = gem_info.gart_size;
 331     ws->info.vram_size = gem_info.vram_size;
 332
 333     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 334
 335     /* Generation-specific queries. */
 336     if (ws->gen == DRV_R300) {
 337         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 338                                   "GB pipe count",
 339                                   &ws->info.r300_num_gb_pipes))
 340             return FALSE;
 341
 342         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 343                                   "Z pipe count",
 344                                   &ws->info.r300_num_z_pipes))
 345             return FALSE;
 346     }
 347     else if (ws->gen >= DRV_R600) {
 348         if (ws->info.drm_minor >= 9 &&
 349             !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 350                                   "num backends",
 351                                   &ws->info.r600_num_backends))
 352             return FALSE;
 353
 354         /* get the GPU counter frequency, failure is not fatal */
 355         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 356                              &ws->info.r600_clock_crystal_freq);
 357
 358         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 359                              &ws->info.r600_tiling_config);
 360
 361         if (ws->info.drm_minor >= 11) {
 362             radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 363                                  &ws->info.r600_num_tile_pipes);
 364
 365             if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 366                                       &ws->info.r600_backend_map))
 367                 ws->info.r600_backend_map_valid = TRUE;
 368         }
 369
 370         ws->info.r600_virtual_address = FALSE;
 371         if (ws->info.drm_minor >= 13) {
 372             ws->info.r600_virtual_address = TRUE;
 373             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 374                                       &ws->info.r600_va_start))
 375                 ws->info.r600_virtual_address = FALSE;
 376             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 377                                       &ws->info.r600_ib_vm_max_size))
 378                 ws->info.r600_virtual_address = FALSE;
 379         }
 380     }
 381
 382     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 383      * chips have at least 2 pipes, so we use 2 as a default. */
 384     ws->info.r600_max_pipes = 2;
 385     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 386                          &ws->info.r600_max_pipes);
 387
 388     return TRUE;
 389 }
 390
 391 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 392 {
 393     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 394
 395     if (!pipe_reference(&ws->base.reference, NULL)) {
 396         return;
 397     }
 398
 399     pipe_mutex_destroy(ws->hyperz_owner_mutex);
 400     pipe_mutex_destroy(ws->cmask_owner_mutex);
 401
 402     ws->cman->destroy(ws->cman);
 403     ws->kman->destroy(ws->kman);
 404     if (ws->gen >= DRV_R600) {
 405         radeon_surface_manager_free(ws->surf_man);
 406     }
 407     if (fd_tab) {
 408         util_hash_table_remove(fd_tab, intptr_to_pointer(ws->fd));
 409     }
 410     FREE(rws);
 411 }
 412
 413 static void radeon_query_info(struct radeon_winsys *rws,
 414                               struct radeon_info *info)
 415 {
 416     *info = ((struct radeon_drm_winsys *)rws)->info;
 417 }
 418
 419 static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 420                                          enum radeon_feature_id fid,
 421                                          boolean enable)
 422 {
 423     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 424
 425     switch (fid) {
 426     case RADEON_FID_R300_HYPERZ_ACCESS:
 427         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 428                                     &cs->ws->hyperz_owner_mutex,
 429                                     RADEON_INFO_WANT_HYPERZ, enable);
 430
 431     case RADEON_FID_R300_CMASK_ACCESS:
 432         if (debug_get_bool_option("RADEON_CMASK", FALSE)) {
 433             return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 434                                         &cs->ws->cmask_owner_mutex,
 435                                         RADEON_INFO_WANT_CMASK, enable);
 436         } else {
 437             return FALSE;
 438         }
 439     }
 440     return FALSE;
 441 }
 442
 443 static int radeon_drm_winsys_surface_init(struct radeon_winsys *rws,
 444                                           struct radeon_surface *surf)
 445 {
 446     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 447
 448     return radeon_surface_init(ws->surf_man, surf);
 449 }
 450
 451 static int radeon_drm_winsys_surface_best(struct radeon_winsys *rws,
 452                                           struct radeon_surface *surf)
 453 {
 454     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 455
 456     return radeon_surface_best(ws->surf_man, surf);
 457 }
 458
 459 static uint64_t radeon_query_timestamp(struct radeon_winsys *rws)
 460 {
 461     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 462     uint64_t ts = 0;
 463
 464     if (ws->info.drm_minor < 20 ||
 465         ws->gen < DRV_R600) {
 466         assert(0);
 467         return 0;
 468     }
 469
 470     radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 471                          (uint32_t*)&ts);
 472     return ts;
 473 }
 474
 475 static unsigned hash_fd(void *key)
 476 {
 477     return pointer_to_intptr(key);
 478 }
 479
 480 static int compare_fd(void *key1, void *key2)
 481 {
 482     return pointer_to_intptr(key1) != pointer_to_intptr(key2);
 483 }
 484
 485 struct radeon_winsys *radeon_drm_winsys_create(int fd)
 486 {
 487     struct radeon_drm_winsys *ws;
 488
 489     if (!fd_tab) {
 490         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 491     }
 492
 493     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 494     if (ws) {
 495         pipe_reference(NULL, &ws->base.reference);
 496         return &ws->base;
 497     }
 498
 499     ws = CALLOC_STRUCT(radeon_drm_winsys);
 500     if (!ws) {
 501         return NULL;
 502     }
 503     ws->fd = fd;
 504     util_hash_table_set(fd_tab, intptr_to_pointer(fd), ws);
 505
 506     if (!do_winsys_init(ws))
 507         goto fail;
 508
 509     /* Create managers. */
 510     ws->kman = radeon_bomgr_create(ws);
 511     if (!ws->kman)
 512         goto fail;
 513     ws->cman = pb_cache_manager_create(ws->kman, 1000000);
 514     if (!ws->cman)
 515         goto fail;
 516
 517     if (ws->gen >= DRV_R600) {
 518         ws->surf_man = radeon_surface_manager_new(fd);
 519         if (!ws->surf_man)
 520             goto fail;
 521     }
 522
 523     /* init reference */
 524     pipe_reference_init(&ws->base.reference, 1);
 525
 526     /* Set functions. */
 527     ws->base.destroy = radeon_winsys_destroy;
 528     ws->base.query_info = radeon_query_info;
 529     ws->base.cs_request_feature = radeon_cs_request_feature;
 530     ws->base.surface_init = radeon_drm_winsys_surface_init;
 531     ws->base.surface_best = radeon_drm_winsys_surface_best;
 532     ws->base.query_timestamp = radeon_query_timestamp;
 533
 534     radeon_bomgr_init_functions(ws);
 535     radeon_drm_cs_init_functions(ws);
 536
 537     pipe_mutex_init(ws->hyperz_owner_mutex);
 538     pipe_mutex_init(ws->cmask_owner_mutex);
 539
 540     return &ws->base;
 541
 542 fail:
 543     if (ws->cman)
 544         ws->cman->destroy(ws->cman);
 545     if (ws->kman)
 546         ws->kman->destroy(ws->kman);
 547     if (ws->surf_man)
 548         radeon_surface_manager_free(ws->surf_man);
 549     FREE(ws);
 550     return NULL;
 551 }