2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "radeon_drm_bo.h"
29 #include "radeon_drm_cs.h"
30 #include "radeon_drm_public.h"
32 #include "util/u_memory.h"
33 #include "util/u_hash_table.h"
37 #include <sys/types.h>
41 #include <radeon_surface.h>
43 static struct util_hash_table
*fd_tab
= NULL
;
44 static mtx_t fd_tab_mutex
= _MTX_INITIALIZER_NP
;
46 /* Enable/disable feature access for one command stream.
47 * If enable == true, return true on success.
48 * Otherwise, return false.
50 * We basically do the same thing kernel does, because we have to deal
51 * with multiple contexts (here command streams) backed by one winsys. */
52 static bool radeon_set_fd_access(struct radeon_drm_cs
*applier
,
53 struct radeon_drm_cs
**owner
,
55 unsigned request
, const char *request_name
,
58 struct drm_radeon_info info
;
59 unsigned value
= enable
? 1 : 0;
61 memset(&info
, 0, sizeof(info
));
65 /* Early exit if we are sure the request will fail. */
72 if (*owner
!= applier
) {
78 /* Pass through the request to the kernel. */
79 info
.value
= (unsigned long)&value
;
80 info
.request
= request
;
81 if (drmCommandWriteRead(applier
->ws
->fd
, DRM_RADEON_INFO
,
82 &info
, sizeof(info
)) != 0) {
87 /* Update the rights in the winsys. */
102 static bool radeon_get_drm_value(int fd
, unsigned request
,
103 const char *errname
, uint32_t *out
)
105 struct drm_radeon_info info
;
108 memset(&info
, 0, sizeof(info
));
110 info
.value
= (unsigned long)out
;
111 info
.request
= request
;
113 retval
= drmCommandWriteRead(fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
116 fprintf(stderr
, "radeon: Failed to get %s, error number %d\n",
124 /* Helper function to do the ioctls needed for setup and init. */
125 static bool do_winsys_init(struct radeon_drm_winsys
*ws
)
127 struct drm_radeon_gem_info gem_info
;
129 drmVersionPtr version
;
131 memset(&gem_info
, 0, sizeof(gem_info
));
133 /* We do things in a specific order here.
135 * DRM version first. We need to be sure we're running on a KMS chipset.
136 * This is also for some features.
138 * Then, the PCI ID. This is essential and should return usable numbers
139 * for all Radeons. If this fails, we probably got handed an FD for some
142 * The GEM info is actually bogus on the kernel side, as well as our side
143 * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
144 * we don't actually use the info for anything yet.
146 * The GB and Z pipe requests should always succeed, but they might not
147 * return sensical values for all chipsets, but that's alright because
148 * the pipe drivers already know that.
151 /* Get DRM version. */
152 version
= drmGetVersion(ws
->fd
);
153 if (version
->version_major
!= 2 ||
154 version
->version_minor
< 12) {
155 fprintf(stderr
, "%s: DRM version is %d.%d.%d but this driver is "
156 "only compatible with 2.12.0 (kernel 3.2) or later.\n",
158 version
->version_major
,
159 version
->version_minor
,
160 version
->version_patchlevel
);
161 drmFreeVersion(version
);
165 ws
->info
.drm_major
= version
->version_major
;
166 ws
->info
.drm_minor
= version
->version_minor
;
167 ws
->info
.drm_patchlevel
= version
->version_patchlevel
;
168 drmFreeVersion(version
);
171 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_DEVICE_ID
, "PCI ID",
176 switch (ws
->info
.pci_id
) {
177 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
178 #include "pci_ids/r300_pci_ids.h"
181 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
182 #include "pci_ids/r600_pci_ids.h"
185 #define CHIPSET(pci_id, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
186 #include "pci_ids/radeonsi_pci_ids.h"
190 fprintf(stderr
, "radeon: Invalid PCI ID.\n");
194 switch (ws
->info
.family
) {
197 fprintf(stderr
, "radeon: Unknown family.\n");
207 ws
->info
.chip_class
= R300
;
209 case CHIP_R420
: /* R4xx-based cores. */
218 ws
->info
.chip_class
= R400
;
220 case CHIP_RV515
: /* R5xx-based cores. */
226 ws
->info
.chip_class
= R500
;
236 ws
->info
.chip_class
= R600
;
242 ws
->info
.chip_class
= R700
;
255 ws
->info
.chip_class
= EVERGREEN
;
259 ws
->info
.chip_class
= CAYMAN
;
266 ws
->info
.chip_class
= SI
;
273 ws
->info
.chip_class
= CIK
;
277 /* Set which chips don't have dedicated VRAM. */
278 switch (ws
->info
.family
) {
294 ws
->info
.has_dedicated_vram
= false;
298 ws
->info
.has_dedicated_vram
= true;
302 ws
->info
.num_sdma_rings
= 0;
303 /* DMA is disabled on R700. There is IB corruption and hangs. */
304 if (ws
->info
.chip_class
>= EVERGREEN
&& ws
->info
.drm_minor
>= 27) {
305 ws
->info
.num_sdma_rings
= 1;
308 /* Check for UVD and VCE */
309 ws
->info
.has_hw_decode
= false;
310 ws
->info
.vce_fw_version
= 0x00000000;
311 if (ws
->info
.drm_minor
>= 32) {
312 uint32_t value
= RADEON_CS_RING_UVD
;
313 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_RING_WORKING
,
314 "UVD Ring working", &value
))
315 ws
->info
.has_hw_decode
= value
;
317 value
= RADEON_CS_RING_VCE
;
318 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_RING_WORKING
,
319 NULL
, &value
) && value
) {
321 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_VCE_FW_VERSION
,
322 "VCE FW version", &value
))
323 ws
->info
.vce_fw_version
= value
;
327 /* Check for userptr support. */
329 struct drm_radeon_gem_userptr args
= {0};
331 /* If the ioctl doesn't exist, -EINVAL is returned.
333 * If the ioctl exists, it should return -EACCES
334 * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
337 ws
->info
.has_userptr
=
338 drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_USERPTR
,
339 &args
, sizeof(args
)) == -EACCES
;
343 retval
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_INFO
,
344 &gem_info
, sizeof(gem_info
));
346 fprintf(stderr
, "radeon: Failed to get MM info, error number %d\n",
350 ws
->info
.gart_size
= gem_info
.gart_size
;
351 ws
->info
.vram_size
= gem_info
.vram_size
;
352 ws
->info
.vram_vis_size
= gem_info
.vram_visible
;
353 /* Older versions of the kernel driver reported incorrect values, and
354 * didn't support more than 256MB of visible VRAM anyway
356 if (ws
->info
.drm_minor
< 49)
357 ws
->info
.vram_vis_size
= MIN2(ws
->info
.vram_vis_size
, 256*1024*1024);
359 /* Radeon allocates all buffers as contigous, which makes large allocations
360 * unlikely to succeed. */
361 ws
->info
.max_alloc_size
= MAX2(ws
->info
.vram_size
, ws
->info
.gart_size
) * 0.7;
362 if (ws
->info
.has_dedicated_vram
)
363 ws
->info
.max_alloc_size
= MIN2(ws
->info
.vram_size
* 0.7, ws
->info
.max_alloc_size
);
364 if (ws
->info
.drm_minor
< 40)
365 ws
->info
.max_alloc_size
= MIN2(ws
->info
.max_alloc_size
, 256*1024*1024);
366 /* Both 32-bit and 64-bit address spaces only have 4GB. */
367 ws
->info
.max_alloc_size
= MIN2(ws
->info
.max_alloc_size
, 3ull*1024*1024*1024);
369 /* Get max clock frequency info and convert it to MHz */
370 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SCLK
, NULL
,
371 &ws
->info
.max_shader_clock
);
372 ws
->info
.max_shader_clock
/= 1000;
374 ws
->num_cpus
= sysconf(_SC_NPROCESSORS_ONLN
);
376 /* Generation-specific queries. */
377 if (ws
->gen
== DRV_R300
) {
378 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_GB_PIPES
,
380 &ws
->info
.r300_num_gb_pipes
))
383 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_Z_PIPES
,
385 &ws
->info
.r300_num_z_pipes
))
388 else if (ws
->gen
>= DRV_R600
) {
389 uint32_t tiling_config
= 0;
391 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BACKENDS
,
393 &ws
->info
.num_render_backends
))
396 /* get the GPU counter frequency, failure is not fatal */
397 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CLOCK_CRYSTAL_FREQ
, NULL
,
398 &ws
->info
.clock_crystal_freq
);
400 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TILING_CONFIG
, NULL
,
403 ws
->info
.r600_num_banks
=
404 ws
->info
.chip_class
>= EVERGREEN
?
405 4 << ((tiling_config
& 0xf0) >> 4) :
406 4 << ((tiling_config
& 0x30) >> 4);
408 ws
->info
.pipe_interleave_bytes
=
409 ws
->info
.chip_class
>= EVERGREEN
?
410 256 << ((tiling_config
& 0xf00) >> 8) :
411 256 << ((tiling_config
& 0xc0) >> 6);
413 if (!ws
->info
.pipe_interleave_bytes
)
414 ws
->info
.pipe_interleave_bytes
=
415 ws
->info
.chip_class
>= EVERGREEN
? 512 : 256;
417 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_TILE_PIPES
, NULL
,
418 &ws
->info
.num_tile_pipes
);
420 /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
421 * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
422 * reports a different value (12). Fix it by setting what's in the
423 * GB_TILE_MODE array (8).
425 if (ws
->gen
== DRV_SI
&& ws
->info
.num_tile_pipes
== 12)
426 ws
->info
.num_tile_pipes
= 8;
428 if (radeon_get_drm_value(ws
->fd
, RADEON_INFO_BACKEND_MAP
, NULL
,
429 &ws
->info
.r600_gb_backend_map
))
430 ws
->info
.r600_gb_backend_map_valid
= true;
433 ws
->info
.enabled_rb_mask
= u_bit_consecutive(0, ws
->info
.num_render_backends
);
435 * This fails (silently) on non-GCN or older kernels, overwriting the
436 * default enabled_rb_mask with the result of the last query.
438 if (ws
->gen
>= DRV_SI
)
439 radeon_get_drm_value(ws
->fd
, RADEON_INFO_SI_BACKEND_ENABLED_MASK
, NULL
,
440 &ws
->info
.enabled_rb_mask
);
442 ws
->info
.r600_has_virtual_memory
= false;
443 if (ws
->info
.drm_minor
>= 13) {
444 uint32_t ib_vm_max_size
;
446 ws
->info
.r600_has_virtual_memory
= true;
447 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_VA_START
, NULL
,
449 ws
->info
.r600_has_virtual_memory
= false;
450 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_IB_VM_MAX_SIZE
, NULL
,
452 ws
->info
.r600_has_virtual_memory
= false;
453 radeon_get_drm_value(ws
->fd
, RADEON_INFO_VA_UNMAP_WORKING
, NULL
,
454 &ws
->va_unmap_working
);
456 if (ws
->gen
== DRV_R600
&& !debug_get_bool_option("RADEON_VA", false))
457 ws
->info
.r600_has_virtual_memory
= false;
460 /* Get max pipes, this is only needed for compute shaders. All evergreen+
461 * chips have at least 2 pipes, so we use 2 as a default. */
462 ws
->info
.r600_max_quad_pipes
= 2;
463 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_PIPES
, NULL
,
464 &ws
->info
.r600_max_quad_pipes
);
466 /* All GPUs have at least one compute unit */
467 ws
->info
.num_good_compute_units
= 1;
468 radeon_get_drm_value(ws
->fd
, RADEON_INFO_ACTIVE_CU_COUNT
, NULL
,
469 &ws
->info
.num_good_compute_units
);
471 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SE
, NULL
,
474 if (!ws
->info
.max_se
) {
475 switch (ws
->info
.family
) {
494 radeon_get_drm_value(ws
->fd
, RADEON_INFO_MAX_SH_PER_SE
, NULL
,
495 &ws
->info
.max_sh_per_se
);
497 radeon_get_drm_value(ws
->fd
, RADEON_INFO_ACCEL_WORKING2
, NULL
,
498 &ws
->accel_working2
);
499 if (ws
->info
.family
== CHIP_HAWAII
&& ws
->accel_working2
< 2) {
500 fprintf(stderr
, "radeon: GPU acceleration for Hawaii disabled, "
501 "returned accel_working2 value %u is smaller than 2. "
502 "Please install a newer kernel.\n",
507 if (ws
->info
.chip_class
== CIK
) {
508 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY
, NULL
,
509 ws
->info
.cik_macrotile_mode_array
)) {
510 fprintf(stderr
, "radeon: Kernel 3.13 is required for CIK support.\n");
515 if (ws
->info
.chip_class
>= SI
) {
516 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_SI_TILE_MODE_ARRAY
, NULL
,
517 ws
->info
.si_tile_mode_array
)) {
518 fprintf(stderr
, "radeon: Kernel 3.10 is required for SI support.\n");
523 /* Hawaii with old firmware needs type2 nop packet.
524 * accel_working2 with value 3 indicates the new firmware.
526 ws
->info
.gfx_ib_pad_with_type2
= ws
->info
.chip_class
<= SI
||
527 (ws
->info
.family
== CHIP_HAWAII
&&
528 ws
->accel_working2
< 3);
529 ws
->info
.tcc_cache_line_size
= 64; /* TC L2 line size on GCN */
530 ws
->info
.ib_start_alignment
= 4096;
531 ws
->info
.kernel_flushes_hdp_before_ib
= ws
->info
.drm_minor
>= 40;
532 /* HTILE is broken with 1D tiling on old kernels and CIK. */
533 ws
->info
.htile_cmask_support_1d_tiling
= ws
->info
.chip_class
!= CIK
||
534 ws
->info
.drm_minor
>= 38;
535 ws
->info
.si_TA_CS_BC_BASE_ADDR_allowed
= ws
->info
.drm_minor
>= 48;
536 ws
->info
.has_bo_metadata
= false;
537 ws
->info
.has_gpu_reset_status_query
= false;
538 ws
->info
.has_gpu_reset_counter_query
= ws
->info
.drm_minor
>= 43;
540 ws
->check_vm
= strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL
;
545 static void radeon_winsys_destroy(struct radeon_winsys
*rws
)
547 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
549 if (util_queue_is_initialized(&ws
->cs_queue
))
550 util_queue_destroy(&ws
->cs_queue
);
552 mtx_destroy(&ws
->hyperz_owner_mutex
);
553 mtx_destroy(&ws
->cmask_owner_mutex
);
555 if (ws
->info
.r600_has_virtual_memory
)
556 pb_slabs_deinit(&ws
->bo_slabs
);
557 pb_cache_deinit(&ws
->bo_cache
);
559 if (ws
->gen
>= DRV_R600
) {
560 radeon_surface_manager_free(ws
->surf_man
);
563 util_hash_table_destroy(ws
->bo_names
);
564 util_hash_table_destroy(ws
->bo_handles
);
565 util_hash_table_destroy(ws
->bo_vas
);
566 mtx_destroy(&ws
->bo_handles_mutex
);
567 mtx_destroy(&ws
->vm32
.mutex
);
568 mtx_destroy(&ws
->vm64
.mutex
);
569 mtx_destroy(&ws
->bo_fence_lock
);
577 static void radeon_query_info(struct radeon_winsys
*rws
,
578 struct radeon_info
*info
)
580 *info
= ((struct radeon_drm_winsys
*)rws
)->info
;
583 static bool radeon_cs_request_feature(struct radeon_winsys_cs
*rcs
,
584 enum radeon_feature_id fid
,
587 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
590 case RADEON_FID_R300_HYPERZ_ACCESS
:
591 return radeon_set_fd_access(cs
, &cs
->ws
->hyperz_owner
,
592 &cs
->ws
->hyperz_owner_mutex
,
593 RADEON_INFO_WANT_HYPERZ
, "Hyper-Z",
596 case RADEON_FID_R300_CMASK_ACCESS
:
597 return radeon_set_fd_access(cs
, &cs
->ws
->cmask_owner
,
598 &cs
->ws
->cmask_owner_mutex
,
599 RADEON_INFO_WANT_CMASK
, "AA optimizations",
605 static uint64_t radeon_query_value(struct radeon_winsys
*rws
,
606 enum radeon_value_id value
)
608 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
612 case RADEON_REQUESTED_VRAM_MEMORY
:
613 return ws
->allocated_vram
;
614 case RADEON_REQUESTED_GTT_MEMORY
:
615 return ws
->allocated_gtt
;
616 case RADEON_MAPPED_VRAM
:
617 return ws
->mapped_vram
;
618 case RADEON_MAPPED_GTT
:
619 return ws
->mapped_gtt
;
620 case RADEON_BUFFER_WAIT_TIME_NS
:
621 return ws
->buffer_wait_time
;
622 case RADEON_NUM_MAPPED_BUFFERS
:
623 return ws
->num_mapped_buffers
;
624 case RADEON_TIMESTAMP
:
625 if (ws
->info
.drm_minor
< 20 || ws
->gen
< DRV_R600
) {
630 radeon_get_drm_value(ws
->fd
, RADEON_INFO_TIMESTAMP
, "timestamp",
633 case RADEON_NUM_GFX_IBS
:
634 return ws
->num_gfx_IBs
;
635 case RADEON_NUM_SDMA_IBS
:
636 return ws
->num_sdma_IBs
;
637 case RADEON_NUM_BYTES_MOVED
:
638 radeon_get_drm_value(ws
->fd
, RADEON_INFO_NUM_BYTES_MOVED
,
639 "num-bytes-moved", (uint32_t*)&retval
);
641 case RADEON_NUM_EVICTIONS
:
642 case RADEON_NUM_VRAM_CPU_PAGE_FAULTS
:
643 case RADEON_VRAM_VIS_USAGE
:
644 case RADEON_GFX_BO_LIST_COUNTER
:
645 case RADEON_GFX_IB_SIZE_COUNTER
:
646 return 0; /* unimplemented */
647 case RADEON_VRAM_USAGE
:
648 radeon_get_drm_value(ws
->fd
, RADEON_INFO_VRAM_USAGE
,
649 "vram-usage", (uint32_t*)&retval
);
651 case RADEON_GTT_USAGE
:
652 radeon_get_drm_value(ws
->fd
, RADEON_INFO_GTT_USAGE
,
653 "gtt-usage", (uint32_t*)&retval
);
655 case RADEON_GPU_TEMPERATURE
:
656 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CURRENT_GPU_TEMP
,
657 "gpu-temp", (uint32_t*)&retval
);
659 case RADEON_CURRENT_SCLK
:
660 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CURRENT_GPU_SCLK
,
661 "current-gpu-sclk", (uint32_t*)&retval
);
663 case RADEON_CURRENT_MCLK
:
664 radeon_get_drm_value(ws
->fd
, RADEON_INFO_CURRENT_GPU_MCLK
,
665 "current-gpu-mclk", (uint32_t*)&retval
);
667 case RADEON_GPU_RESET_COUNTER
:
668 radeon_get_drm_value(ws
->fd
, RADEON_INFO_GPU_RESET_COUNTER
,
669 "gpu-reset-counter", (uint32_t*)&retval
);
671 case RADEON_CS_THREAD_TIME
:
672 return util_queue_get_thread_time_nano(&ws
->cs_queue
, 0);
677 static bool radeon_read_registers(struct radeon_winsys
*rws
,
679 unsigned num_registers
, uint32_t *out
)
681 struct radeon_drm_winsys
*ws
= (struct radeon_drm_winsys
*)rws
;
684 for (i
= 0; i
< num_registers
; i
++) {
685 uint32_t reg
= reg_offset
+ i
*4;
687 if (!radeon_get_drm_value(ws
->fd
, RADEON_INFO_READ_REG
, NULL
, ®
))
694 static unsigned hash_fd(void *key
)
696 int fd
= pointer_to_intptr(key
);
700 return stat
.st_dev
^ stat
.st_ino
^ stat
.st_rdev
;
703 static int compare_fd(void *key1
, void *key2
)
705 int fd1
= pointer_to_intptr(key1
);
706 int fd2
= pointer_to_intptr(key2
);
707 struct stat stat1
, stat2
;
711 return stat1
.st_dev
!= stat2
.st_dev
||
712 stat1
.st_ino
!= stat2
.st_ino
||
713 stat1
.st_rdev
!= stat2
.st_rdev
;
716 DEBUG_GET_ONCE_BOOL_OPTION(thread
, "RADEON_THREAD", true)
718 static bool radeon_winsys_unref(struct radeon_winsys
*ws
)
720 struct radeon_drm_winsys
*rws
= (struct radeon_drm_winsys
*)ws
;
723 /* When the reference counter drops to zero, remove the fd from the table.
724 * This must happen while the mutex is locked, so that
725 * radeon_drm_winsys_create in another thread doesn't get the winsys
726 * from the table when the counter drops to 0. */
727 mtx_lock(&fd_tab_mutex
);
729 destroy
= pipe_reference(&rws
->reference
, NULL
);
730 if (destroy
&& fd_tab
) {
731 util_hash_table_remove(fd_tab
, intptr_to_pointer(rws
->fd
));
732 if (util_hash_table_count(fd_tab
) == 0) {
733 util_hash_table_destroy(fd_tab
);
738 mtx_unlock(&fd_tab_mutex
);
742 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
744 static unsigned handle_hash(void *key
)
746 return PTR_TO_UINT(key
);
749 static int handle_compare(void *key1
, void *key2
)
751 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
754 PUBLIC
struct radeon_winsys
*
755 radeon_drm_winsys_create(int fd
, const struct pipe_screen_config
*config
,
756 radeon_screen_create_t screen_create
)
758 struct radeon_drm_winsys
*ws
;
760 mtx_lock(&fd_tab_mutex
);
762 fd_tab
= util_hash_table_create(hash_fd
, compare_fd
);
765 ws
= util_hash_table_get(fd_tab
, intptr_to_pointer(fd
));
767 pipe_reference(NULL
, &ws
->reference
);
768 mtx_unlock(&fd_tab_mutex
);
772 ws
= CALLOC_STRUCT(radeon_drm_winsys
);
774 mtx_unlock(&fd_tab_mutex
);
778 ws
->fd
= fcntl(fd
, F_DUPFD_CLOEXEC
, 3);
780 if (!do_winsys_init(ws
))
783 pb_cache_init(&ws
->bo_cache
, RADEON_MAX_CACHED_HEAPS
,
784 500000, ws
->check_vm
? 1.0f
: 2.0f
, 0,
785 MIN2(ws
->info
.vram_size
, ws
->info
.gart_size
),
787 radeon_bo_can_reclaim
);
789 if (ws
->info
.r600_has_virtual_memory
) {
790 /* There is no fundamental obstacle to using slab buffer allocation
791 * without GPUVM, but enabling it requires making sure that the drivers
792 * honor the address offset.
794 if (!pb_slabs_init(&ws
->bo_slabs
,
795 RADEON_SLAB_MIN_SIZE_LOG2
, RADEON_SLAB_MAX_SIZE_LOG2
,
796 RADEON_MAX_SLAB_HEAPS
,
798 radeon_bo_can_reclaim_slab
,
799 radeon_bo_slab_alloc
,
800 radeon_bo_slab_free
))
803 ws
->info
.min_alloc_size
= 1 << RADEON_SLAB_MIN_SIZE_LOG2
;
805 ws
->info
.min_alloc_size
= ws
->info
.gart_page_size
;
808 if (ws
->gen
>= DRV_R600
) {
809 ws
->surf_man
= radeon_surface_manager_new(ws
->fd
);
815 pipe_reference_init(&ws
->reference
, 1);
818 ws
->base
.unref
= radeon_winsys_unref
;
819 ws
->base
.destroy
= radeon_winsys_destroy
;
820 ws
->base
.query_info
= radeon_query_info
;
821 ws
->base
.cs_request_feature
= radeon_cs_request_feature
;
822 ws
->base
.query_value
= radeon_query_value
;
823 ws
->base
.read_registers
= radeon_read_registers
;
825 radeon_drm_bo_init_functions(ws
);
826 radeon_drm_cs_init_functions(ws
);
827 radeon_surface_init_functions(ws
);
829 (void) mtx_init(&ws
->hyperz_owner_mutex
, mtx_plain
);
830 (void) mtx_init(&ws
->cmask_owner_mutex
, mtx_plain
);
832 ws
->bo_names
= util_hash_table_create(handle_hash
, handle_compare
);
833 ws
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
834 ws
->bo_vas
= util_hash_table_create(handle_hash
, handle_compare
);
835 (void) mtx_init(&ws
->bo_handles_mutex
, mtx_plain
);
836 (void) mtx_init(&ws
->vm32
.mutex
, mtx_plain
);
837 (void) mtx_init(&ws
->vm64
.mutex
, mtx_plain
);
838 (void) mtx_init(&ws
->bo_fence_lock
, mtx_plain
);
839 list_inithead(&ws
->vm32
.holes
);
840 list_inithead(&ws
->vm64
.holes
);
842 /* The kernel currently returns 8MB. Make sure this doesn't change. */
843 if (ws
->va_start
> 8 * 1024 * 1024) {
844 /* Not enough 32-bit address space. */
845 radeon_winsys_destroy(&ws
->base
);
846 mtx_unlock(&fd_tab_mutex
);
850 ws
->vm32
.start
= ws
->va_start
;
851 ws
->vm32
.end
= 1ull << 32;
853 /* The maximum is 8GB of virtual address space limited by the kernel.
854 * It's obviously not enough for bigger cards, like Hawaiis with 4GB
855 * and 8GB of physical memory and 4GB of GART.
857 * Older kernels set the limit to 4GB, which is even worse, so they only
858 * have 32-bit address space.
860 if (ws
->info
.drm_minor
>= 41) {
861 ws
->vm64
.start
= 1ull << 32;
862 ws
->vm64
.end
= 1ull << 33;
865 /* TTM aligns the BO size to the CPU page size */
866 ws
->info
.gart_page_size
= sysconf(_SC_PAGESIZE
);
868 if (ws
->num_cpus
> 1 && debug_get_option_thread())
869 util_queue_init(&ws
->cs_queue
, "radeon_cs", 8, 1, 0);
871 /* Create the screen at the end. The winsys must be initialized
874 * Alternatively, we could create the screen based on "ws->gen"
875 * and link all drivers into one binary blob. */
876 ws
->base
.screen
= screen_create(&ws
->base
, config
);
877 if (!ws
->base
.screen
) {
878 radeon_winsys_destroy(&ws
->base
);
879 mtx_unlock(&fd_tab_mutex
);
883 util_hash_table_set(fd_tab
, intptr_to_pointer(ws
->fd
), ws
);
885 /* We must unlock the mutex once the winsys is fully initialized, so that
886 * other threads attempting to create the winsys from the same fd will
887 * get a fully initialized winsys and not just half-way initialized. */
888 mtx_unlock(&fd_tab_mutex
);
893 if (ws
->info
.r600_has_virtual_memory
)
894 pb_slabs_deinit(&ws
->bo_slabs
);
896 pb_cache_deinit(&ws
->bo_cache
);
898 mtx_unlock(&fd_tab_mutex
);
900 radeon_surface_manager_free(ws
->surf_man
);