src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "util/u_memory.h"
  39 #include "util/u_hash_table.h"
  40
  41 #include <xf86drm.h>
  42 #include <stdio.h>
  43 #include <sys/types.h>
  44 #include <sys/stat.h>
  45 #include <unistd.h>
  46 #include <fcntl.h>
  47 #include <radeon_surface.h>
  48
  49 #ifndef RADEON_INFO_ACTIVE_CU_COUNT
  50 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
  51 #endif
  52
  53 #ifndef RADEON_INFO_CURRENT_GPU_TEMP
  54 #define RADEON_INFO_CURRENT_GPU_TEMP    0x21
  55 #define RADEON_INFO_CURRENT_GPU_SCLK    0x22
  56 #define RADEON_INFO_CURRENT_GPU_MCLK    0x23
  57 #define RADEON_INFO_READ_REG            0x24
  58 #endif
  59
  60 #define RADEON_INFO_VA_UNMAP_WORKING    0x25
  61
  62 #ifndef RADEON_INFO_GPU_RESET_COUNTER
  63 #define RADEON_INFO_GPU_RESET_COUNTER   0x26
  64 #endif
  65
  66 static struct util_hash_table *fd_tab = NULL;
  67 pipe_static_mutex(fd_tab_mutex);
  68
  69 /* Enable/disable feature access for one command stream.
  70  * If enable == true, return true on success.
  71  * Otherwise, return false.
  72  *
  73  * We basically do the same thing kernel does, because we have to deal
  74  * with multiple contexts (here command streams) backed by one winsys. */
  75 static bool radeon_set_fd_access(struct radeon_drm_cs *applier,
  76                                  struct radeon_drm_cs **owner,
  77                                  pipe_mutex *mutex,
  78                                  unsigned request, const char *request_name,
  79                                  bool enable)
  80 {
  81     struct drm_radeon_info info;
  82     unsigned value = enable ? 1 : 0;
  83
  84     memset(&info, 0, sizeof(info));
  85
  86     pipe_mutex_lock(*mutex);
  87
  88     /* Early exit if we are sure the request will fail. */
  89     if (enable) {
  90         if (*owner) {
  91             pipe_mutex_unlock(*mutex);
  92             return false;
  93         }
  94     } else {
  95         if (*owner != applier) {
  96             pipe_mutex_unlock(*mutex);
  97             return false;
  98         }
  99     }
 100
 101     /* Pass through the request to the kernel. */
 102     info.value = (unsigned long)&value;
 103     info.request = request;
 104     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
 105                             &info, sizeof(info)) != 0) {
 106         pipe_mutex_unlock(*mutex);
 107         return false;
 108     }
 109
 110     /* Update the rights in the winsys. */
 111     if (enable) {
 112         if (value) {
 113             *owner = applier;
 114             pipe_mutex_unlock(*mutex);
 115             return true;
 116         }
 117     } else {
 118         *owner = NULL;
 119     }
 120
 121     pipe_mutex_unlock(*mutex);
 122     return false;
 123 }
 124
 125 static bool radeon_get_drm_value(int fd, unsigned request,
 126                                  const char *errname, uint32_t *out)
 127 {
 128     struct drm_radeon_info info;
 129     int retval;
 130
 131     memset(&info, 0, sizeof(info));
 132
 133     info.value = (unsigned long)out;
 134     info.request = request;
 135
 136     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 137     if (retval) {
 138         if (errname) {
 139             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 140                     errname, retval);
 141         }
 142         return false;
 143     }
 144     return true;
 145 }
 146
 147 /* Helper function to do the ioctls needed for setup and init. */
 148 static bool do_winsys_init(struct radeon_drm_winsys *ws)
 149 {
 150     struct drm_radeon_gem_info gem_info;
 151     int retval;
 152     drmVersionPtr version;
 153
 154     memset(&gem_info, 0, sizeof(gem_info));
 155
 156     /* We do things in a specific order here.
 157      *
 158      * DRM version first. We need to be sure we're running on a KMS chipset.
 159      * This is also for some features.
 160      *
 161      * Then, the PCI ID. This is essential and should return usable numbers
 162      * for all Radeons. If this fails, we probably got handed an FD for some
 163      * non-Radeon card.
 164      *
 165      * The GEM info is actually bogus on the kernel side, as well as our side
 166      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 167      * we don't actually use the info for anything yet.
 168      *
 169      * The GB and Z pipe requests should always succeed, but they might not
 170      * return sensical values for all chipsets, but that's alright because
 171      * the pipe drivers already know that.
 172      */
 173
 174     /* Get DRM version. */
 175     version = drmGetVersion(ws->fd);
 176     if (version->version_major != 2 ||
 177         version->version_minor < 12) {
 178         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 179                 "only compatible with 2.12.0 (kernel 3.2) or later.\n",
 180                 __FUNCTION__,
 181                 version->version_major,
 182                 version->version_minor,
 183                 version->version_patchlevel);
 184         drmFreeVersion(version);
 185         return false;
 186     }
 187
 188     ws->info.drm_major = version->version_major;
 189     ws->info.drm_minor = version->version_minor;
 190     ws->info.drm_patchlevel = version->version_patchlevel;
 191     drmFreeVersion(version);
 192
 193     /* Get PCI ID. */
 194     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 195                               &ws->info.pci_id))
 196         return false;
 197
 198     /* Check PCI ID. */
 199     switch (ws->info.pci_id) {
 200 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 201 #include "pci_ids/r300_pci_ids.h"
 202 #undef CHIPSET
 203
 204 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 205 #include "pci_ids/r600_pci_ids.h"
 206 #undef CHIPSET
 207
 208 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 209 #include "pci_ids/radeonsi_pci_ids.h"
 210 #undef CHIPSET
 211
 212     default:
 213         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 214         return false;
 215     }
 216
 217     switch (ws->info.family) {
 218     default:
 219     case CHIP_UNKNOWN:
 220         fprintf(stderr, "radeon: Unknown family.\n");
 221         return false;
 222     case CHIP_R300:
 223     case CHIP_R350:
 224     case CHIP_RV350:
 225     case CHIP_RV370:
 226     case CHIP_RV380:
 227     case CHIP_RS400:
 228     case CHIP_RC410:
 229     case CHIP_RS480:
 230         ws->info.chip_class = R300;
 231         break;
 232     case CHIP_R420:     /* R4xx-based cores. */
 233     case CHIP_R423:
 234     case CHIP_R430:
 235     case CHIP_R480:
 236     case CHIP_R481:
 237     case CHIP_RV410:
 238     case CHIP_RS600:
 239     case CHIP_RS690:
 240     case CHIP_RS740:
 241         ws->info.chip_class = R400;
 242         break;
 243     case CHIP_RV515:    /* R5xx-based cores. */
 244     case CHIP_R520:
 245     case CHIP_RV530:
 246     case CHIP_R580:
 247     case CHIP_RV560:
 248     case CHIP_RV570:
 249         ws->info.chip_class = R500;
 250         break;
 251     case CHIP_R600:
 252     case CHIP_RV610:
 253     case CHIP_RV630:
 254     case CHIP_RV670:
 255     case CHIP_RV620:
 256     case CHIP_RV635:
 257     case CHIP_RS780:
 258     case CHIP_RS880:
 259         ws->info.chip_class = R600;
 260         break;
 261     case CHIP_RV770:
 262     case CHIP_RV730:
 263     case CHIP_RV710:
 264     case CHIP_RV740:
 265         ws->info.chip_class = R700;
 266         break;
 267     case CHIP_CEDAR:
 268     case CHIP_REDWOOD:
 269     case CHIP_JUNIPER:
 270     case CHIP_CYPRESS:
 271     case CHIP_HEMLOCK:
 272     case CHIP_PALM:
 273     case CHIP_SUMO:
 274     case CHIP_SUMO2:
 275     case CHIP_BARTS:
 276     case CHIP_TURKS:
 277     case CHIP_CAICOS:
 278         ws->info.chip_class = EVERGREEN;
 279         break;
 280     case CHIP_CAYMAN:
 281     case CHIP_ARUBA:
 282         ws->info.chip_class = CAYMAN;
 283         break;
 284     case CHIP_TAHITI:
 285     case CHIP_PITCAIRN:
 286     case CHIP_VERDE:
 287     case CHIP_OLAND:
 288     case CHIP_HAINAN:
 289         ws->info.chip_class = SI;
 290         break;
 291     case CHIP_BONAIRE:
 292     case CHIP_KAVERI:
 293     case CHIP_KABINI:
 294     case CHIP_HAWAII:
 295     case CHIP_MULLINS:
 296         ws->info.chip_class = CIK;
 297         break;
 298     }
 299
 300     /* Set which chips don't have dedicated VRAM. */
 301     switch (ws->info.family) {
 302     case CHIP_RS400:
 303     case CHIP_RC410:
 304     case CHIP_RS480:
 305     case CHIP_RS600:
 306     case CHIP_RS690:
 307     case CHIP_RS740:
 308     case CHIP_RS780:
 309     case CHIP_RS880:
 310     case CHIP_PALM:
 311     case CHIP_SUMO:
 312     case CHIP_SUMO2:
 313     case CHIP_ARUBA:
 314     case CHIP_KAVERI:
 315     case CHIP_KABINI:
 316     case CHIP_MULLINS:
 317        ws->info.has_dedicated_vram = false;
 318        break;
 319
 320     default:
 321        ws->info.has_dedicated_vram = true;
 322     }
 323
 324     /* Check for dma */
 325     ws->info.has_sdma = false;
 326     /* DMA is disabled on R700. There is IB corruption and hangs. */
 327     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 328         ws->info.has_sdma = true;
 329     }
 330
 331     /* Check for UVD and VCE */
 332     ws->info.has_uvd = false;
 333     ws->info.vce_fw_version = 0x00000000;
 334     if (ws->info.drm_minor >= 32) {
 335         uint32_t value = RADEON_CS_RING_UVD;
 336         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 337                                  "UVD Ring working", &value))
 338             ws->info.has_uvd = value;
 339
 340         value = RADEON_CS_RING_VCE;
 341         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 342                                  NULL, &value) && value) {
 343
 344             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 345                                      "VCE FW version", &value))
 346                 ws->info.vce_fw_version = value;
 347         }
 348     }
 349
 350     /* Check for userptr support. */
 351     {
 352         struct drm_radeon_gem_userptr args = {0};
 353
 354         /* If the ioctl doesn't exist, -EINVAL is returned.
 355          *
 356          * If the ioctl exists, it should return -EACCES
 357          * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
 358          * aren't set.
 359          */
 360         ws->info.has_userptr =
 361             drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
 362                                 &args, sizeof(args)) == -EACCES;
 363     }
 364
 365     /* Get GEM info. */
 366     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 367             &gem_info, sizeof(gem_info));
 368     if (retval) {
 369         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 370                 retval);
 371         return false;
 372     }
 373     ws->info.gart_size = gem_info.gart_size;
 374     ws->info.vram_size = gem_info.vram_size;
 375     ws->info.vram_vis_size = gem_info.vram_visible;
 376
 377     /* Radeon allocates all buffers as contigous, which makes large allocations
 378      * unlikely to succeed. */
 379     ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 0.7;
 380     if (ws->info.drm_minor < 40)
 381         ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
 382
 383     /* Get max clock frequency info and convert it to MHz */
 384     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 385                          &ws->info.max_shader_clock);
 386     ws->info.max_shader_clock /= 1000;
 387
 388     radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
 389                          &ws->info.enabled_rb_mask);
 390
 391     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 392
 393     /* Generation-specific queries. */
 394     if (ws->gen == DRV_R300) {
 395         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 396                                   "GB pipe count",
 397                                   &ws->info.r300_num_gb_pipes))
 398             return false;
 399
 400         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 401                                   "Z pipe count",
 402                                   &ws->info.r300_num_z_pipes))
 403             return false;
 404     }
 405     else if (ws->gen >= DRV_R600) {
 406         uint32_t tiling_config = 0;
 407
 408         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 409                                   "num backends",
 410                                   &ws->info.num_render_backends))
 411             return false;
 412
 413         /* get the GPU counter frequency, failure is not fatal */
 414         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 415                              &ws->info.clock_crystal_freq);
 416
 417         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 418                              &tiling_config);
 419
 420         ws->info.r600_num_banks =
 421             ws->info.chip_class >= EVERGREEN ?
 422                 4 << ((tiling_config & 0xf0) >> 4) :
 423                 4 << ((tiling_config & 0x30) >> 4);
 424
 425         ws->info.pipe_interleave_bytes =
 426             ws->info.chip_class >= EVERGREEN ?
 427                 256 << ((tiling_config & 0xf00) >> 8) :
 428                 256 << ((tiling_config & 0xc0) >> 6);
 429
 430         if (!ws->info.pipe_interleave_bytes)
 431             ws->info.pipe_interleave_bytes =
 432                 ws->info.chip_class >= EVERGREEN ? 512 : 256;
 433
 434         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 435                              &ws->info.num_tile_pipes);
 436
 437         /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
 438          * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
 439          * reports a different value (12). Fix it by setting what's in the
 440          * GB_TILE_MODE array (8).
 441          */
 442         if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
 443             ws->info.num_tile_pipes = 8;
 444
 445         if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 446                                   &ws->info.r600_gb_backend_map))
 447             ws->info.r600_gb_backend_map_valid = true;
 448
 449         ws->info.has_virtual_memory = false;
 450         if (ws->info.drm_minor >= 13) {
 451             uint32_t ib_vm_max_size;
 452
 453             ws->info.has_virtual_memory = true;
 454             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 455                                       &ws->va_start))
 456                 ws->info.has_virtual_memory = false;
 457             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 458                                       &ib_vm_max_size))
 459                 ws->info.has_virtual_memory = false;
 460             radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
 461                                  &ws->va_unmap_working);
 462         }
 463         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false))
 464                 ws->info.has_virtual_memory = false;
 465     }
 466
 467     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 468      * chips have at least 2 pipes, so we use 2 as a default. */
 469     ws->info.r600_max_quad_pipes = 2;
 470     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 471                          &ws->info.r600_max_quad_pipes);
 472
 473     /* All GPUs have at least one compute unit */
 474     ws->info.num_good_compute_units = 1;
 475     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 476                          &ws->info.num_good_compute_units);
 477
 478     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 479                          &ws->info.max_se);
 480
 481     if (!ws->info.max_se) {
 482         switch (ws->info.family) {
 483         default:
 484             ws->info.max_se = 1;
 485             break;
 486         case CHIP_CYPRESS:
 487         case CHIP_HEMLOCK:
 488         case CHIP_BARTS:
 489         case CHIP_CAYMAN:
 490         case CHIP_TAHITI:
 491         case CHIP_PITCAIRN:
 492         case CHIP_BONAIRE:
 493             ws->info.max_se = 2;
 494             break;
 495         case CHIP_HAWAII:
 496             ws->info.max_se = 4;
 497             break;
 498         }
 499     }
 500
 501     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 502                          &ws->info.max_sh_per_se);
 503
 504     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 505                          &ws->accel_working2);
 506     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 507         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 508                 "returned accel_working2 value %u is smaller than 2. "
 509                 "Please install a newer kernel.\n",
 510                 ws->accel_working2);
 511         return false;
 512     }
 513
 514     if (ws->info.chip_class == CIK) {
 515         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 516                                   ws->info.cik_macrotile_mode_array)) {
 517             fprintf(stderr, "radeon: Kernel 3.13 is required for CIK support.\n");
 518             return false;
 519         }
 520     }
 521
 522     if (ws->info.chip_class >= SI) {
 523         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 524                                   ws->info.si_tile_mode_array)) {
 525             fprintf(stderr, "radeon: Kernel 3.10 is required for SI support.\n");
 526             return false;
 527         }
 528     }
 529
 530     /* Hawaii with old firmware needs type2 nop packet.
 531      * accel_working2 with value 3 indicates the new firmware.
 532      */
 533     ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI ||
 534                                      (ws->info.family == CHIP_HAWAII &&
 535                                       ws->accel_working2 < 3);
 536
 537     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
 538
 539     return true;
 540 }
 541
 542 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 543 {
 544     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 545
 546     if (util_queue_is_initialized(&ws->cs_queue))
 547         util_queue_destroy(&ws->cs_queue);
 548
 549     pipe_mutex_destroy(ws->hyperz_owner_mutex);
 550     pipe_mutex_destroy(ws->cmask_owner_mutex);
 551
 552     if (ws->info.has_virtual_memory)
 553         pb_slabs_deinit(&ws->bo_slabs);
 554     pb_cache_deinit(&ws->bo_cache);
 555
 556     if (ws->gen >= DRV_R600) {
 557         radeon_surface_manager_free(ws->surf_man);
 558     }
 559
 560     util_hash_table_destroy(ws->bo_names);
 561     util_hash_table_destroy(ws->bo_handles);
 562     util_hash_table_destroy(ws->bo_vas);
 563     pipe_mutex_destroy(ws->bo_handles_mutex);
 564     pipe_mutex_destroy(ws->bo_va_mutex);
 565     pipe_mutex_destroy(ws->bo_fence_lock);
 566
 567     if (ws->fd >= 0)
 568         close(ws->fd);
 569
 570     FREE(rws);
 571 }
 572
 573 static void radeon_query_info(struct radeon_winsys *rws,
 574                               struct radeon_info *info)
 575 {
 576     *info = ((struct radeon_drm_winsys *)rws)->info;
 577 }
 578
 579 static bool radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 580                                       enum radeon_feature_id fid,
 581                                       bool enable)
 582 {
 583     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 584
 585     switch (fid) {
 586     case RADEON_FID_R300_HYPERZ_ACCESS:
 587         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 588                                     &cs->ws->hyperz_owner_mutex,
 589                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 590                                     enable);
 591
 592     case RADEON_FID_R300_CMASK_ACCESS:
 593         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 594                                     &cs->ws->cmask_owner_mutex,
 595                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 596                                     enable);
 597     }
 598     return false;
 599 }
 600
 601 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 602                                    enum radeon_value_id value)
 603 {
 604     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 605     uint64_t retval = 0;
 606
 607     switch (value) {
 608     case RADEON_REQUESTED_VRAM_MEMORY:
 609         return ws->allocated_vram;
 610     case RADEON_REQUESTED_GTT_MEMORY:
 611         return ws->allocated_gtt;
 612     case RADEON_MAPPED_VRAM:
 613        return ws->mapped_vram;
 614     case RADEON_MAPPED_GTT:
 615        return ws->mapped_gtt;
 616     case RADEON_BUFFER_WAIT_TIME_NS:
 617         return ws->buffer_wait_time;
 618     case RADEON_NUM_MAPPED_BUFFERS:
 619         return ws->num_mapped_buffers;
 620     case RADEON_TIMESTAMP:
 621         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 622             assert(0);
 623             return 0;
 624         }
 625
 626         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 627                              (uint32_t*)&retval);
 628         return retval;
 629     case RADEON_NUM_GFX_IBS:
 630         return ws->num_gfx_IBs;
 631     case RADEON_NUM_SDMA_IBS:
 632         return ws->num_sdma_IBs;
 633     case RADEON_NUM_BYTES_MOVED:
 634         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 635                              "num-bytes-moved", (uint32_t*)&retval);
 636         return retval;
 637     case RADEON_NUM_EVICTIONS:
 638     case RADEON_VRAM_VIS_USAGE:
 639         return 0; /* unimplemented */
 640     case RADEON_VRAM_USAGE:
 641         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 642                              "vram-usage", (uint32_t*)&retval);
 643         return retval;
 644     case RADEON_GTT_USAGE:
 645         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 646                              "gtt-usage", (uint32_t*)&retval);
 647         return retval;
 648     case RADEON_GPU_TEMPERATURE:
 649         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
 650                              "gpu-temp", (uint32_t*)&retval);
 651         return retval;
 652     case RADEON_CURRENT_SCLK:
 653         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
 654                              "current-gpu-sclk", (uint32_t*)&retval);
 655         return retval;
 656     case RADEON_CURRENT_MCLK:
 657         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
 658                              "current-gpu-mclk", (uint32_t*)&retval);
 659         return retval;
 660     case RADEON_GPU_RESET_COUNTER:
 661         radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
 662                              "gpu-reset-counter", (uint32_t*)&retval);
 663         return retval;
 664     }
 665     return 0;
 666 }
 667
 668 static bool radeon_read_registers(struct radeon_winsys *rws,
 669                                   unsigned reg_offset,
 670                                   unsigned num_registers, uint32_t *out)
 671 {
 672     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 673     unsigned i;
 674
 675     for (i = 0; i < num_registers; i++) {
 676         uint32_t reg = reg_offset + i*4;
 677
 678         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg))
 679             return false;
 680         out[i] = reg;
 681     }
 682     return true;
 683 }
 684
 685 static unsigned hash_fd(void *key)
 686 {
 687     int fd = pointer_to_intptr(key);
 688     struct stat stat;
 689     fstat(fd, &stat);
 690
 691     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 692 }
 693
 694 static int compare_fd(void *key1, void *key2)
 695 {
 696     int fd1 = pointer_to_intptr(key1);
 697     int fd2 = pointer_to_intptr(key2);
 698     struct stat stat1, stat2;
 699     fstat(fd1, &stat1);
 700     fstat(fd2, &stat2);
 701
 702     return stat1.st_dev != stat2.st_dev ||
 703            stat1.st_ino != stat2.st_ino ||
 704            stat1.st_rdev != stat2.st_rdev;
 705 }
 706
 707 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", true)
 708
 709 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 710 {
 711     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 712     bool destroy;
 713
 714     /* When the reference counter drops to zero, remove the fd from the table.
 715      * This must happen while the mutex is locked, so that
 716      * radeon_drm_winsys_create in another thread doesn't get the winsys
 717      * from the table when the counter drops to 0. */
 718     pipe_mutex_lock(fd_tab_mutex);
 719
 720     destroy = pipe_reference(&rws->reference, NULL);
 721     if (destroy && fd_tab)
 722         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 723
 724     pipe_mutex_unlock(fd_tab_mutex);
 725     return destroy;
 726 }
 727
 728 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 729
 730 static unsigned handle_hash(void *key)
 731 {
 732     return PTR_TO_UINT(key);
 733 }
 734
 735 static int handle_compare(void *key1, void *key2)
 736 {
 737     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 738 }
 739
 740 PUBLIC struct radeon_winsys *
 741 radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
 742 {
 743     struct radeon_drm_winsys *ws;
 744
 745     pipe_mutex_lock(fd_tab_mutex);
 746     if (!fd_tab) {
 747         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 748     }
 749
 750     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 751     if (ws) {
 752         pipe_reference(NULL, &ws->reference);
 753         pipe_mutex_unlock(fd_tab_mutex);
 754         return &ws->base;
 755     }
 756
 757     ws = CALLOC_STRUCT(radeon_drm_winsys);
 758     if (!ws) {
 759         pipe_mutex_unlock(fd_tab_mutex);
 760         return NULL;
 761     }
 762
 763     ws->fd = fcntl(fd, F_DUPFD_CLOEXEC, 3);
 764
 765     if (!do_winsys_init(ws))
 766         goto fail1;
 767
 768     pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
 769                   MIN2(ws->info.vram_size, ws->info.gart_size),
 770                   radeon_bo_destroy,
 771                   radeon_bo_can_reclaim);
 772
 773     if (ws->info.has_virtual_memory) {
 774         /* There is no fundamental obstacle to using slab buffer allocation
 775          * without GPUVM, but enabling it requires making sure that the drivers
 776          * honor the address offset.
 777          */
 778         if (!pb_slabs_init(&ws->bo_slabs,
 779                            RADEON_SLAB_MIN_SIZE_LOG2, RADEON_SLAB_MAX_SIZE_LOG2,
 780                            12,
 781                            ws,
 782                            radeon_bo_can_reclaim_slab,
 783                            radeon_bo_slab_alloc,
 784                            radeon_bo_slab_free))
 785             goto fail_cache;
 786
 787         ws->info.min_alloc_size = 1 << RADEON_SLAB_MIN_SIZE_LOG2;
 788     } else {
 789         ws->info.min_alloc_size = ws->info.gart_page_size;
 790     }
 791
 792     if (ws->gen >= DRV_R600) {
 793         ws->surf_man = radeon_surface_manager_new(ws->fd);
 794         if (!ws->surf_man)
 795             goto fail_slab;
 796     }
 797
 798     /* init reference */
 799     pipe_reference_init(&ws->reference, 1);
 800
 801     /* Set functions. */
 802     ws->base.unref = radeon_winsys_unref;
 803     ws->base.destroy = radeon_winsys_destroy;
 804     ws->base.query_info = radeon_query_info;
 805     ws->base.cs_request_feature = radeon_cs_request_feature;
 806     ws->base.query_value = radeon_query_value;
 807     ws->base.read_registers = radeon_read_registers;
 808
 809     radeon_drm_bo_init_functions(ws);
 810     radeon_drm_cs_init_functions(ws);
 811     radeon_surface_init_functions(ws);
 812
 813     pipe_mutex_init(ws->hyperz_owner_mutex);
 814     pipe_mutex_init(ws->cmask_owner_mutex);
 815
 816     ws->bo_names = util_hash_table_create(handle_hash, handle_compare);
 817     ws->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 818     ws->bo_vas = util_hash_table_create(handle_hash, handle_compare);
 819     pipe_mutex_init(ws->bo_handles_mutex);
 820     pipe_mutex_init(ws->bo_va_mutex);
 821     pipe_mutex_init(ws->bo_fence_lock);
 822     ws->va_offset = ws->va_start;
 823     list_inithead(&ws->va_holes);
 824
 825     /* TTM aligns the BO size to the CPU page size */
 826     ws->info.gart_page_size = sysconf(_SC_PAGESIZE);
 827
 828     if (ws->num_cpus > 1 && debug_get_option_thread())
 829         util_queue_init(&ws->cs_queue, "radeon_cs", 8, 1);
 830
 831     /* Create the screen at the end. The winsys must be initialized
 832      * completely.
 833      *
 834      * Alternatively, we could create the screen based on "ws->gen"
 835      * and link all drivers into one binary blob. */
 836     ws->base.screen = screen_create(&ws->base);
 837     if (!ws->base.screen) {
 838         radeon_winsys_destroy(&ws->base);
 839         pipe_mutex_unlock(fd_tab_mutex);
 840         return NULL;
 841     }
 842
 843     util_hash_table_set(fd_tab, intptr_to_pointer(ws->fd), ws);
 844
 845     /* We must unlock the mutex once the winsys is fully initialized, so that
 846      * other threads attempting to create the winsys from the same fd will
 847      * get a fully initialized winsys and not just half-way initialized. */
 848     pipe_mutex_unlock(fd_tab_mutex);
 849
 850     return &ws->base;
 851
 852 fail_slab:
 853     if (ws->info.has_virtual_memory)
 854         pb_slabs_deinit(&ws->bo_slabs);
 855 fail_cache:
 856     pb_cache_deinit(&ws->bo_cache);
 857 fail1:
 858     pipe_mutex_unlock(fd_tab_mutex);
 859     if (ws->surf_man)
 860         radeon_surface_manager_free(ws->surf_man);
 861     if (ws->fd >= 0)
 862         close(ws->fd);
 863
 864     FREE(ws);
 865     return NULL;
 866 }