src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "pipebuffer/pb_bufmgr.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_hash_table.h"
  41
  42 #include <xf86drm.h>
  43 #include <stdio.h>
  44 #include <sys/types.h>
  45 #include <sys/stat.h>
  46 #include <unistd.h>
  47
  48 #ifndef RADEON_INFO_ACTIVE_CU_COUNT
  49 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
  50 #endif
  51
  52 static struct util_hash_table *fd_tab = NULL;
  53 pipe_static_mutex(fd_tab_mutex);
  54
  55 /* Enable/disable feature access for one command stream.
  56  * If enable == TRUE, return TRUE on success.
  57  * Otherwise, return FALSE.
  58  *
  59  * We basically do the same thing kernel does, because we have to deal
  60  * with multiple contexts (here command streams) backed by one winsys. */
  61 static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
  62                                     struct radeon_drm_cs **owner,
  63                                     pipe_mutex *mutex,
  64                                     unsigned request, const char *request_name,
  65                                     boolean enable)
  66 {
  67     struct drm_radeon_info info;
  68     unsigned value = enable ? 1 : 0;
  69
  70     memset(&info, 0, sizeof(info));
  71
  72     pipe_mutex_lock(*mutex);
  73
  74     /* Early exit if we are sure the request will fail. */
  75     if (enable) {
  76         if (*owner) {
  77             pipe_mutex_unlock(*mutex);
  78             return FALSE;
  79         }
  80     } else {
  81         if (*owner != applier) {
  82             pipe_mutex_unlock(*mutex);
  83             return FALSE;
  84         }
  85     }
  86
  87     /* Pass through the request to the kernel. */
  88     info.value = (unsigned long)&value;
  89     info.request = request;
  90     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
  91                             &info, sizeof(info)) != 0) {
  92         pipe_mutex_unlock(*mutex);
  93         return FALSE;
  94     }
  95
  96     /* Update the rights in the winsys. */
  97     if (enable) {
  98         if (value) {
  99             *owner = applier;
 100             pipe_mutex_unlock(*mutex);
 101             return TRUE;
 102         }
 103     } else {
 104         *owner = NULL;
 105     }
 106
 107     pipe_mutex_unlock(*mutex);
 108     return FALSE;
 109 }
 110
 111 static boolean radeon_get_drm_value(int fd, unsigned request,
 112                                     const char *errname, uint32_t *out)
 113 {
 114     struct drm_radeon_info info;
 115     int retval;
 116
 117     memset(&info, 0, sizeof(info));
 118
 119     info.value = (unsigned long)out;
 120     info.request = request;
 121
 122     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 123     if (retval) {
 124         if (errname) {
 125             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 126                     errname, retval);
 127         }
 128         return FALSE;
 129     }
 130     return TRUE;
 131 }
 132
 133 /* Helper function to do the ioctls needed for setup and init. */
 134 static boolean do_winsys_init(struct radeon_drm_winsys *ws)
 135 {
 136     struct drm_radeon_gem_info gem_info;
 137     int retval;
 138     drmVersionPtr version;
 139
 140     memset(&gem_info, 0, sizeof(gem_info));
 141
 142     /* We do things in a specific order here.
 143      *
 144      * DRM version first. We need to be sure we're running on a KMS chipset.
 145      * This is also for some features.
 146      *
 147      * Then, the PCI ID. This is essential and should return usable numbers
 148      * for all Radeons. If this fails, we probably got handed an FD for some
 149      * non-Radeon card.
 150      *
 151      * The GEM info is actually bogus on the kernel side, as well as our side
 152      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 153      * we don't actually use the info for anything yet.
 154      *
 155      * The GB and Z pipe requests should always succeed, but they might not
 156      * return sensical values for all chipsets, but that's alright because
 157      * the pipe drivers already know that.
 158      */
 159
 160     /* Get DRM version. */
 161     version = drmGetVersion(ws->fd);
 162     if (version->version_major != 2 ||
 163         version->version_minor < 3) {
 164         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 165                 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
 166                 __FUNCTION__,
 167                 version->version_major,
 168                 version->version_minor,
 169                 version->version_patchlevel);
 170         drmFreeVersion(version);
 171         return FALSE;
 172     }
 173
 174     ws->info.drm_major = version->version_major;
 175     ws->info.drm_minor = version->version_minor;
 176     ws->info.drm_patchlevel = version->version_patchlevel;
 177     drmFreeVersion(version);
 178
 179     /* Get PCI ID. */
 180     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 181                               &ws->info.pci_id))
 182         return FALSE;
 183
 184     /* Check PCI ID. */
 185     switch (ws->info.pci_id) {
 186 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 187 #include "pci_ids/r300_pci_ids.h"
 188 #undef CHIPSET
 189
 190 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 191 #include "pci_ids/r600_pci_ids.h"
 192 #undef CHIPSET
 193
 194 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 195 #include "pci_ids/radeonsi_pci_ids.h"
 196 #undef CHIPSET
 197
 198     default:
 199         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 200         return FALSE;
 201     }
 202
 203     switch (ws->info.family) {
 204     default:
 205     case CHIP_UNKNOWN:
 206         fprintf(stderr, "radeon: Unknown family.\n");
 207         return FALSE;
 208     case CHIP_R300:
 209     case CHIP_R350:
 210     case CHIP_RV350:
 211     case CHIP_RV370:
 212     case CHIP_RV380:
 213     case CHIP_RS400:
 214     case CHIP_RC410:
 215     case CHIP_RS480:
 216         ws->info.chip_class = R300;
 217         break;
 218     case CHIP_R420:     /* R4xx-based cores. */
 219     case CHIP_R423:
 220     case CHIP_R430:
 221     case CHIP_R480:
 222     case CHIP_R481:
 223     case CHIP_RV410:
 224     case CHIP_RS600:
 225     case CHIP_RS690:
 226     case CHIP_RS740:
 227         ws->info.chip_class = R400;
 228         break;
 229     case CHIP_RV515:    /* R5xx-based cores. */
 230     case CHIP_R520:
 231     case CHIP_RV530:
 232     case CHIP_R580:
 233     case CHIP_RV560:
 234     case CHIP_RV570:
 235         ws->info.chip_class = R500;
 236         break;
 237     case CHIP_R600:
 238     case CHIP_RV610:
 239     case CHIP_RV630:
 240     case CHIP_RV670:
 241     case CHIP_RV620:
 242     case CHIP_RV635:
 243     case CHIP_RS780:
 244     case CHIP_RS880:
 245         ws->info.chip_class = R600;
 246         break;
 247     case CHIP_RV770:
 248     case CHIP_RV730:
 249     case CHIP_RV710:
 250     case CHIP_RV740:
 251         ws->info.chip_class = R700;
 252         break;
 253     case CHIP_CEDAR:
 254     case CHIP_REDWOOD:
 255     case CHIP_JUNIPER:
 256     case CHIP_CYPRESS:
 257     case CHIP_HEMLOCK:
 258     case CHIP_PALM:
 259     case CHIP_SUMO:
 260     case CHIP_SUMO2:
 261     case CHIP_BARTS:
 262     case CHIP_TURKS:
 263     case CHIP_CAICOS:
 264         ws->info.chip_class = EVERGREEN;
 265         break;
 266     case CHIP_CAYMAN:
 267     case CHIP_ARUBA:
 268         ws->info.chip_class = CAYMAN;
 269         break;
 270     case CHIP_TAHITI:
 271     case CHIP_PITCAIRN:
 272     case CHIP_VERDE:
 273     case CHIP_OLAND:
 274     case CHIP_HAINAN:
 275         ws->info.chip_class = SI;
 276         break;
 277     case CHIP_BONAIRE:
 278     case CHIP_KAVERI:
 279     case CHIP_KABINI:
 280     case CHIP_HAWAII:
 281     case CHIP_MULLINS:
 282         ws->info.chip_class = CIK;
 283         break;
 284     }
 285
 286     /* Check for dma */
 287     ws->info.r600_has_dma = FALSE;
 288     /* DMA is disabled on R700. There is IB corruption and hangs. */
 289     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 290         ws->info.r600_has_dma = TRUE;
 291     }
 292
 293     /* Check for UVD and VCE */
 294     ws->info.has_uvd = FALSE;
 295     ws->info.vce_fw_version = 0x00000000;
 296     if (ws->info.drm_minor >= 32) {
 297         uint32_t value = RADEON_CS_RING_UVD;
 298         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 299                                  "UVD Ring working", &value))
 300             ws->info.has_uvd = value;
 301
 302         value = RADEON_CS_RING_VCE;
 303         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 304                                  NULL, &value) && value) {
 305
 306             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 307                                      "VCE FW version", &value))
 308                 ws->info.vce_fw_version = value;
 309         }
 310     }
 311
 312     /* Get GEM info. */
 313     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 314             &gem_info, sizeof(gem_info));
 315     if (retval) {
 316         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 317                 retval);
 318         return FALSE;
 319     }
 320     ws->info.gart_size = gem_info.gart_size;
 321     ws->info.vram_size = gem_info.vram_size;
 322
 323     /* Get max clock frequency info and convert it to MHz */
 324     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 325                          &ws->info.max_sclk);
 326     ws->info.max_sclk /= 1000;
 327
 328     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 329
 330     /* Generation-specific queries. */
 331     if (ws->gen == DRV_R300) {
 332         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 333                                   "GB pipe count",
 334                                   &ws->info.r300_num_gb_pipes))
 335             return FALSE;
 336
 337         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 338                                   "Z pipe count",
 339                                   &ws->info.r300_num_z_pipes))
 340             return FALSE;
 341     }
 342     else if (ws->gen >= DRV_R600) {
 343         if (ws->info.drm_minor >= 9 &&
 344             !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 345                                   "num backends",
 346                                   &ws->info.r600_num_backends))
 347             return FALSE;
 348
 349         /* get the GPU counter frequency, failure is not fatal */
 350         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 351                              &ws->info.r600_clock_crystal_freq);
 352
 353         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 354                              &ws->info.r600_tiling_config);
 355
 356         if (ws->info.drm_minor >= 11) {
 357             radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 358                                  &ws->info.r600_num_tile_pipes);
 359
 360             if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 361                                       &ws->info.r600_backend_map))
 362                 ws->info.r600_backend_map_valid = TRUE;
 363         }
 364
 365         ws->info.r600_virtual_address = FALSE;
 366         if (ws->info.drm_minor >= 13) {
 367             uint32_t ib_vm_max_size;
 368
 369             ws->info.r600_virtual_address = TRUE;
 370             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 371                                       &ws->va_start))
 372                 ws->info.r600_virtual_address = FALSE;
 373             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 374                                       &ib_vm_max_size))
 375                 ws->info.r600_virtual_address = FALSE;
 376         }
 377         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", FALSE))
 378                 ws->info.r600_virtual_address = FALSE;
 379     }
 380
 381     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 382      * chips have at least 2 pipes, so we use 2 as a default. */
 383     ws->info.r600_max_pipes = 2;
 384     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 385                          &ws->info.r600_max_pipes);
 386
 387     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 388                          &ws->info.max_compute_units);
 389
 390     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 391                          &ws->info.max_se);
 392
 393     if (!ws->info.max_se) {
 394         switch (ws->info.family) {
 395         default:
 396             ws->info.max_se = 1;
 397             break;
 398         case CHIP_CYPRESS:
 399         case CHIP_HEMLOCK:
 400         case CHIP_BARTS:
 401         case CHIP_CAYMAN:
 402         case CHIP_TAHITI:
 403         case CHIP_PITCAIRN:
 404         case CHIP_BONAIRE:
 405             ws->info.max_se = 2;
 406             break;
 407         case CHIP_HAWAII:
 408             ws->info.max_se = 4;
 409             break;
 410         }
 411     }
 412
 413     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 414                          &ws->info.max_sh_per_se);
 415
 416     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 417                          &ws->accel_working2);
 418     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 419         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 420                 "returned accel_working2 value %u is smaller than 2. "
 421                 "Please install a newer kernel.\n",
 422                 ws->accel_working2);
 423         return FALSE;
 424     }
 425
 426     if (radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 427                              ws->info.si_tile_mode_array)) {
 428         ws->info.si_tile_mode_array_valid = TRUE;
 429     }
 430
 431     if (radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 432                              ws->info.cik_macrotile_mode_array)) {
 433         ws->info.cik_macrotile_mode_array_valid = TRUE;
 434     }
 435
 436     return TRUE;
 437 }
 438
 439 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 440 {
 441     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 442
 443     if (ws->thread) {
 444         ws->kill_thread = 1;
 445         pipe_semaphore_signal(&ws->cs_queued);
 446         pipe_thread_wait(ws->thread);
 447     }
 448     pipe_semaphore_destroy(&ws->cs_queued);
 449
 450     pipe_mutex_destroy(ws->hyperz_owner_mutex);
 451     pipe_mutex_destroy(ws->cmask_owner_mutex);
 452     pipe_mutex_destroy(ws->cs_stack_lock);
 453
 454     ws->cman->destroy(ws->cman);
 455     ws->kman->destroy(ws->kman);
 456     if (ws->gen >= DRV_R600) {
 457         radeon_surface_manager_free(ws->surf_man);
 458     }
 459     FREE(rws);
 460 }
 461
 462 static void radeon_query_info(struct radeon_winsys *rws,
 463                               struct radeon_info *info)
 464 {
 465     *info = ((struct radeon_drm_winsys *)rws)->info;
 466 }
 467
 468 static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 469                                          enum radeon_feature_id fid,
 470                                          boolean enable)
 471 {
 472     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 473
 474     switch (fid) {
 475     case RADEON_FID_R300_HYPERZ_ACCESS:
 476         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 477                                     &cs->ws->hyperz_owner_mutex,
 478                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 479                                     enable);
 480
 481     case RADEON_FID_R300_CMASK_ACCESS:
 482         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 483                                     &cs->ws->cmask_owner_mutex,
 484                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 485                                     enable);
 486     }
 487     return FALSE;
 488 }
 489
 490 static int radeon_drm_winsys_surface_init(struct radeon_winsys *rws,
 491                                           struct radeon_surface *surf)
 492 {
 493     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 494
 495     return radeon_surface_init(ws->surf_man, surf);
 496 }
 497
 498 static int radeon_drm_winsys_surface_best(struct radeon_winsys *rws,
 499                                           struct radeon_surface *surf)
 500 {
 501     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 502
 503     return radeon_surface_best(ws->surf_man, surf);
 504 }
 505
 506 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 507                                    enum radeon_value_id value)
 508 {
 509     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 510     uint64_t retval = 0;
 511
 512     switch (value) {
 513     case RADEON_REQUESTED_VRAM_MEMORY:
 514         return ws->allocated_vram;
 515     case RADEON_REQUESTED_GTT_MEMORY:
 516         return ws->allocated_gtt;
 517     case RADEON_BUFFER_WAIT_TIME_NS:
 518         return ws->buffer_wait_time;
 519     case RADEON_TIMESTAMP:
 520         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 521             assert(0);
 522             return 0;
 523         }
 524
 525         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 526                              (uint32_t*)&retval);
 527         return retval;
 528     case RADEON_NUM_CS_FLUSHES:
 529         return ws->num_cs_flushes;
 530     case RADEON_NUM_BYTES_MOVED:
 531         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 532                              "num-bytes-moved", (uint32_t*)&retval);
 533         return retval;
 534     case RADEON_VRAM_USAGE:
 535         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 536                              "vram-usage", (uint32_t*)&retval);
 537         return retval;
 538     case RADEON_GTT_USAGE:
 539         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 540                              "gtt-usage", (uint32_t*)&retval);
 541         return retval;
 542     }
 543     return 0;
 544 }
 545
 546 static unsigned hash_fd(void *key)
 547 {
 548     int fd = pointer_to_intptr(key);
 549     struct stat stat;
 550     fstat(fd, &stat);
 551
 552     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 553 }
 554
 555 static int compare_fd(void *key1, void *key2)
 556 {
 557     int fd1 = pointer_to_intptr(key1);
 558     int fd2 = pointer_to_intptr(key2);
 559     struct stat stat1, stat2;
 560     fstat(fd1, &stat1);
 561     fstat(fd2, &stat2);
 562
 563     return stat1.st_dev != stat2.st_dev ||
 564            stat1.st_ino != stat2.st_ino ||
 565            stat1.st_rdev != stat2.st_rdev;
 566 }
 567
 568 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys *ws, struct radeon_drm_cs *cs)
 569 {
 570 retry:
 571     pipe_mutex_lock(ws->cs_stack_lock);
 572     if (ws->ncs >= RING_LAST) {
 573         /* no room left for a flush */
 574         pipe_mutex_unlock(ws->cs_stack_lock);
 575         goto retry;
 576     }
 577     ws->cs_stack[ws->ncs++] = cs;
 578     pipe_mutex_unlock(ws->cs_stack_lock);
 579     pipe_semaphore_signal(&ws->cs_queued);
 580 }
 581
 582 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param)
 583 {
 584     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys *)param;
 585     struct radeon_drm_cs *cs;
 586     unsigned i;
 587
 588     while (1) {
 589         pipe_semaphore_wait(&ws->cs_queued);
 590         if (ws->kill_thread)
 591             break;
 592
 593         pipe_mutex_lock(ws->cs_stack_lock);
 594         cs = ws->cs_stack[0];
 595         for (i = 1; i < ws->ncs; i++)
 596             ws->cs_stack[i - 1] = ws->cs_stack[i];
 597         ws->cs_stack[--ws->ncs] = NULL;
 598         pipe_mutex_unlock(ws->cs_stack_lock);
 599
 600         if (cs) {
 601             radeon_drm_cs_emit_ioctl_oneshot(cs, cs->cst);
 602             pipe_semaphore_signal(&cs->flush_completed);
 603         }
 604     }
 605     pipe_mutex_lock(ws->cs_stack_lock);
 606     for (i = 0; i < ws->ncs; i++) {
 607         pipe_semaphore_signal(&ws->cs_stack[i]->flush_completed);
 608         ws->cs_stack[i] = NULL;
 609     }
 610     ws->ncs = 0;
 611     pipe_mutex_unlock(ws->cs_stack_lock);
 612     return 0;
 613 }
 614
 615 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", TRUE)
 616 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param);
 617
 618 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 619 {
 620     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 621     bool destroy;
 622
 623     /* When the reference counter drops to zero, remove the fd from the table.
 624      * This must happen while the mutex is locked, so that
 625      * radeon_drm_winsys_create in another thread doesn't get the winsys
 626      * from the table when the counter drops to 0. */
 627     pipe_mutex_lock(fd_tab_mutex);
 628
 629     destroy = pipe_reference(&rws->reference, NULL);
 630     if (destroy && fd_tab)
 631         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 632
 633     pipe_mutex_unlock(fd_tab_mutex);
 634     return destroy;
 635 }
 636
 637 PUBLIC struct radeon_winsys *
 638 radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
 639 {
 640     struct radeon_drm_winsys *ws;
 641
 642     pipe_mutex_lock(fd_tab_mutex);
 643     if (!fd_tab) {
 644         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 645     }
 646
 647     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 648     if (ws) {
 649         pipe_reference(NULL, &ws->reference);
 650         pipe_mutex_unlock(fd_tab_mutex);
 651         return &ws->base;
 652     }
 653
 654     ws = CALLOC_STRUCT(radeon_drm_winsys);
 655     if (!ws) {
 656         pipe_mutex_unlock(fd_tab_mutex);
 657         return NULL;
 658     }
 659
 660     ws->fd = fd;
 661
 662     if (!do_winsys_init(ws))
 663         goto fail;
 664
 665     /* Create managers. */
 666     ws->kman = radeon_bomgr_create(ws);
 667     if (!ws->kman)
 668         goto fail;
 669
 670     ws->cman = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0,
 671                                        (ws->info.vram_size + ws->info.gart_size) / 8);
 672     if (!ws->cman)
 673         goto fail;
 674
 675     if (ws->gen >= DRV_R600) {
 676         ws->surf_man = radeon_surface_manager_new(fd);
 677         if (!ws->surf_man)
 678             goto fail;
 679     }
 680
 681     /* init reference */
 682     pipe_reference_init(&ws->reference, 1);
 683
 684     /* Set functions. */
 685     ws->base.unref = radeon_winsys_unref;
 686     ws->base.destroy = radeon_winsys_destroy;
 687     ws->base.query_info = radeon_query_info;
 688     ws->base.cs_request_feature = radeon_cs_request_feature;
 689     ws->base.surface_init = radeon_drm_winsys_surface_init;
 690     ws->base.surface_best = radeon_drm_winsys_surface_best;
 691     ws->base.query_value = radeon_query_value;
 692
 693     radeon_bomgr_init_functions(ws);
 694     radeon_drm_cs_init_functions(ws);
 695
 696     pipe_mutex_init(ws->hyperz_owner_mutex);
 697     pipe_mutex_init(ws->cmask_owner_mutex);
 698     pipe_mutex_init(ws->cs_stack_lock);
 699
 700     ws->ncs = 0;
 701     pipe_semaphore_init(&ws->cs_queued, 0);
 702     if (ws->num_cpus > 1 && debug_get_option_thread())
 703         ws->thread = pipe_thread_create(radeon_drm_cs_emit_ioctl, ws);
 704
 705     /* Create the screen at the end. The winsys must be initialized
 706      * completely.
 707      *
 708      * Alternatively, we could create the screen based on "ws->gen"
 709      * and link all drivers into one binary blob. */
 710     ws->base.screen = screen_create(&ws->base);
 711     if (!ws->base.screen) {
 712         radeon_winsys_destroy(&ws->base);
 713         pipe_mutex_unlock(fd_tab_mutex);
 714         return NULL;
 715     }
 716
 717     util_hash_table_set(fd_tab, intptr_to_pointer(fd), ws);
 718
 719     /* We must unlock the mutex once the winsys is fully initialized, so that
 720      * other threads attempting to create the winsys from the same fd will
 721      * get a fully initialized winsys and not just half-way initialized. */
 722     pipe_mutex_unlock(fd_tab_mutex);
 723
 724     return &ws->base;
 725
 726 fail:
 727     pipe_mutex_unlock(fd_tab_mutex);
 728     if (ws->cman)
 729         ws->cman->destroy(ws->cman);
 730     if (ws->kman)
 731         ws->kman->destroy(ws->kman);
 732     if (ws->surf_man)
 733         radeon_surface_manager_free(ws->surf_man);
 734     FREE(ws);
 735     return NULL;
 736 }