2 * Copyright © 2009 Corbin Simpson
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
28 * Corbin Simpson <MostAwesomeDude@gmail.com>
30 #ifndef RADEON_DRM_WINSYS_H
31 #define RADEON_DRM_WINSYS_H
33 #include "gallium/drivers/radeon/radeon_winsys.h"
34 #include "pipebuffer/pb_cache.h"
35 #include "util/u_queue.h"
36 #include "util/list.h"
37 #include <radeon_drm.h>
39 #ifndef DRM_RADEON_GEM_USERPTR
41 #define DRM_RADEON_GEM_USERPTR 0x2d
43 #define RADEON_GEM_USERPTR_READONLY (1 << 0)
44 #define RADEON_GEM_USERPTR_ANONONLY (1 << 1)
45 #define RADEON_GEM_USERPTR_VALIDATE (1 << 2)
46 #define RADEON_GEM_USERPTR_REGISTER (1 << 3)
48 struct drm_radeon_gem_userptr
{
59 enum radeon_generation
{
65 struct radeon_drm_winsys
{
66 struct radeon_winsys base
;
67 struct pipe_reference reference
;
68 struct pb_cache bo_cache
;
70 int fd
; /* DRM file descriptor */
71 int num_cs
; /* The number of command streams created. */
72 uint64_t allocated_vram
;
73 uint64_t allocated_gtt
;
76 uint64_t buffer_wait_time
; /* time spent in buffer_wait in ns */
77 uint64_t num_cs_flushes
;
78 uint32_t next_bo_hash
;
80 enum radeon_generation gen
;
81 struct radeon_info info
;
83 uint32_t va_unmap_working
;
84 uint32_t accel_working2
;
86 /* List of buffer GEM names. Protected by bo_handles_mutex. */
87 struct util_hash_table
*bo_names
;
88 /* List of buffer handles. Protectded by bo_handles_mutex. */
89 struct util_hash_table
*bo_handles
;
90 /* List of buffer virtual memory ranges. Protectded by bo_handles_mutex. */
91 struct util_hash_table
*bo_vas
;
92 pipe_mutex bo_handles_mutex
;
93 pipe_mutex bo_va_mutex
;
94 pipe_mutex bo_fence_lock
;
97 struct list_head va_holes
;
100 struct radeon_surface_manager
*surf_man
;
102 uint32_t num_cpus
; /* Number of CPUs. */
104 struct radeon_drm_cs
*hyperz_owner
;
105 pipe_mutex hyperz_owner_mutex
;
106 struct radeon_drm_cs
*cmask_owner
;
107 pipe_mutex cmask_owner_mutex
;
109 /* multithreaded command submission */
110 struct util_queue cs_queue
;
113 static inline struct radeon_drm_winsys
*
114 radeon_drm_winsys(struct radeon_winsys
*base
)
116 return (struct radeon_drm_winsys
*)base
;
119 void radeon_surface_init_functions(struct radeon_drm_winsys
*ws
);