src/gallium/winsys/radeon/drm/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 /* R300 features in DRM.
  30  *
  31  * 2.6.0:
  32  * - Hyper-Z
  33  * - GB_Z_PEQ_CONFIG on rv350->r4xx
  34  * - R500 FG_ALPHA_VALUE
  35  *
  36  * 2.8.0:
  37  * - R500 US_FORMAT regs
  38  * - R500 ARGB2101010 colorbuffer
  39  * - CMask and AA regs
  40  * - R16F/RG16F
  41  */
  42
  43 #include "pipebuffer/pb_buffer.h"
  44 #include "radeon_surface.h"
  45
  46 #define RADEON_MAX_CMDBUF_DWORDS (16 * 1024)
  47
  48 #define RADEON_FLUSH_ASYNC              (1 << 0)
  49 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1) /* needs DRM 2.12.0 */
  50 #define RADEON_FLUSH_COMPUTE            (1 << 2)
  51 #define RADEON_FLUSH_END_OF_FRAME       (1 << 3)
  52
  53 /* Tiling flags. */
  54 enum radeon_bo_layout {
  55     RADEON_LAYOUT_LINEAR = 0,
  56     RADEON_LAYOUT_TILED,
  57     RADEON_LAYOUT_SQUARETILED,
  58
  59     RADEON_LAYOUT_UNKNOWN
  60 };
  61
  62 enum radeon_bo_domain { /* bitfield */
  63     RADEON_DOMAIN_GTT  = 2,
  64     RADEON_DOMAIN_VRAM = 4,
  65     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  66 };
  67
  68 enum radeon_bo_usage { /* bitfield */
  69     RADEON_USAGE_READ = 2,
  70     RADEON_USAGE_WRITE = 4,
  71     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  72 };
  73
  74 enum radeon_family {
  75     CHIP_UNKNOWN = 0,
  76     CHIP_R300, /* R3xx-based cores. */
  77     CHIP_R350,
  78     CHIP_RV350,
  79     CHIP_RV370,
  80     CHIP_RV380,
  81     CHIP_RS400,
  82     CHIP_RC410,
  83     CHIP_RS480,
  84     CHIP_R420,     /* R4xx-based cores. */
  85     CHIP_R423,
  86     CHIP_R430,
  87     CHIP_R480,
  88     CHIP_R481,
  89     CHIP_RV410,
  90     CHIP_RS600,
  91     CHIP_RS690,
  92     CHIP_RS740,
  93     CHIP_RV515,    /* R5xx-based cores. */
  94     CHIP_R520,
  95     CHIP_RV530,
  96     CHIP_R580,
  97     CHIP_RV560,
  98     CHIP_RV570,
  99     CHIP_R600,
 100     CHIP_RV610,
 101     CHIP_RV630,
 102     CHIP_RV670,
 103     CHIP_RV620,
 104     CHIP_RV635,
 105     CHIP_RS780,
 106     CHIP_RS880,
 107     CHIP_RV770,
 108     CHIP_RV730,
 109     CHIP_RV710,
 110     CHIP_RV740,
 111     CHIP_CEDAR,
 112     CHIP_REDWOOD,
 113     CHIP_JUNIPER,
 114     CHIP_CYPRESS,
 115     CHIP_HEMLOCK,
 116     CHIP_PALM,
 117     CHIP_SUMO,
 118     CHIP_SUMO2,
 119     CHIP_BARTS,
 120     CHIP_TURKS,
 121     CHIP_CAICOS,
 122     CHIP_CAYMAN,
 123     CHIP_ARUBA,
 124     CHIP_TAHITI,
 125     CHIP_PITCAIRN,
 126     CHIP_VERDE,
 127     CHIP_OLAND,
 128     CHIP_HAINAN,
 129     CHIP_BONAIRE,
 130     CHIP_KAVERI,
 131     CHIP_KABINI,
 132     CHIP_HAWAII,
 133     CHIP_LAST,
 134 };
 135
 136 enum chip_class {
 137     CLASS_UNKNOWN = 0,
 138     R300,
 139     R400,
 140     R500,
 141     R600,
 142     R700,
 143     EVERGREEN,
 144     CAYMAN,
 145     SI,
 146     CIK,
 147 };
 148
 149 enum ring_type {
 150     RING_GFX = 0,
 151     RING_DMA,
 152     RING_UVD,
 153     RING_VCE,
 154     RING_LAST,
 155 };
 156
 157 enum radeon_value_id {
 158     RADEON_REQUESTED_VRAM_MEMORY,
 159     RADEON_REQUESTED_GTT_MEMORY,
 160     RADEON_BUFFER_WAIT_TIME_NS,
 161     RADEON_TIMESTAMP,
 162     RADEON_NUM_CS_FLUSHES,
 163     RADEON_NUM_BYTES_MOVED,
 164     RADEON_VRAM_USAGE,
 165     RADEON_GTT_USAGE
 166 };
 167
 168 enum radeon_bo_priority {
 169     RADEON_PRIO_MIN,
 170     RADEON_PRIO_SHADER_DATA, /* shader code, resource descriptors */
 171     RADEON_PRIO_SHADER_BUFFER_RO, /* read-only */
 172     RADEON_PRIO_SHADER_TEXTURE_RO, /* read-only */
 173     RADEON_PRIO_SHADER_RESOURCE_RW, /* buffers, textures, streamout, GS rings, RATs; read/write */
 174     RADEON_PRIO_COLOR_BUFFER,
 175     RADEON_PRIO_DEPTH_BUFFER,
 176     RADEON_PRIO_SHADER_TEXTURE_MSAA,
 177     RADEON_PRIO_COLOR_BUFFER_MSAA,
 178     RADEON_PRIO_DEPTH_BUFFER_MSAA,
 179     RADEON_PRIO_COLOR_META,
 180     RADEON_PRIO_DEPTH_META,
 181     RADEON_PRIO_MAX /* must be <= 15 */
 182 };
 183
 184 struct winsys_handle;
 185 struct radeon_winsys_cs_handle;
 186
 187 struct radeon_winsys_cs {
 188     unsigned                    cdw;  /* Number of used dwords. */
 189     uint32_t                    *buf; /* The command buffer. */
 190     enum ring_type              ring_type;
 191 };
 192
 193 struct radeon_info {
 194     uint32_t                    pci_id;
 195     enum radeon_family          family;
 196     enum chip_class             chip_class;
 197     uint32_t                    gart_size;
 198     uint32_t                    vram_size;
 199
 200     uint32_t                    drm_major; /* version */
 201     uint32_t                    drm_minor;
 202     uint32_t                    drm_patchlevel;
 203
 204     boolean                     has_uvd;
 205     uint32_t                    vce_fw_version;
 206
 207     uint32_t                    r300_num_gb_pipes;
 208     uint32_t                    r300_num_z_pipes;
 209
 210     uint32_t                    r600_num_backends;
 211     uint32_t                    r600_clock_crystal_freq;
 212     uint32_t                    r600_tiling_config;
 213     uint32_t                    r600_num_tile_pipes;
 214     uint32_t                    r600_max_pipes;
 215     boolean                     r600_virtual_address;
 216     boolean                     r600_has_dma;
 217
 218     uint32_t                    r600_backend_map;
 219     boolean                     r600_backend_map_valid;
 220
 221     boolean                     si_tile_mode_array_valid;
 222     uint32_t                    si_tile_mode_array[32];
 223
 224     boolean                     cik_macrotile_mode_array_valid;
 225     uint32_t                    cik_macrotile_mode_array[16];
 226 };
 227
 228 enum radeon_feature_id {
 229     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 230     RADEON_FID_R300_CMASK_ACCESS,
 231 };
 232
 233 struct radeon_winsys {
 234     /**
 235      * The screen object this winsys was created for
 236      */
 237     struct pipe_screen *screen;
 238
 239     /**
 240      * Decrement the winsys reference count.
 241      *
 242      * \param ws  The winsys this function is called for.
 243      * \return    True if the winsys and screen should be destroyed.
 244      */
 245     bool (*unref)(struct radeon_winsys *ws);
 246
 247     /**
 248      * Destroy this winsys.
 249      *
 250      * \param ws        The winsys this function is called from.
 251      */
 252     void (*destroy)(struct radeon_winsys *ws);
 253
 254     /**
 255      * Query an info structure from winsys.
 256      *
 257      * \param ws        The winsys this function is called from.
 258      * \param info      Return structure
 259      */
 260     void (*query_info)(struct radeon_winsys *ws,
 261                        struct radeon_info *info);
 262
 263     /**************************************************************************
 264      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 265      *
 266      * Remember that gallium gets to choose the interface it needs, and the
 267      * window systems must then implement that interface (rather than the
 268      * other way around...).
 269      *************************************************************************/
 270
 271     /**
 272      * Create a buffer object.
 273      *
 274      * \param ws        The winsys this function is called from.
 275      * \param size      The size to allocate.
 276      * \param alignment An alignment of the buffer in memory.
 277      * \param use_reusable_pool Whether the cache buffer manager should be used.
 278      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 279      * \return          The created buffer object.
 280      */
 281     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 282                                        unsigned size,
 283                                        unsigned alignment,
 284                                        boolean use_reusable_pool,
 285                                        enum radeon_bo_domain domain);
 286
 287     struct radeon_winsys_cs_handle *(*buffer_get_cs_handle)(
 288             struct pb_buffer *buf);
 289
 290     /**
 291      * Map the entire data store of a buffer object into the client's address
 292      * space.
 293      *
 294      * \param buf       A winsys buffer object to map.
 295      * \param cs        A command stream to flush if the buffer is referenced by it.
 296      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 297      * \return          The pointer at the beginning of the buffer.
 298      */
 299     void *(*buffer_map)(struct radeon_winsys_cs_handle *buf,
 300                         struct radeon_winsys_cs *cs,
 301                         enum pipe_transfer_usage usage);
 302
 303     /**
 304      * Unmap a buffer object from the client's address space.
 305      *
 306      * \param buf       A winsys buffer object to unmap.
 307      */
 308     void (*buffer_unmap)(struct radeon_winsys_cs_handle *buf);
 309
 310     /**
 311      * Return TRUE if a buffer object is being used by the GPU.
 312      *
 313      * \param buf       A winsys buffer object.
 314      * \param usage     Only check whether the buffer is busy for the given usage.
 315      */
 316     boolean (*buffer_is_busy)(struct pb_buffer *buf,
 317                               enum radeon_bo_usage usage);
 318
 319     /**
 320      * Wait for a buffer object until it is not used by a GPU. This is
 321      * equivalent to a fence placed after the last command using the buffer,
 322      * and synchronizing to the fence.
 323      *
 324      * \param buf       A winsys buffer object to wait for.
 325      * \param usage     Only wait until the buffer is idle for the given usage,
 326      *                  but may still be busy for some other usage.
 327      */
 328     void (*buffer_wait)(struct pb_buffer *buf, enum radeon_bo_usage usage);
 329
 330     /**
 331      * Return tiling flags describing a memory layout of a buffer object.
 332      *
 333      * \param buf       A winsys buffer object to get the flags from.
 334      * \param macrotile A pointer to the return value of the microtile flag.
 335      * \param microtile A pointer to the return value of the macrotile flag.
 336      *
 337      * \note microtile and macrotile are not bitmasks!
 338      */
 339     void (*buffer_get_tiling)(struct pb_buffer *buf,
 340                               enum radeon_bo_layout *microtile,
 341                               enum radeon_bo_layout *macrotile,
 342                               unsigned *bankw, unsigned *bankh,
 343                               unsigned *tile_split,
 344                               unsigned *stencil_tile_split,
 345                               unsigned *mtilea,
 346                               bool *scanout);
 347
 348     /**
 349      * Set tiling flags describing a memory layout of a buffer object.
 350      *
 351      * \param buf       A winsys buffer object to set the flags for.
 352      * \param cs        A command stream to flush if the buffer is referenced by it.
 353      * \param macrotile A macrotile flag.
 354      * \param microtile A microtile flag.
 355      * \param stride    A stride of the buffer in bytes, for texturing.
 356      *
 357      * \note microtile and macrotile are not bitmasks!
 358      */
 359     void (*buffer_set_tiling)(struct pb_buffer *buf,
 360                               struct radeon_winsys_cs *rcs,
 361                               enum radeon_bo_layout microtile,
 362                               enum radeon_bo_layout macrotile,
 363                               unsigned bankw, unsigned bankh,
 364                               unsigned tile_split,
 365                               unsigned stencil_tile_split,
 366                               unsigned mtilea,
 367                               unsigned stride,
 368                               bool scanout);
 369
 370     /**
 371      * Get a winsys buffer from a winsys handle. The internal structure
 372      * of the handle is platform-specific and only a winsys should access it.
 373      *
 374      * \param ws        The winsys this function is called from.
 375      * \param whandle   A winsys handle pointer as was received from a state
 376      *                  tracker.
 377      * \param stride    The returned buffer stride in bytes.
 378      */
 379     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 380                                             struct winsys_handle *whandle,
 381                                             unsigned *stride);
 382
 383     /**
 384      * Get a winsys handle from a winsys buffer. The internal structure
 385      * of the handle is platform-specific and only a winsys should access it.
 386      *
 387      * \param buf       A winsys buffer object to get the handle from.
 388      * \param whandle   A winsys handle pointer.
 389      * \param stride    A stride of the buffer in bytes, for texturing.
 390      * \return          TRUE on success.
 391      */
 392     boolean (*buffer_get_handle)(struct pb_buffer *buf,
 393                                  unsigned stride,
 394                                  struct winsys_handle *whandle);
 395
 396     /**
 397      * Return the virtual address of a buffer.
 398      *
 399      * \param buf       A winsys buffer object
 400      * \return          virtual address
 401      */
 402     uint64_t (*buffer_get_virtual_address)(struct radeon_winsys_cs_handle *buf);
 403
 404     /**
 405      * Query the initial placement of the buffer from the kernel driver.
 406      */
 407     enum radeon_bo_domain (*buffer_get_initial_domain)(struct radeon_winsys_cs_handle *buf);
 408
 409     /**************************************************************************
 410      * Command submission.
 411      *
 412      * Each pipe context should create its own command stream and submit
 413      * commands independently of other contexts.
 414      *************************************************************************/
 415
 416     /**
 417      * Create a command stream.
 418      *
 419      * \param ws        The winsys this function is called from.
 420      * \param ring_type The ring type (GFX, DMA, UVD)
 421      * \param flush     Flush callback function associated with the command stream.
 422      * \param user      User pointer that will be passed to the flush callback.
 423      * \param trace_buf Trace buffer when tracing is enabled
 424      */
 425     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
 426                                           enum ring_type ring_type,
 427                                           void (*flush)(void *ctx, unsigned flags),
 428                                           void *flush_ctx,
 429                                           struct radeon_winsys_cs_handle *trace_buf);
 430
 431     /**
 432      * Destroy a command stream.
 433      *
 434      * \param cs        A command stream to destroy.
 435      */
 436     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 437
 438     /**
 439      * Add a new buffer relocation. Every relocation must first be added
 440      * before it can be written.
 441      *
 442      * \param cs  A command stream to add buffer for validation against.
 443      * \param buf A winsys buffer to validate.
 444      * \param usage   Whether the buffer is used for read and/or write.
 445      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 446      * \param priority  A higher number means a greater chance of being
 447      *                  placed in the requested domain. 15 is the maximum.
 448      * \return Relocation index.
 449      */
 450     unsigned (*cs_add_reloc)(struct radeon_winsys_cs *cs,
 451                              struct radeon_winsys_cs_handle *buf,
 452                              enum radeon_bo_usage usage,
 453                              enum radeon_bo_domain domain,
 454                              enum radeon_bo_priority priority);
 455
 456     /**
 457      * Return the index of an already-added buffer.
 458      *
 459      * \param cs        Command stream
 460      * \param buf       Buffer
 461      * \return          The buffer index, or -1 if the buffer has not been added.
 462      */
 463     int (*cs_get_reloc)(struct radeon_winsys_cs *cs,
 464                         struct radeon_winsys_cs_handle *buf);
 465
 466     /**
 467      * Return TRUE if there is enough memory in VRAM and GTT for the relocs
 468      * added so far. If the validation fails, all the relocations which have
 469      * been added since the last call of cs_validate will be removed and
 470      * the CS will be flushed (provided there are still any relocations).
 471      *
 472      * \param cs        A command stream to validate.
 473      */
 474     boolean (*cs_validate)(struct radeon_winsys_cs *cs);
 475
 476     /**
 477      * Return TRUE if there is enough memory in VRAM and GTT for the relocs
 478      * added so far.
 479      *
 480      * \param cs        A command stream to validate.
 481      * \param vram      VRAM memory size pending to be use
 482      * \param gtt       GTT memory size pending to be use
 483      */
 484     boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
 485
 486     /**
 487      * Flush a command stream.
 488      *
 489      * \param cs          A command stream to flush.
 490      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 491      * \param cs_trace_id A unique identifiant for the cs
 492      */
 493     void (*cs_flush)(struct radeon_winsys_cs *cs, unsigned flags, uint32_t cs_trace_id);
 494
 495     /**
 496      * Return TRUE if a buffer is referenced by a command stream.
 497      *
 498      * \param cs        A command stream.
 499      * \param buf       A winsys buffer.
 500      */
 501     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 502                                        struct radeon_winsys_cs_handle *buf,
 503                                        enum radeon_bo_usage usage);
 504
 505     /**
 506      * Request access to a feature for a command stream.
 507      *
 508      * \param cs        A command stream.
 509      * \param fid       Feature ID, one of RADEON_FID_*
 510      * \param enable    Whether to enable or disable the feature.
 511      */
 512     boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
 513                                   enum radeon_feature_id fid,
 514                                   boolean enable);
 515      /**
 516       * Make sure all asynchronous flush of the cs have completed
 517       *
 518       * \param cs        A command stream.
 519       */
 520     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 521
 522     /**
 523      * Return a fence associated with the CS. The fence will be signalled
 524      * once the CS is flushed and all commands in the CS are completed
 525      * by the GPU.
 526      */
 527     struct pipe_fence_handle *(*cs_create_fence)(struct radeon_winsys_cs *cs);
 528
 529     /**
 530      * Wait for the fence and return true if the fence has been signalled.
 531      * The timeout of 0 will only return the status.
 532      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 533      * is signalled.
 534      */
 535     bool (*fence_wait)(struct radeon_winsys *ws,
 536                        struct pipe_fence_handle *fence,
 537                        uint64_t timeout);
 538
 539     /**
 540      * Reference counting for fences.
 541      */
 542     void (*fence_reference)(struct pipe_fence_handle **dst,
 543                             struct pipe_fence_handle *src);
 544
 545     /**
 546      * Initialize surface
 547      *
 548      * \param ws        The winsys this function is called from.
 549      * \param surf      Surface structure ptr
 550      */
 551     int (*surface_init)(struct radeon_winsys *ws,
 552                         struct radeon_surface *surf);
 553
 554     /**
 555      * Find best values for a surface
 556      *
 557      * \param ws        The winsys this function is called from.
 558      * \param surf      Surface structure ptr
 559      */
 560     int (*surface_best)(struct radeon_winsys *ws,
 561                         struct radeon_surface *surf);
 562
 563     uint64_t (*query_value)(struct radeon_winsys *ws,
 564                             enum radeon_value_id value);
 565 };
 566
 567
 568 static INLINE void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 569 {
 570     cs->buf[cs->cdw++] = value;
 571 }
 572
 573 static INLINE void radeon_emit_array(struct radeon_winsys_cs *cs,
 574                                      const uint32_t *values, unsigned count)
 575 {
 576     memcpy(cs->buf+cs->cdw, values, count * 4);
 577     cs->cdw += count;
 578 }
 579
 580 #endif