src/gallium/winsys/radeon/drm/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 /* R300 features in DRM.
  30  *
  31  * 2.6.0:
  32  * - Hyper-Z
  33  * - GB_Z_PEQ_CONFIG on rv350->r4xx
  34  * - R500 FG_ALPHA_VALUE
  35  *
  36  * 2.8.0:
  37  * - R500 US_FORMAT regs
  38  * - R500 ARGB2101010 colorbuffer
  39  * - CMask and AA regs
  40  * - R16F/RG16F
  41  */
  42
  43 #include "pipebuffer/pb_buffer.h"
  44 #include "radeon_surface.h"
  45
  46 #define RADEON_MAX_CMDBUF_DWORDS (16 * 1024)
  47
  48 #define RADEON_FLUSH_ASYNC              (1 << 0)
  49 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1) /* needs DRM 2.12.0 */
  50 #define RADEON_FLUSH_COMPUTE            (1 << 2)
  51 #define RADEON_FLUSH_END_OF_FRAME       (1 << 3)
  52
  53 /* Tiling flags. */
  54 enum radeon_bo_layout {
  55     RADEON_LAYOUT_LINEAR = 0,
  56     RADEON_LAYOUT_TILED,
  57     RADEON_LAYOUT_SQUARETILED,
  58
  59     RADEON_LAYOUT_UNKNOWN
  60 };
  61
  62 enum radeon_bo_domain { /* bitfield */
  63     RADEON_DOMAIN_GTT  = 2,
  64     RADEON_DOMAIN_VRAM = 4,
  65     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  66 };
  67
  68 enum radeon_bo_flag { /* bitfield */
  69    RADEON_FLAG_GTT_WC = (1 << 0)
  70 };
  71
  72 enum radeon_bo_usage { /* bitfield */
  73     RADEON_USAGE_READ = 2,
  74     RADEON_USAGE_WRITE = 4,
  75     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  76 };
  77
  78 enum radeon_family {
  79     CHIP_UNKNOWN = 0,
  80     CHIP_R300, /* R3xx-based cores. */
  81     CHIP_R350,
  82     CHIP_RV350,
  83     CHIP_RV370,
  84     CHIP_RV380,
  85     CHIP_RS400,
  86     CHIP_RC410,
  87     CHIP_RS480,
  88     CHIP_R420,     /* R4xx-based cores. */
  89     CHIP_R423,
  90     CHIP_R430,
  91     CHIP_R480,
  92     CHIP_R481,
  93     CHIP_RV410,
  94     CHIP_RS600,
  95     CHIP_RS690,
  96     CHIP_RS740,
  97     CHIP_RV515,    /* R5xx-based cores. */
  98     CHIP_R520,
  99     CHIP_RV530,
 100     CHIP_R580,
 101     CHIP_RV560,
 102     CHIP_RV570,
 103     CHIP_R600,
 104     CHIP_RV610,
 105     CHIP_RV630,
 106     CHIP_RV670,
 107     CHIP_RV620,
 108     CHIP_RV635,
 109     CHIP_RS780,
 110     CHIP_RS880,
 111     CHIP_RV770,
 112     CHIP_RV730,
 113     CHIP_RV710,
 114     CHIP_RV740,
 115     CHIP_CEDAR,
 116     CHIP_REDWOOD,
 117     CHIP_JUNIPER,
 118     CHIP_CYPRESS,
 119     CHIP_HEMLOCK,
 120     CHIP_PALM,
 121     CHIP_SUMO,
 122     CHIP_SUMO2,
 123     CHIP_BARTS,
 124     CHIP_TURKS,
 125     CHIP_CAICOS,
 126     CHIP_CAYMAN,
 127     CHIP_ARUBA,
 128     CHIP_TAHITI,
 129     CHIP_PITCAIRN,
 130     CHIP_VERDE,
 131     CHIP_OLAND,
 132     CHIP_HAINAN,
 133     CHIP_BONAIRE,
 134     CHIP_KAVERI,
 135     CHIP_KABINI,
 136     CHIP_HAWAII,
 137     CHIP_MULLINS,
 138     CHIP_LAST,
 139 };
 140
 141 enum chip_class {
 142     CLASS_UNKNOWN = 0,
 143     R300,
 144     R400,
 145     R500,
 146     R600,
 147     R700,
 148     EVERGREEN,
 149     CAYMAN,
 150     SI,
 151     CIK,
 152 };
 153
 154 enum ring_type {
 155     RING_GFX = 0,
 156     RING_DMA,
 157     RING_UVD,
 158     RING_VCE,
 159     RING_LAST,
 160 };
 161
 162 enum radeon_value_id {
 163     RADEON_REQUESTED_VRAM_MEMORY,
 164     RADEON_REQUESTED_GTT_MEMORY,
 165     RADEON_BUFFER_WAIT_TIME_NS,
 166     RADEON_TIMESTAMP,
 167     RADEON_NUM_CS_FLUSHES,
 168     RADEON_NUM_BYTES_MOVED,
 169     RADEON_VRAM_USAGE,
 170     RADEON_GTT_USAGE
 171 };
 172
 173 enum radeon_bo_priority {
 174     RADEON_PRIO_MIN,
 175     RADEON_PRIO_SHADER_DATA, /* shader code, resource descriptors */
 176     RADEON_PRIO_SHADER_BUFFER_RO, /* read-only */
 177     RADEON_PRIO_SHADER_TEXTURE_RO, /* read-only */
 178     RADEON_PRIO_SHADER_RESOURCE_RW, /* buffers, textures, streamout, GS rings, RATs; read/write */
 179     RADEON_PRIO_COLOR_BUFFER,
 180     RADEON_PRIO_DEPTH_BUFFER,
 181     RADEON_PRIO_SHADER_TEXTURE_MSAA,
 182     RADEON_PRIO_COLOR_BUFFER_MSAA,
 183     RADEON_PRIO_DEPTH_BUFFER_MSAA,
 184     RADEON_PRIO_COLOR_META,
 185     RADEON_PRIO_DEPTH_META,
 186     RADEON_PRIO_MAX /* must be <= 15 */
 187 };
 188
 189 struct winsys_handle;
 190 struct radeon_winsys_cs_handle;
 191
 192 struct radeon_winsys_cs {
 193     unsigned                    cdw;  /* Number of used dwords. */
 194     uint32_t                    *buf; /* The command buffer. */
 195     enum ring_type              ring_type;
 196 };
 197
 198 struct radeon_info {
 199     uint32_t                    pci_id;
 200     enum radeon_family          family;
 201     enum chip_class             chip_class;
 202     uint64_t                    gart_size;
 203     uint64_t                    vram_size;
 204     uint32_t                    max_sclk;
 205     uint32_t                    max_compute_units;
 206     uint32_t                    max_se;
 207     uint32_t                    max_sh_per_se;
 208
 209     uint32_t                    drm_major; /* version */
 210     uint32_t                    drm_minor;
 211     uint32_t                    drm_patchlevel;
 212
 213     boolean                     has_uvd;
 214     uint32_t                    vce_fw_version;
 215
 216     uint32_t                    r300_num_gb_pipes;
 217     uint32_t                    r300_num_z_pipes;
 218
 219     uint32_t                    r600_num_backends;
 220     uint32_t                    r600_clock_crystal_freq;
 221     uint32_t                    r600_tiling_config;
 222     uint32_t                    r600_num_tile_pipes;
 223     uint32_t                    r600_max_pipes;
 224     boolean                     r600_virtual_address;
 225     boolean                     r600_has_dma;
 226
 227     uint32_t                    r600_backend_map;
 228     boolean                     r600_backend_map_valid;
 229
 230     boolean                     si_tile_mode_array_valid;
 231     uint32_t                    si_tile_mode_array[32];
 232
 233     boolean                     cik_macrotile_mode_array_valid;
 234     uint32_t                    cik_macrotile_mode_array[16];
 235 };
 236
 237 enum radeon_feature_id {
 238     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 239     RADEON_FID_R300_CMASK_ACCESS,
 240 };
 241
 242 struct radeon_winsys {
 243     /**
 244      * The screen object this winsys was created for
 245      */
 246     struct pipe_screen *screen;
 247
 248     /**
 249      * Decrement the winsys reference count.
 250      *
 251      * \param ws  The winsys this function is called for.
 252      * \return    True if the winsys and screen should be destroyed.
 253      */
 254     bool (*unref)(struct radeon_winsys *ws);
 255
 256     /**
 257      * Destroy this winsys.
 258      *
 259      * \param ws        The winsys this function is called from.
 260      */
 261     void (*destroy)(struct radeon_winsys *ws);
 262
 263     /**
 264      * Query an info structure from winsys.
 265      *
 266      * \param ws        The winsys this function is called from.
 267      * \param info      Return structure
 268      */
 269     void (*query_info)(struct radeon_winsys *ws,
 270                        struct radeon_info *info);
 271
 272     /**************************************************************************
 273      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 274      *
 275      * Remember that gallium gets to choose the interface it needs, and the
 276      * window systems must then implement that interface (rather than the
 277      * other way around...).
 278      *************************************************************************/
 279
 280     /**
 281      * Create a buffer object.
 282      *
 283      * \param ws        The winsys this function is called from.
 284      * \param size      The size to allocate.
 285      * \param alignment An alignment of the buffer in memory.
 286      * \param use_reusable_pool Whether the cache buffer manager should be used.
 287      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 288      * \return          The created buffer object.
 289      */
 290     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 291                                        unsigned size,
 292                                        unsigned alignment,
 293                                        boolean use_reusable_pool,
 294                                        enum radeon_bo_domain domain,
 295                                        enum radeon_bo_flag flags);
 296
 297     struct radeon_winsys_cs_handle *(*buffer_get_cs_handle)(
 298             struct pb_buffer *buf);
 299
 300     /**
 301      * Map the entire data store of a buffer object into the client's address
 302      * space.
 303      *
 304      * \param buf       A winsys buffer object to map.
 305      * \param cs        A command stream to flush if the buffer is referenced by it.
 306      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 307      * \return          The pointer at the beginning of the buffer.
 308      */
 309     void *(*buffer_map)(struct radeon_winsys_cs_handle *buf,
 310                         struct radeon_winsys_cs *cs,
 311                         enum pipe_transfer_usage usage);
 312
 313     /**
 314      * Unmap a buffer object from the client's address space.
 315      *
 316      * \param buf       A winsys buffer object to unmap.
 317      */
 318     void (*buffer_unmap)(struct radeon_winsys_cs_handle *buf);
 319
 320     /**
 321      * Return TRUE if a buffer object is being used by the GPU.
 322      *
 323      * \param buf       A winsys buffer object.
 324      * \param usage     Only check whether the buffer is busy for the given usage.
 325      */
 326     boolean (*buffer_is_busy)(struct pb_buffer *buf,
 327                               enum radeon_bo_usage usage);
 328
 329     /**
 330      * Wait for a buffer object until it is not used by a GPU. This is
 331      * equivalent to a fence placed after the last command using the buffer,
 332      * and synchronizing to the fence.
 333      *
 334      * \param buf       A winsys buffer object to wait for.
 335      * \param usage     Only wait until the buffer is idle for the given usage,
 336      *                  but may still be busy for some other usage.
 337      */
 338     void (*buffer_wait)(struct pb_buffer *buf, enum radeon_bo_usage usage);
 339
 340     /**
 341      * Return tiling flags describing a memory layout of a buffer object.
 342      *
 343      * \param buf       A winsys buffer object to get the flags from.
 344      * \param macrotile A pointer to the return value of the microtile flag.
 345      * \param microtile A pointer to the return value of the macrotile flag.
 346      *
 347      * \note microtile and macrotile are not bitmasks!
 348      */
 349     void (*buffer_get_tiling)(struct pb_buffer *buf,
 350                               enum radeon_bo_layout *microtile,
 351                               enum radeon_bo_layout *macrotile,
 352                               unsigned *bankw, unsigned *bankh,
 353                               unsigned *tile_split,
 354                               unsigned *stencil_tile_split,
 355                               unsigned *mtilea,
 356                               bool *scanout);
 357
 358     /**
 359      * Set tiling flags describing a memory layout of a buffer object.
 360      *
 361      * \param buf       A winsys buffer object to set the flags for.
 362      * \param cs        A command stream to flush if the buffer is referenced by it.
 363      * \param macrotile A macrotile flag.
 364      * \param microtile A microtile flag.
 365      * \param stride    A stride of the buffer in bytes, for texturing.
 366      *
 367      * \note microtile and macrotile are not bitmasks!
 368      */
 369     void (*buffer_set_tiling)(struct pb_buffer *buf,
 370                               struct radeon_winsys_cs *rcs,
 371                               enum radeon_bo_layout microtile,
 372                               enum radeon_bo_layout macrotile,
 373                               unsigned bankw, unsigned bankh,
 374                               unsigned tile_split,
 375                               unsigned stencil_tile_split,
 376                               unsigned mtilea,
 377                               unsigned stride,
 378                               bool scanout);
 379
 380     /**
 381      * Get a winsys buffer from a winsys handle. The internal structure
 382      * of the handle is platform-specific and only a winsys should access it.
 383      *
 384      * \param ws        The winsys this function is called from.
 385      * \param whandle   A winsys handle pointer as was received from a state
 386      *                  tracker.
 387      * \param stride    The returned buffer stride in bytes.
 388      */
 389     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 390                                             struct winsys_handle *whandle,
 391                                             unsigned *stride);
 392
 393     /**
 394      * Get a winsys handle from a winsys buffer. The internal structure
 395      * of the handle is platform-specific and only a winsys should access it.
 396      *
 397      * \param buf       A winsys buffer object to get the handle from.
 398      * \param whandle   A winsys handle pointer.
 399      * \param stride    A stride of the buffer in bytes, for texturing.
 400      * \return          TRUE on success.
 401      */
 402     boolean (*buffer_get_handle)(struct pb_buffer *buf,
 403                                  unsigned stride,
 404                                  struct winsys_handle *whandle);
 405
 406     /**
 407      * Return the virtual address of a buffer.
 408      *
 409      * \param buf       A winsys buffer object
 410      * \return          virtual address
 411      */
 412     uint64_t (*buffer_get_virtual_address)(struct radeon_winsys_cs_handle *buf);
 413
 414     /**
 415      * Query the initial placement of the buffer from the kernel driver.
 416      */
 417     enum radeon_bo_domain (*buffer_get_initial_domain)(struct radeon_winsys_cs_handle *buf);
 418
 419     /**************************************************************************
 420      * Command submission.
 421      *
 422      * Each pipe context should create its own command stream and submit
 423      * commands independently of other contexts.
 424      *************************************************************************/
 425
 426     /**
 427      * Create a command stream.
 428      *
 429      * \param ws        The winsys this function is called from.
 430      * \param ring_type The ring type (GFX, DMA, UVD)
 431      * \param flush     Flush callback function associated with the command stream.
 432      * \param user      User pointer that will be passed to the flush callback.
 433      * \param trace_buf Trace buffer when tracing is enabled
 434      */
 435     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
 436                                           enum ring_type ring_type,
 437                                           void (*flush)(void *ctx, unsigned flags,
 438                                                         struct pipe_fence_handle **fence),
 439                                           void *flush_ctx,
 440                                           struct radeon_winsys_cs_handle *trace_buf);
 441
 442     /**
 443      * Destroy a command stream.
 444      *
 445      * \param cs        A command stream to destroy.
 446      */
 447     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 448
 449     /**
 450      * Add a new buffer relocation. Every relocation must first be added
 451      * before it can be written.
 452      *
 453      * \param cs  A command stream to add buffer for validation against.
 454      * \param buf A winsys buffer to validate.
 455      * \param usage   Whether the buffer is used for read and/or write.
 456      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 457      * \param priority  A higher number means a greater chance of being
 458      *                  placed in the requested domain. 15 is the maximum.
 459      * \return Relocation index.
 460      */
 461     unsigned (*cs_add_reloc)(struct radeon_winsys_cs *cs,
 462                              struct radeon_winsys_cs_handle *buf,
 463                              enum radeon_bo_usage usage,
 464                              enum radeon_bo_domain domain,
 465                              enum radeon_bo_priority priority);
 466
 467     /**
 468      * Return the index of an already-added buffer.
 469      *
 470      * \param cs        Command stream
 471      * \param buf       Buffer
 472      * \return          The buffer index, or -1 if the buffer has not been added.
 473      */
 474     int (*cs_get_reloc)(struct radeon_winsys_cs *cs,
 475                         struct radeon_winsys_cs_handle *buf);
 476
 477     /**
 478      * Return TRUE if there is enough memory in VRAM and GTT for the relocs
 479      * added so far. If the validation fails, all the relocations which have
 480      * been added since the last call of cs_validate will be removed and
 481      * the CS will be flushed (provided there are still any relocations).
 482      *
 483      * \param cs        A command stream to validate.
 484      */
 485     boolean (*cs_validate)(struct radeon_winsys_cs *cs);
 486
 487     /**
 488      * Return TRUE if there is enough memory in VRAM and GTT for the relocs
 489      * added so far.
 490      *
 491      * \param cs        A command stream to validate.
 492      * \param vram      VRAM memory size pending to be use
 493      * \param gtt       GTT memory size pending to be use
 494      */
 495     boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
 496
 497     /**
 498      * Flush a command stream.
 499      *
 500      * \param cs          A command stream to flush.
 501      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 502      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 503      *                    after the CS and is returned through this parameter.
 504      * \param cs_trace_id A unique identifier of the cs, used for tracing.
 505      */
 506     void (*cs_flush)(struct radeon_winsys_cs *cs,
 507                      unsigned flags,
 508                      struct pipe_fence_handle **fence,
 509                      uint32_t cs_trace_id);
 510
 511     /**
 512      * Return TRUE if a buffer is referenced by a command stream.
 513      *
 514      * \param cs        A command stream.
 515      * \param buf       A winsys buffer.
 516      */
 517     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 518                                        struct radeon_winsys_cs_handle *buf,
 519                                        enum radeon_bo_usage usage);
 520
 521     /**
 522      * Request access to a feature for a command stream.
 523      *
 524      * \param cs        A command stream.
 525      * \param fid       Feature ID, one of RADEON_FID_*
 526      * \param enable    Whether to enable or disable the feature.
 527      */
 528     boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
 529                                   enum radeon_feature_id fid,
 530                                   boolean enable);
 531      /**
 532       * Make sure all asynchronous flush of the cs have completed
 533       *
 534       * \param cs        A command stream.
 535       */
 536     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 537
 538     /**
 539      * Wait for the fence and return true if the fence has been signalled.
 540      * The timeout of 0 will only return the status.
 541      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 542      * is signalled.
 543      */
 544     bool (*fence_wait)(struct radeon_winsys *ws,
 545                        struct pipe_fence_handle *fence,
 546                        uint64_t timeout);
 547
 548     /**
 549      * Reference counting for fences.
 550      */
 551     void (*fence_reference)(struct pipe_fence_handle **dst,
 552                             struct pipe_fence_handle *src);
 553
 554     /**
 555      * Initialize surface
 556      *
 557      * \param ws        The winsys this function is called from.
 558      * \param surf      Surface structure ptr
 559      */
 560     int (*surface_init)(struct radeon_winsys *ws,
 561                         struct radeon_surface *surf);
 562
 563     /**
 564      * Find best values for a surface
 565      *
 566      * \param ws        The winsys this function is called from.
 567      * \param surf      Surface structure ptr
 568      */
 569     int (*surface_best)(struct radeon_winsys *ws,
 570                         struct radeon_surface *surf);
 571
 572     uint64_t (*query_value)(struct radeon_winsys *ws,
 573                             enum radeon_value_id value);
 574 };
 575
 576
 577 static INLINE void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 578 {
 579     cs->buf[cs->cdw++] = value;
 580 }
 581
 582 static INLINE void radeon_emit_array(struct radeon_winsys_cs *cs,
 583                                      const uint32_t *values, unsigned count)
 584 {
 585     memcpy(cs->buf+cs->cdw, values, count * 4);
 586     cs->cdw += count;
 587 }
 588
 589 #endif