src/gallium/winsys/radeon/tools/radeon_ctx.h

   1 /*
   2  * Copyright 2011 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jérôme Glisse
  25  */
  26 #ifndef RADEON_CTX_H
  27 #define RADEON_CTX_H
  28
  29 #define _FILE_OFFSET_BITS 64
  30 #include <sys/mman.h>
  31
  32 #include <errno.h>
  33 #include <stdio.h>
  34 #include <stdlib.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include "xf86drm.h"
  38 #include "radeon_drm.h"
  39
  40 #ifndef RADEON_CHUNK_ID_FLAGS
  41 #define RADEON_CHUNK_ID_FLAGS       0x03
  42 /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
  43 #define RADEON_CS_KEEP_TILING_FLAGS 0x01
  44 #endif
  45
  46
  47 #ifndef RADEON_VA_MAP
  48
  49 #define RADEON_VA_MAP               1
  50 #define RADEON_VA_UNMAP             2
  51 #define RADEON_VA_RESULT_OK         0
  52 #define RADEON_VA_RESULT_ERROR      1
  53 #define RADEON_VA_RESULT_VA_EXIST   2
  54 #define RADEON_VM_PAGE_VALID        (1 << 0)
  55 #define RADEON_VM_PAGE_READABLE     (1 << 1)
  56 #define RADEON_VM_PAGE_WRITEABLE    (1 << 2)
  57 #define RADEON_VM_PAGE_SYSTEM       (1 << 3)
  58 #define RADEON_VM_PAGE_SNOOPED      (1 << 4)
  59 struct drm_radeon_gem_va {
  60     uint32_t    handle;
  61     uint32_t    operation;
  62     uint32_t    vm_id;
  63     uint32_t    flags;
  64     uint64_t    offset;
  65 };
  66 #define DRM_RADEON_GEM_VA   0x2b
  67 #endif
  68
  69
  70 struct ctx {
  71     int                         fd;
  72 };
  73
  74 struct bo {
  75     uint32_t                    handle;
  76     uint32_t                    alignment;
  77     uint64_t                    size;
  78     uint64_t                    va;
  79     void                        *ptr;
  80 };
  81
  82 static void ctx_init(struct ctx *ctx)
  83 {
  84     ctx->fd = drmOpen("radeon", NULL);
  85     if (ctx->fd < 0) {
  86         fprintf(stderr, "failed to open radeon drm device file\n");
  87         exit(-1);
  88     }
  89 }
  90
  91 static void bo_wait(struct ctx *ctx, struct bo *bo)
  92 {
  93     struct drm_radeon_gem_wait_idle args;
  94     void *ptr;
  95     int r;
  96
  97     /* Zero out args to make valgrind happy */
  98     memset(&args, 0, sizeof(args));
  99     args.handle = bo->handle;
 100     do {
 101         r = drmCommandWriteRead(ctx->fd, DRM_RADEON_GEM_WAIT_IDLE, &args, sizeof(args));
 102     } while (r == -EBUSY);
 103 }
 104
 105
 106 static void ctx_cs(struct ctx *ctx, uint32_t *cs, uint32_t cs_flags[2], unsigned ndw,
 107                    struct bo **bo, uint32_t *bo_relocs, unsigned nbo)
 108 {
 109     struct drm_radeon_cs args;
 110     struct drm_radeon_cs_chunk chunks[3];
 111     uint64_t chunk_array[3];
 112     unsigned i;
 113     int r;
 114
 115     /* update handle */
 116     for (i = 0; i < nbo; i++) {
 117         bo_relocs[i*4+0] = bo[i]->handle;
 118     }
 119
 120     args.num_chunks = 2;
 121     if (cs_flags[0] || cs_flags[1]) {
 122         /* enable RADEON_CHUNK_ID_FLAGS */
 123         args.num_chunks = 3;
 124     }
 125     args.chunks = (uint64_t)(uintptr_t)chunk_array;
 126     chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
 127     chunks[0].length_dw = ndw;
 128     chunks[0].chunk_data = (uintptr_t)cs;
 129     chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
 130     chunks[1].length_dw = nbo * 4;
 131     chunks[1].chunk_data = (uintptr_t)bo_relocs;
 132     chunks[2].chunk_id = RADEON_CHUNK_ID_FLAGS;
 133     chunks[2].length_dw = 2;
 134     chunks[2].chunk_data = (uintptr_t)cs_flags;
 135     chunk_array[0] = (uintptr_t)&chunks[0];
 136     chunk_array[1] = (uintptr_t)&chunks[1];
 137     chunk_array[2] = (uintptr_t)&chunks[2];
 138
 139     fprintf(stderr, "emiting cs %ddw with %d bo\n", ndw, nbo);
 140     r = drmCommandWriteRead(ctx->fd, DRM_RADEON_CS, &args, sizeof(args));
 141     if (r) {
 142         fprintf(stderr, "cs submission failed with %d\n", r);
 143         return;
 144     }
 145 }
 146
 147 static void bo_map(struct ctx *ctx, struct bo *bo)
 148 {
 149     struct drm_radeon_gem_mmap args;
 150     void *ptr;
 151     int r;
 152
 153     /* Zero out args to make valgrind happy */
 154     memset(&args, 0, sizeof(args));
 155     args.handle = bo->handle;
 156     args.offset = 0;
 157     args.size = (uint64_t)bo->size;
 158     r = drmCommandWriteRead(ctx->fd, DRM_RADEON_GEM_MMAP, &args, sizeof(args));
 159     if (r) {
 160         fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n", bo, bo->handle, r);
 161         exit(-1);
 162     }
 163     ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, ctx->fd, args.addr_ptr);
 164     if (ptr == MAP_FAILED) {
 165         fprintf(stderr, "%s failed to map bo\n", __func__);
 166         exit(-1);
 167     }
 168     bo->ptr = ptr;
 169 }
 170
 171 static void bo_va(struct ctx *ctx, struct bo *bo)
 172 {
 173     struct drm_radeon_gem_va args;
 174     int r;
 175
 176     args.handle = bo->handle;
 177     args.vm_id = 0;
 178     args.operation = RADEON_VA_MAP;
 179     args.flags = RADEON_VM_PAGE_READABLE | RADEON_VM_PAGE_WRITEABLE | RADEON_VM_PAGE_SNOOPED;
 180     args.offset = bo->va;
 181     r = drmCommandWriteRead(ctx->fd, DRM_RADEON_GEM_VA, &args, sizeof(args));
 182     if (r && args.operation == RADEON_VA_RESULT_ERROR) {
 183         fprintf(stderr, "radeon: Failed to allocate virtual address for buffer:\n");
 184         fprintf(stderr, "radeon:    size      : %d bytes\n", bo->size);
 185         fprintf(stderr, "radeon:    alignment : %d bytes\n", bo->alignment);
 186         fprintf(stderr, "radeon:    va        : 0x%016llx\n", (unsigned long long)bo->va);
 187         exit(-1);
 188     }
 189 }
 190
 191 static struct bo *bo_new(struct ctx *ctx, unsigned ndw, uint32_t *data, uint64_t va, uint32_t alignment)
 192 {
 193     struct drm_radeon_gem_create args;
 194     struct bo *bo;
 195     int r;
 196
 197     bo = calloc(1, sizeof(*bo));
 198     if (bo == NULL) {
 199         fprintf(stderr, "failed to malloc bo struct\n");
 200         exit(-1);
 201     }
 202     bo->size = ndw * 4ULL;
 203     bo->va = va;
 204     bo->alignment = alignment;
 205
 206     args.size = bo->size;
 207     args.alignment = bo->alignment;
 208     args.initial_domain = RADEON_GEM_DOMAIN_GTT;
 209     args.flags = 0;
 210     args.handle = 0;
 211
 212     r = drmCommandWriteRead(ctx->fd, DRM_RADEON_GEM_CREATE, &args, sizeof(args));
 213     bo->handle = args.handle;
 214     if (r) {
 215         fprintf(stderr, "Failed to allocate :\n");
 216         fprintf(stderr, "   size      : %d bytes\n", bo->size);
 217         fprintf(stderr, "   alignment : %d bytes\n", bo->alignment);
 218         free(bo);
 219         exit(-1);
 220     }
 221
 222     if (data) {
 223         bo_map(ctx, bo);
 224         memcpy(bo->ptr, data, bo->size);
 225     }
 226
 227     if (va) {
 228         bo_va(ctx, bo);
 229     }
 230
 231     return bo;
 232 }
 233
 234
 235 #endif