src/gallium/winsys/svga/drm/vmwgfx_drm.h

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
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   6  * Permission is hereby granted, free of charge, to any person obtaining a
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  11  * permit persons to whom the Software is furnished to do so, subject to
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  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
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  26  **************************************************************************/
  27
  28 #ifndef __VMWGFX_DRM_H__
  29 #define __VMWGFX_DRM_H__
  30
  31 #ifndef __KERNEL__
  32 #include <drm.h>
  33 #endif
  34
  35 #define DRM_VMW_MAX_SURFACE_FACES 6
  36 #define DRM_VMW_MAX_MIP_LEVELS 24
  37
  38
  39 #define DRM_VMW_GET_PARAM            0
  40 #define DRM_VMW_ALLOC_DMABUF         1
  41 #define DRM_VMW_UNREF_DMABUF         2
  42 #define DRM_VMW_CURSOR_BYPASS        3
  43 /* guarded by DRM_VMW_PARAM_NUM_STREAMS != 0*/
  44 #define DRM_VMW_CONTROL_STREAM       4
  45 #define DRM_VMW_CLAIM_STREAM         5
  46 #define DRM_VMW_UNREF_STREAM         6
  47 /* guarded by DRM_VMW_PARAM_3D == 1 */
  48 #define DRM_VMW_CREATE_CONTEXT       7
  49 #define DRM_VMW_UNREF_CONTEXT        8
  50 #define DRM_VMW_CREATE_SURFACE       9
  51 #define DRM_VMW_UNREF_SURFACE        10
  52 #define DRM_VMW_REF_SURFACE          11
  53 #define DRM_VMW_EXECBUF              12
  54 #define DRM_VMW_GET_3D_CAP           13
  55 #define DRM_VMW_FENCE_WAIT           14
  56 #define DRM_VMW_FENCE_SIGNALED       15
  57 #define DRM_VMW_FENCE_UNREF          16
  58 #define DRM_VMW_FENCE_EVENT          17
  59 #define DRM_VMW_PRESENT              18
  60 #define DRM_VMW_PRESENT_READBACK     19
  61 #define DRM_VMW_UPDATE_LAYOUT        20
  62 #define DRM_VMW_CREATE_SHADER        21
  63 #define DRM_VMW_UNREF_SHADER         22
  64 #define DRM_VMW_GB_SURFACE_CREATE    23
  65 #define DRM_VMW_GB_SURFACE_REF       24
  66 #define DRM_VMW_SYNCCPU              25
  67
  68 /*************************************************************************/
  69 /**
  70  * DRM_VMW_GET_PARAM - get device information.
  71  *
  72  * DRM_VMW_PARAM_FIFO_OFFSET:
  73  * Offset to use to map the first page of the FIFO read-only.
  74  * The fifo is mapped using the mmap() system call on the drm device.
  75  *
  76  * DRM_VMW_PARAM_OVERLAY_IOCTL:
  77  * Does the driver support the overlay ioctl.
  78  */
  79
  80 #define DRM_VMW_PARAM_NUM_STREAMS      0
  81 #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1
  82 #define DRM_VMW_PARAM_3D               2
  83 #define DRM_VMW_PARAM_HW_CAPS          3
  84 #define DRM_VMW_PARAM_FIFO_CAPS        4
  85 #define DRM_VMW_PARAM_MAX_FB_SIZE      5
  86 #define DRM_VMW_PARAM_FIFO_HW_VERSION  6
  87 #define DRM_VMW_PARAM_MAX_SURF_MEMORY  7
  88 #define DRM_VMW_PARAM_3D_CAPS_SIZE     8
  89 #define DRM_VMW_PARAM_MAX_MOB_MEMORY   9
  90
  91 /**
  92  * struct drm_vmw_getparam_arg
  93  *
  94  * @value: Returned value. //Out
  95  * @param: Parameter to query. //In.
  96  *
  97  * Argument to the DRM_VMW_GET_PARAM Ioctl.
  98  */
  99
 100 struct drm_vmw_getparam_arg {
 101         uint64_t value;
 102         uint32_t param;
 103         uint32_t pad64;
 104 };
 105
 106 /*************************************************************************/
 107 /**
 108  * DRM_VMW_CREATE_CONTEXT - Create a host context.
 109  *
 110  * Allocates a device unique context id, and queues a create context command
 111  * for the host. Does not wait for host completion.
 112  */
 113
 114 /**
 115  * struct drm_vmw_context_arg
 116  *
 117  * @cid: Device unique context ID.
 118  *
 119  * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl.
 120  * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl.
 121  */
 122
 123 struct drm_vmw_context_arg {
 124         int32_t cid;
 125         uint32_t pad64;
 126 };
 127
 128 /*************************************************************************/
 129 /**
 130  * DRM_VMW_UNREF_CONTEXT - Create a host context.
 131  *
 132  * Frees a global context id, and queues a destroy host command for the host.
 133  * Does not wait for host completion. The context ID can be used directly
 134  * in the command stream and shows up as the same context ID on the host.
 135  */
 136
 137 /*************************************************************************/
 138 /**
 139  * DRM_VMW_CREATE_SURFACE - Create a host suface.
 140  *
 141  * Allocates a device unique surface id, and queues a create surface command
 142  * for the host. Does not wait for host completion. The surface ID can be
 143  * used directly in the command stream and shows up as the same surface
 144  * ID on the host.
 145  */
 146
 147 /**
 148  * struct drm_wmv_surface_create_req
 149  *
 150  * @flags: Surface flags as understood by the host.
 151  * @format: Surface format as understood by the host.
 152  * @mip_levels: Number of mip levels for each face.
 153  * An unused face should have 0 encoded.
 154  * @size_addr: Address of a user-space array of sruct drm_vmw_size
 155  * cast to an uint64_t for 32-64 bit compatibility.
 156  * The size of the array should equal the total number of mipmap levels.
 157  * @shareable: Boolean whether other clients (as identified by file descriptors)
 158  * may reference this surface.
 159  * @scanout: Boolean whether the surface is intended to be used as a
 160  * scanout.
 161  *
 162  * Input data to the DRM_VMW_CREATE_SURFACE Ioctl.
 163  * Output data from the DRM_VMW_REF_SURFACE Ioctl.
 164  */
 165
 166 struct drm_vmw_surface_create_req {
 167         uint32_t flags;
 168         uint32_t format;
 169         uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES];
 170         uint64_t size_addr;
 171         int32_t shareable;
 172         int32_t scanout;
 173 };
 174
 175 /**
 176  * struct drm_wmv_surface_arg
 177  *
 178  * @sid: Surface id of created surface or surface to destroy or reference.
 179  *
 180  * Output data from the DRM_VMW_CREATE_SURFACE Ioctl.
 181  * Input argument to the DRM_VMW_UNREF_SURFACE Ioctl.
 182  * Input argument to the DRM_VMW_REF_SURFACE Ioctl.
 183  */
 184
 185 struct drm_vmw_surface_arg {
 186         int32_t sid;
 187         uint32_t pad64;
 188 };
 189
 190 /**
 191  * struct drm_vmw_size ioctl.
 192  *
 193  * @width - mip level width
 194  * @height - mip level height
 195  * @depth - mip level depth
 196  *
 197  * Description of a mip level.
 198  * Input data to the DRM_WMW_CREATE_SURFACE Ioctl.
 199  */
 200
 201 struct drm_vmw_size {
 202         uint32_t width;
 203         uint32_t height;
 204         uint32_t depth;
 205         uint32_t pad64;
 206 };
 207
 208 /**
 209  * union drm_vmw_surface_create_arg
 210  *
 211  * @rep: Output data as described above.
 212  * @req: Input data as described above.
 213  *
 214  * Argument to the DRM_VMW_CREATE_SURFACE Ioctl.
 215  */
 216
 217 union drm_vmw_surface_create_arg {
 218         struct drm_vmw_surface_arg rep;
 219         struct drm_vmw_surface_create_req req;
 220 };
 221
 222 /*************************************************************************/
 223 /**
 224  * DRM_VMW_REF_SURFACE - Reference a host surface.
 225  *
 226  * Puts a reference on a host surface with a give sid, as previously
 227  * returned by the DRM_VMW_CREATE_SURFACE ioctl.
 228  * A reference will make sure the surface isn't destroyed while we hold
 229  * it and will allow the calling client to use the surface ID in the command
 230  * stream.
 231  *
 232  * On successful return, the Ioctl returns the surface information given
 233  * in the DRM_VMW_CREATE_SURFACE ioctl.
 234  */
 235
 236 /**
 237  * union drm_vmw_surface_reference_arg
 238  *
 239  * @rep: Output data as described above.
 240  * @req: Input data as described above.
 241  *
 242  * Argument to the DRM_VMW_REF_SURFACE Ioctl.
 243  */
 244
 245 union drm_vmw_surface_reference_arg {
 246         struct drm_vmw_surface_create_req rep;
 247         struct drm_vmw_surface_arg req;
 248 };
 249
 250 /*************************************************************************/
 251 /**
 252  * DRM_VMW_UNREF_SURFACE - Unreference a host surface.
 253  *
 254  * Clear a reference previously put on a host surface.
 255  * When all references are gone, including the one implicitly placed
 256  * on creation,
 257  * a destroy surface command will be queued for the host.
 258  * Does not wait for completion.
 259  */
 260
 261 /*************************************************************************/
 262 /**
 263  * DRM_VMW_EXECBUF
 264  *
 265  * Submit a command buffer for execution on the host, and return a
 266  * fence seqno that when signaled, indicates that the command buffer has
 267  * executed.
 268  */
 269
 270 /**
 271  * struct drm_vmw_execbuf_arg
 272  *
 273  * @commands: User-space address of a command buffer cast to an uint64_t.
 274  * @command-size: Size in bytes of the command buffer.
 275  * @throttle-us: Sleep until software is less than @throttle_us
 276  * microseconds ahead of hardware. The driver may round this value
 277  * to the nearest kernel tick.
 278  * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an
 279  * uint64_t.
 280  * @version: Allows expanding the execbuf ioctl parameters without breaking
 281  * backwards compatibility, since user-space will always tell the kernel
 282  * which version it uses.
 283  * @flags: Execbuf flags. None currently.
 284  *
 285  * Argument to the DRM_VMW_EXECBUF Ioctl.
 286  */
 287
 288 #define DRM_VMW_EXECBUF_VERSION 1
 289
 290 struct drm_vmw_execbuf_arg {
 291         uint64_t commands;
 292         uint32_t command_size;
 293         uint32_t throttle_us;
 294         uint64_t fence_rep;
 295         uint32_t version;
 296         uint32_t flags;
 297 };
 298
 299 /**
 300  * struct drm_vmw_fence_rep
 301  *
 302  * @handle: Fence object handle for fence associated with a command submission.
 303  * @mask: Fence flags relevant for this fence object.
 304  * @seqno: Fence sequence number in fifo. A fence object with a lower
 305  * seqno will signal the EXEC flag before a fence object with a higher
 306  * seqno. This can be used by user-space to avoid kernel calls to determine
 307  * whether a fence has signaled the EXEC flag. Note that @seqno will
 308  * wrap at 32-bit.
 309  * @passed_seqno: The highest seqno number processed by the hardware
 310  * so far. This can be used to mark user-space fence objects as signaled, and
 311  * to determine whether a fence seqno might be stale.
 312  * @error: This member should've been set to -EFAULT on submission.
 313  * The following actions should be take on completion:
 314  * error == -EFAULT: Fence communication failed. The host is synchronized.
 315  * Use the last fence id read from the FIFO fence register.
 316  * error != 0 && error != -EFAULT:
 317  * Fence submission failed. The host is synchronized. Use the fence_seq member.
 318  * error == 0: All is OK, The host may not be synchronized.
 319  * Use the fence_seq member.
 320  *
 321  * Input / Output data to the DRM_VMW_EXECBUF Ioctl.
 322  */
 323
 324 struct drm_vmw_fence_rep {
 325         uint32_t handle;
 326         uint32_t mask;
 327         uint32_t seqno;
 328         uint32_t passed_seqno;
 329         uint32_t pad64;
 330         int32_t error;
 331 };
 332
 333 /*************************************************************************/
 334 /**
 335  * DRM_VMW_ALLOC_DMABUF
 336  *
 337  * Allocate a DMA buffer that is visible also to the host.
 338  * NOTE: The buffer is
 339  * identified by a handle and an offset, which are private to the guest, but
 340  * useable in the command stream. The guest kernel may translate these
 341  * and patch up the command stream accordingly. In the future, the offset may
 342  * be zero at all times, or it may disappear from the interface before it is
 343  * fixed.
 344  *
 345  * The DMA buffer may stay user-space mapped in the guest at all times,
 346  * and is thus suitable for sub-allocation.
 347  *
 348  * DMA buffers are mapped using the mmap() syscall on the drm device.
 349  */
 350
 351 /**
 352  * struct drm_vmw_alloc_dmabuf_req
 353  *
 354  * @size: Required minimum size of the buffer.
 355  *
 356  * Input data to the DRM_VMW_ALLOC_DMABUF Ioctl.
 357  */
 358
 359 struct drm_vmw_alloc_dmabuf_req {
 360         uint32_t size;
 361         uint32_t pad64;
 362 };
 363
 364 /**
 365  * struct drm_vmw_dmabuf_rep
 366  *
 367  * @map_handle: Offset to use in the mmap() call used to map the buffer.
 368  * @handle: Handle unique to this buffer. Used for unreferencing.
 369  * @cur_gmr_id: GMR id to use in the command stream when this buffer is
 370  * referenced. See not above.
 371  * @cur_gmr_offset: Offset to use in the command stream when this buffer is
 372  * referenced. See note above.
 373  *
 374  * Output data from the DRM_VMW_ALLOC_DMABUF Ioctl.
 375  */
 376
 377 struct drm_vmw_dmabuf_rep {
 378         uint64_t map_handle;
 379         uint32_t handle;
 380         uint32_t cur_gmr_id;
 381         uint32_t cur_gmr_offset;
 382         uint32_t pad64;
 383 };
 384
 385 /**
 386  * union drm_vmw_dmabuf_arg
 387  *
 388  * @req: Input data as described above.
 389  * @rep: Output data as described above.
 390  *
 391  * Argument to the DRM_VMW_ALLOC_DMABUF Ioctl.
 392  */
 393
 394 union drm_vmw_alloc_dmabuf_arg {
 395         struct drm_vmw_alloc_dmabuf_req req;
 396         struct drm_vmw_dmabuf_rep rep;
 397 };
 398
 399 /*************************************************************************/
 400 /**
 401  * DRM_VMW_UNREF_DMABUF - Free a DMA buffer.
 402  *
 403  */
 404
 405 /**
 406  * struct drm_vmw_unref_dmabuf_arg
 407  *
 408  * @handle: Handle indicating what buffer to free. Obtained from the
 409  * DRM_VMW_ALLOC_DMABUF Ioctl.
 410  *
 411  * Argument to the DRM_VMW_UNREF_DMABUF Ioctl.
 412  */
 413
 414 struct drm_vmw_unref_dmabuf_arg {
 415         uint32_t handle;
 416         uint32_t pad64;
 417 };
 418
 419 /*************************************************************************/
 420 /**
 421  * DRM_VMW_CONTROL_STREAM - Control overlays, aka streams.
 422  *
 423  * This IOCTL controls the overlay units of the svga device.
 424  * The SVGA overlay units does not work like regular hardware units in
 425  * that they do not automaticaly read back the contents of the given dma
 426  * buffer. But instead only read back for each call to this ioctl, and
 427  * at any point between this call being made and a following call that
 428  * either changes the buffer or disables the stream.
 429  */
 430
 431 /**
 432  * struct drm_vmw_rect
 433  *
 434  * Defines a rectangle. Used in the overlay ioctl to define
 435  * source and destination rectangle.
 436  */
 437
 438 struct drm_vmw_rect {
 439         int32_t x;
 440         int32_t y;
 441         uint32_t w;
 442         uint32_t h;
 443 };
 444
 445 /**
 446  * struct drm_vmw_control_stream_arg
 447  *
 448  * @stream_id: Stearm to control
 449  * @enabled: If false all following arguments are ignored.
 450  * @handle: Handle to buffer for getting data from.
 451  * @format: Format of the overlay as understood by the host.
 452  * @width: Width of the overlay.
 453  * @height: Height of the overlay.
 454  * @size: Size of the overlay in bytes.
 455  * @pitch: Array of pitches, the two last are only used for YUV12 formats.
 456  * @offset: Offset from start of dma buffer to overlay.
 457  * @src: Source rect, must be within the defined area above.
 458  * @dst: Destination rect, x and y may be negative.
 459  *
 460  * Argument to the DRM_VMW_CONTROL_STREAM Ioctl.
 461  */
 462
 463 struct drm_vmw_control_stream_arg {
 464         uint32_t stream_id;
 465         uint32_t enabled;
 466
 467         uint32_t flags;
 468         uint32_t color_key;
 469
 470         uint32_t handle;
 471         uint32_t offset;
 472         int32_t format;
 473         uint32_t size;
 474         uint32_t width;
 475         uint32_t height;
 476         uint32_t pitch[3];
 477
 478         uint32_t pad64;
 479         struct drm_vmw_rect src;
 480         struct drm_vmw_rect dst;
 481 };
 482
 483 /*************************************************************************/
 484 /**
 485  * DRM_VMW_CURSOR_BYPASS - Give extra information about cursor bypass.
 486  *
 487  */
 488
 489 #define DRM_VMW_CURSOR_BYPASS_ALL    (1 << 0)
 490 #define DRM_VMW_CURSOR_BYPASS_FLAGS       (1)
 491
 492 /**
 493  * struct drm_vmw_cursor_bypass_arg
 494  *
 495  * @flags: Flags.
 496  * @crtc_id: Crtc id, only used if DMR_CURSOR_BYPASS_ALL isn't passed.
 497  * @xpos: X position of cursor.
 498  * @ypos: Y position of cursor.
 499  * @xhot: X hotspot.
 500  * @yhot: Y hotspot.
 501  *
 502  * Argument to the DRM_VMW_CURSOR_BYPASS Ioctl.
 503  */
 504
 505 struct drm_vmw_cursor_bypass_arg {
 506         uint32_t flags;
 507         uint32_t crtc_id;
 508         int32_t xpos;
 509         int32_t ypos;
 510         int32_t xhot;
 511         int32_t yhot;
 512 };
 513
 514 /*************************************************************************/
 515 /**
 516  * DRM_VMW_CLAIM_STREAM - Claim a single stream.
 517  */
 518
 519 /**
 520  * struct drm_vmw_context_arg
 521  *
 522  * @stream_id: Device unique context ID.
 523  *
 524  * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl.
 525  * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl.
 526  */
 527
 528 struct drm_vmw_stream_arg {
 529         uint32_t stream_id;
 530         uint32_t pad64;
 531 };
 532
 533 /*************************************************************************/
 534 /**
 535  * DRM_VMW_UNREF_STREAM - Unclaim a stream.
 536  *
 537  * Return a single stream that was claimed by this process. Also makes
 538  * sure that the stream has been stopped.
 539  */
 540
 541 /*************************************************************************/
 542 /**
 543  * DRM_VMW_GET_3D_CAP
 544  *
 545  * Read 3D capabilities from the FIFO
 546  *
 547  */
 548
 549 /**
 550  * struct drm_vmw_get_3d_cap_arg
 551  *
 552  * @buffer: Pointer to a buffer for capability data, cast to an uint64_t
 553  * @size: Max size to copy
 554  *
 555  * Input argument to the DRM_VMW_GET_3D_CAP_IOCTL
 556  * ioctls.
 557  */
 558
 559 struct drm_vmw_get_3d_cap_arg {
 560         uint64_t buffer;
 561         uint32_t max_size;
 562         uint32_t pad64;
 563 };
 564
 565
 566 /*************************************************************************/
 567 /**
 568  * DRM_VMW_FENCE_WAIT
 569  *
 570  * Waits for a fence object to signal. The wait is interruptible, so that
 571  * signals may be delivered during the interrupt. The wait may timeout,
 572  * in which case the calls returns -EBUSY. If the wait is restarted,
 573  * that is restarting without resetting @cookie_valid to zero,
 574  * the timeout is computed from the first call.
 575  *
 576  * The flags argument to the DRM_VMW_FENCE_WAIT ioctl indicates what to wait
 577  * on:
 578  * DRM_VMW_FENCE_FLAG_EXEC: All commands ahead of the fence in the command
 579  * stream
 580  * have executed.
 581  * DRM_VMW_FENCE_FLAG_QUERY: All query results resulting from query finish
 582  * commands
 583  * in the buffer given to the EXECBUF ioctl returning the fence object handle
 584  * are available to user-space.
 585  *
 586  * DRM_VMW_WAIT_OPTION_UNREF: If this wait option is given, and the
 587  * fenc wait ioctl returns 0, the fence object has been unreferenced after
 588  * the wait.
 589  */
 590
 591 #define DRM_VMW_FENCE_FLAG_EXEC   (1 << 0)
 592 #define DRM_VMW_FENCE_FLAG_QUERY  (1 << 1)
 593
 594 #define DRM_VMW_WAIT_OPTION_UNREF (1 << 0)
 595
 596 /**
 597  * struct drm_vmw_fence_wait_arg
 598  *
 599  * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl.
 600  * @cookie_valid: Must be reset to 0 on first call. Left alone on restart.
 601  * @kernel_cookie: Set to 0 on first call. Left alone on restart.
 602  * @timeout_us: Wait timeout in microseconds. 0 for indefinite timeout.
 603  * @lazy: Set to 1 if timing is not critical. Allow more than a kernel tick
 604  * before returning.
 605  * @flags: Fence flags to wait on.
 606  * @wait_options: Options that control the behaviour of the wait ioctl.
 607  *
 608  * Input argument to the DRM_VMW_FENCE_WAIT ioctl.
 609  */
 610
 611 struct drm_vmw_fence_wait_arg {
 612         uint32_t handle;
 613         int32_t  cookie_valid;
 614         uint64_t kernel_cookie;
 615         uint64_t timeout_us;
 616         int32_t lazy;
 617         int32_t flags;
 618         int32_t wait_options;
 619         int32_t pad64;
 620 };
 621
 622 /*************************************************************************/
 623 /**
 624  * DRM_VMW_FENCE_SIGNALED
 625  *
 626  * Checks if a fence object is signaled..
 627  */
 628
 629 /**
 630  * struct drm_vmw_fence_signaled_arg
 631  *
 632  * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl.
 633  * @flags: Fence object flags input to DRM_VMW_FENCE_SIGNALED ioctl
 634  * @signaled: Out: Flags signaled.
 635  * @sequence: Out: Highest sequence passed so far. Can be used to signal the
 636  * EXEC flag of user-space fence objects.
 637  *
 638  * Input/Output argument to the DRM_VMW_FENCE_SIGNALED and DRM_VMW_FENCE_UNREF
 639  * ioctls.
 640  */
 641
 642 struct drm_vmw_fence_signaled_arg {
 643          uint32_t handle;
 644          uint32_t flags;
 645          int32_t signaled;
 646          uint32_t passed_seqno;
 647          uint32_t signaled_flags;
 648          uint32_t pad64;
 649 };
 650
 651 /*************************************************************************/
 652 /**
 653  * DRM_VMW_FENCE_UNREF
 654  *
 655  * Unreferences a fence object, and causes it to be destroyed if there are no
 656  * other references to it.
 657  *
 658  */
 659
 660 /**
 661  * struct drm_vmw_fence_arg
 662  *
 663  * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl.
 664  *
 665  * Input/Output argument to the DRM_VMW_FENCE_UNREF ioctl..
 666  */
 667
 668 struct drm_vmw_fence_arg {
 669          uint32_t handle;
 670          uint32_t pad64;
 671 };
 672
 673
 674 /*************************************************************************/
 675 /**
 676  * DRM_VMW_FENCE_EVENT
 677  *
 678  * Queues an event on a fence to be delivered on the drm character device
 679  * when the fence has signaled the DRM_VMW_FENCE_FLAG_EXEC flag.
 680  * Optionally the approximate time when the fence signaled is
 681  * given by the event.
 682  */
 683
 684 /*
 685  * The event type
 686  */
 687 #define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000
 688
 689 struct drm_vmw_event_fence {
 690         struct drm_event base;
 691         uint64_t user_data;
 692         uint32_t tv_sec;
 693         uint32_t tv_usec;
 694 };
 695
 696 /*
 697  * Flags that may be given to the command.
 698  */
 699 /* Request fence signaled time on the event. */
 700 #define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0)
 701
 702 /**
 703  * struct drm_vmw_fence_event_arg
 704  *
 705  * @fence_rep: Pointer to fence_rep structure cast to uint64_t or 0 if
 706  * the fence is not supposed to be referenced by user-space.
 707  * @user_info: Info to be delivered with the event.
 708  * @handle: Attach the event to this fence only.
 709  * @flags: A set of flags as defined above.
 710  */
 711 struct drm_vmw_fence_event_arg {
 712         uint64_t fence_rep;
 713         uint64_t user_data;
 714         uint32_t handle;
 715         uint32_t flags;
 716 };
 717
 718
 719 /*************************************************************************/
 720 /**
 721  * DRM_VMW_PRESENT
 722  *
 723  * Executes an SVGA present on a given fb for a given surface. The surface
 724  * is placed on the framebuffer. Cliprects are given relative to the given
 725  * point (the point disignated by dest_{x|y}).
 726  *
 727  */
 728
 729 /**
 730  * struct drm_vmw_present_arg
 731  * @fb_id: framebuffer id to present / read back from.
 732  * @sid: Surface id to present from.
 733  * @dest_x: X placement coordinate for surface.
 734  * @dest_y: Y placement coordinate for surface.
 735  * @clips_ptr: Pointer to an array of clip rects cast to an uint64_t.
 736  * @num_clips: Number of cliprects given relative to the framebuffer origin,
 737  * in the same coordinate space as the frame buffer.
 738  * @pad64: Unused 64-bit padding.
 739  *
 740  * Input argument to the DRM_VMW_PRESENT ioctl.
 741  */
 742
 743 struct drm_vmw_present_arg {
 744         uint32_t fb_id;
 745         uint32_t sid;
 746         int32_t dest_x;
 747         int32_t dest_y;
 748         uint64_t clips_ptr;
 749         uint32_t num_clips;
 750         uint32_t pad64;
 751 };
 752
 753
 754 /*************************************************************************/
 755 /**
 756  * DRM_VMW_PRESENT_READBACK
 757  *
 758  * Executes an SVGA present readback from a given fb to the dma buffer
 759  * currently bound as the fb. If there is no dma buffer bound to the fb,
 760  * an error will be returned.
 761  *
 762  */
 763
 764 /**
 765  * struct drm_vmw_present_arg
 766  * @fb_id: fb_id to present / read back from.
 767  * @num_clips: Number of cliprects.
 768  * @clips_ptr: Pointer to an array of clip rects cast to an uint64_t.
 769  * @fence_rep: Pointer to a struct drm_vmw_fence_rep, cast to an uint64_t.
 770  * If this member is NULL, then the ioctl should not return a fence.
 771  */
 772
 773 struct drm_vmw_present_readback_arg {
 774          uint32_t fb_id;
 775          uint32_t num_clips;
 776          uint64_t clips_ptr;
 777          uint64_t fence_rep;
 778 };
 779
 780 /*************************************************************************/
 781 /**
 782  * DRM_VMW_UPDATE_LAYOUT - Update layout
 783  *
 784  * Updates the preferred modes and connection status for connectors. The
 785  * command consists of one drm_vmw_update_layout_arg pointing to an array
 786  * of num_outputs drm_vmw_rect's.
 787  */
 788
 789 /**
 790  * struct drm_vmw_update_layout_arg
 791  *
 792  * @num_outputs: number of active connectors
 793  * @rects: pointer to array of drm_vmw_rect cast to an uint64_t
 794  *
 795  * Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl.
 796  */
 797 struct drm_vmw_update_layout_arg {
 798         uint32_t num_outputs;
 799         uint32_t pad64;
 800         uint64_t rects;
 801 };
 802
 803
 804 /*************************************************************************/
 805 /**
 806  * DRM_VMW_CREATE_SHADER - Create shader
 807  *
 808  * Creates a shader and optionally binds it to a dma buffer containing
 809  * the shader byte-code.
 810  */
 811
 812 /**
 813  * enum drm_vmw_shader_type - Shader types
 814  */
 815 enum drm_vmw_shader_type {
 816         drm_vmw_shader_type_vs = 0,
 817         drm_vmw_shader_type_ps,
 818         drm_vmw_shader_type_gs
 819 };
 820
 821
 822 /**
 823  * struct drm_vmw_shader_create_arg
 824  *
 825  * @shader_type: Shader type of the shader to create.
 826  * @size: Size of the byte-code in bytes.
 827  * where the shader byte-code starts
 828  * @buffer_handle: Buffer handle identifying the buffer containing the
 829  * shader byte-code
 830  * @shader_handle: On successful completion contains a handle that
 831  * can be used to subsequently identify the shader.
 832  * @offset: Offset in bytes into the buffer given by @buffer_handle,
 833  *
 834  * Input / Output argument to the DRM_VMW_CREATE_SHADER Ioctl.
 835  */
 836 struct drm_vmw_shader_create_arg {
 837         enum drm_vmw_shader_type shader_type;
 838         uint32_t size;
 839         uint32_t buffer_handle;
 840         uint32_t shader_handle;
 841         uint64_t offset;
 842 };
 843
 844 /*************************************************************************/
 845 /**
 846  * DRM_VMW_UNREF_SHADER - Unreferences a shader
 847  *
 848  * Destroys a user-space reference to a shader, optionally destroying
 849  * it.
 850  */
 851
 852 /**
 853  * struct drm_vmw_shader_arg
 854  *
 855  * @handle: Handle identifying the shader to destroy.
 856  *
 857  * Input argument to the DRM_VMW_UNREF_SHADER ioctl.
 858  */
 859 struct drm_vmw_shader_arg {
 860         uint32_t handle;
 861         uint32_t pad64;
 862 };
 863
 864 /*************************************************************************/
 865 /**
 866  * DRM_VMW_GB_SURFACE_CREATE - Create a host guest-backed surface.
 867  *
 868  * Allocates a surface handle and queues a create surface command
 869  * for the host on the first use of the surface. The surface ID can
 870  * be used as the surface ID in commands referencing the surface.
 871  */
 872
 873 /**
 874  * enum drm_vmw_surface_flags
 875  *
 876  * @drm_vmw_surface_flag_shareable:     Whether the surface is shareable
 877  * @drm_vmw_surface_flag_scanout:       Whether the surface is a scanout
 878  *                                      surface.
 879  * @drm_vmw_surface_flag_create_buffer: Create a backup buffer if none is
 880  *                                      given.
 881  */
 882 enum drm_vmw_surface_flags {
 883         drm_vmw_surface_flag_shareable = (1 << 0),
 884         drm_vmw_surface_flag_scanout = (1 << 1),
 885         drm_vmw_surface_flag_create_buffer = (1 << 2)
 886 };
 887
 888 /**
 889  * struct drm_vmw_gb_surface_create_req
 890  *
 891  * @svga3d_flags:     SVGA3d surface flags for the device.
 892  * @format:           SVGA3d format.
 893  * @mip_level:        Number of mip levels for all faces.
 894  * @drm_surface_flags Flags as described above.
 895  * @multisample_count Future use. Set to 0.
 896  * @autogen_filter    Future use. Set to 0.
 897  * @buffer_handle     Buffer handle of backup buffer. SVGA3D_INVALID_ID
 898  *                    if none.
 899  * @base_size         Size of the base mip level for all faces.
 900  *
 901  * Input argument to the  DRM_VMW_GB_SURFACE_CREATE Ioctl.
 902  * Part of output argument for the DRM_VMW_GB_SURFACE_REF Ioctl.
 903  */
 904 struct drm_vmw_gb_surface_create_req {
 905         uint32_t svga3d_flags;
 906         uint32_t format;
 907         uint32_t mip_levels;
 908         enum drm_vmw_surface_flags drm_surface_flags;
 909         uint32_t multisample_count;
 910         uint32_t autogen_filter;
 911         uint32_t buffer_handle;
 912         uint32_t pad64;
 913         struct drm_vmw_size base_size;
 914 };
 915
 916 /**
 917  * struct drm_vmw_gb_surface_create_rep
 918  *
 919  * @handle:            Surface handle.
 920  * @backup_size:       Size of backup buffers for this surface.
 921  * @buffer_handle:     Handle of backup buffer. SVGA3D_INVALID_ID if none.
 922  * @buffer_size:       Actual size of the buffer identified by
 923  *                     @buffer_handle
 924  * @buffer_map_handle: Offset into device address space for the buffer
 925  *                     identified by @buffer_handle.
 926  *
 927  * Part of output argument for the DRM_VMW_GB_SURFACE_REF ioctl.
 928  * Output argument for the DRM_VMW_GB_SURFACE_CREATE ioctl.
 929  */
 930 struct drm_vmw_gb_surface_create_rep {
 931         uint32_t handle;
 932         uint32_t backup_size;
 933         uint32_t buffer_handle;
 934         uint32_t buffer_size;
 935         uint64_t buffer_map_handle;
 936 };
 937
 938 /**
 939  * union drm_vmw_gb_surface_create_arg
 940  *
 941  * @req: Input argument as described above.
 942  * @rep: Output argument as described above.
 943  *
 944  * Argument to the DRM_VMW_GB_SURFACE_CREATE ioctl.
 945  */
 946 union drm_vmw_gb_surface_create_arg {
 947         struct drm_vmw_gb_surface_create_rep rep;
 948         struct drm_vmw_gb_surface_create_req req;
 949 };
 950
 951 /*************************************************************************/
 952 /**
 953  * DRM_VMW_GB_SURFACE_REF - Reference a host surface.
 954  *
 955  * Puts a reference on a host surface with a given handle, as previously
 956  * returned by the DRM_VMW_GB_SURFACE_CREATE ioctl.
 957  * A reference will make sure the surface isn't destroyed while we hold
 958  * it and will allow the calling client to use the surface handle in
 959  * the command stream.
 960  *
 961  * On successful return, the Ioctl returns the surface information given
 962  * to and returned from the DRM_VMW_GB_SURFACE_CREATE ioctl.
 963  */
 964
 965 /**
 966  * struct drm_vmw_gb_surface_reference_arg
 967  *
 968  * @creq: The data used as input when the surface was created, as described
 969  *        above at "struct drm_vmw_gb_surface_create_req"
 970  * @crep: Additional data output when the surface was created, as described
 971  *        above at "struct drm_vmw_gb_surface_create_rep"
 972  *
 973  * Output Argument to the DRM_VMW_GB_SURFACE_REF ioctl.
 974  */
 975 struct drm_vmw_gb_surface_ref_rep {
 976         struct drm_vmw_gb_surface_create_req creq;
 977         struct drm_vmw_gb_surface_create_rep crep;
 978 };
 979
 980 /**
 981  * union drm_vmw_gb_surface_reference_arg
 982  *
 983  * @req: Input data as described above at "struct drm_vmw_surface_arg"
 984  * @rep: Output data as described above at "struct drm_vmw_gb_surface_ref_rep"
 985  *
 986  * Argument to the DRM_VMW_GB_SURFACE_REF Ioctl.
 987  */
 988 union drm_vmw_gb_surface_reference_arg {
 989         struct drm_vmw_gb_surface_ref_rep rep;
 990         struct drm_vmw_surface_arg req;
 991 };
 992
 993
 994 /*************************************************************************/
 995 /**
 996  * DRM_VMW_SYNCCPU - Sync a DMA buffer / MOB for CPU access.
 997  *
 998  * Idles any previously submitted GPU operations on the buffer and
 999  * by default blocks command submissions that reference the buffer.
1000  * If the file descriptor used to grab a blocking CPU sync is closed, the
1001  * cpu sync is released.
1002  * The flags argument indicates how the grab / release operation should be
1003  * performed:
1004  */
1005
1006 /**
1007  * enum drm_vmw_synccpu_flags - Synccpu flags:
1008  *
1009  * @drm_vmw_synccpu_read: Sync for read. If sync is done for read only, it's a
1010  * hint to the kernel to allow command submissions that references the buffer
1011  * for read-only.
1012  * @drm_vmw_synccpu_write: Sync for write. Block all command submissions
1013  * referencing this buffer.
1014  * @drm_vmw_synccpu_dontblock: Dont wait for GPU idle, but rather return
1015  * -EBUSY should the buffer be busy.
1016  * @drm_vmw_synccpu_allow_cs: Allow command submission that touches the buffer
1017  * while the buffer is synced for CPU. This is similar to the GEM bo idle
1018  * behavior.
1019  */
1020 enum drm_vmw_synccpu_flags {
1021         drm_vmw_synccpu_read = (1 << 0),
1022         drm_vmw_synccpu_write = (1 << 1),
1023         drm_vmw_synccpu_dontblock = (1 << 2),
1024         drm_vmw_synccpu_allow_cs = (1 << 3)
1025 };
1026
1027 /**
1028  * enum drm_vmw_synccpu_op - Synccpu operations:
1029  *
1030  * @drm_vmw_synccpu_grab:    Grab the buffer for CPU operations
1031  * @drm_vmw_synccpu_release: Release a previous grab.
1032  */
1033 enum drm_vmw_synccpu_op {
1034         drm_vmw_synccpu_grab,
1035         drm_vmw_synccpu_release
1036 };
1037
1038 /**
1039  * struct drm_vmw_synccpu_arg
1040  *
1041  * @op:                      The synccpu operation as described above.
1042  * @handle:                  Handle identifying the buffer object.
1043  * @flags:                   Flags as described above.
1044  */
1045 struct drm_vmw_synccpu_arg {
1046         enum drm_vmw_synccpu_op op;
1047         enum drm_vmw_synccpu_flags flags;
1048         uint32_t handle;
1049         uint32_t pad64;
1050 };
1051
1052 #endif