src/gallium/winsys/virgl/drm/virtgpu_drm.h

   1 /*
   2  * Copyright 2013 Red Hat
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 #ifndef VIRTGPU_DRM_H
  25 #define VIRTGPU_DRM_H
  26
  27 #include <stddef.h>
  28 #include "drm.h"
  29
  30 /* Please note that modifications to all structs defined here are
  31  * subject to backwards-compatibility constraints.
  32  *
  33  * Do not use pointers, use uint64_t instead for 32 bit / 64 bit user/kernel
  34  * compatibility Keep fields aligned to their size
  35  */
  36
  37 #define DRM_VIRTGPU_MAP         0x01
  38 #define DRM_VIRTGPU_EXECBUFFER  0x02
  39 #define DRM_VIRTGPU_GETPARAM    0x03
  40 #define DRM_VIRTGPU_RESOURCE_CREATE 0x04
  41 #define DRM_VIRTGPU_RESOURCE_INFO     0x05
  42 #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
  43 #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
  44 #define DRM_VIRTGPU_WAIT     0x08
  45 #define DRM_VIRTGPU_GET_CAPS  0x09
  46
  47 /*
  48  * virtgpu execbuffer flags
  49  */
  50 #define VIRTGPU_EXECBUF_FENCE_FD_IN     0x01
  51 #define VIRTGPU_EXECBUF_FENCE_FD_OUT    0x02
  52 #define VIRTGPU_EXECBUF_FLAGS   (\
  53                 VIRTGPU_EXECBUF_FENCE_FD_IN |\
  54                 VIRTGPU_EXECBUF_FENCE_FD_OUT |\
  55                 0)
  56
  57 struct drm_virtgpu_map {
  58         uint64_t offset; /* use for mmap system call */
  59         uint32_t handle;
  60         uint32_t pad;
  61 };
  62
  63 struct drm_virtgpu_execbuffer {
  64         uint32_t                flags;          /* for future use */
  65         uint32_t size;
  66         uint64_t command; /* void* */
  67         uint64_t bo_handles;
  68         uint32_t num_bo_handles;
  69         int32_t fence_fd;
  70 };
  71
  72 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
  73 #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2
  74
  75 struct drm_virtgpu_getparam {
  76         uint64_t param;
  77         uint64_t value;
  78 };
  79
  80 /* NO_BO flags? NO resource flag? */
  81 /* resource flag for y_0_top */
  82 struct drm_virtgpu_resource_create {
  83         uint32_t target;
  84         uint32_t format;
  85         uint32_t bind;
  86         uint32_t width;
  87         uint32_t height;
  88         uint32_t depth;
  89         uint32_t array_size;
  90         uint32_t last_level;
  91         uint32_t nr_samples;
  92         uint32_t flags;
  93         uint32_t bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
  94         uint32_t res_handle;  /* returned by kernel */
  95         uint32_t size;        /* validate transfer in the host */
  96         uint32_t stride;      /* validate transfer in the host */
  97 };
  98
  99 struct drm_virtgpu_resource_info {
 100         uint32_t bo_handle;
 101         uint32_t res_handle;
 102         uint32_t size;
 103         uint32_t stride;
 104 };
 105
 106 struct drm_virtgpu_3d_box {
 107         uint32_t x, y, z;
 108         uint32_t w, h, d;
 109 };
 110
 111 struct drm_virtgpu_3d_transfer_to_host {
 112         uint32_t bo_handle;
 113         struct drm_virtgpu_3d_box box;
 114         uint32_t level;
 115         uint32_t offset;
 116 };
 117
 118 struct drm_virtgpu_3d_transfer_from_host {
 119         uint32_t bo_handle;
 120         struct drm_virtgpu_3d_box box;
 121         uint32_t level;
 122         uint32_t offset;
 123 };
 124
 125 #define VIRTGPU_WAIT_NOWAIT 1 /* like it */
 126 struct drm_virtgpu_3d_wait {
 127         uint32_t handle; /* 0 is an invalid handle */
 128         uint32_t flags;
 129 };
 130
 131 struct drm_virtgpu_get_caps {
 132         uint32_t cap_set_id;
 133         uint32_t cap_set_ver;
 134         uint64_t addr;
 135         uint32_t size;
 136         uint32_t pad;
 137 };
 138
 139 #define DRM_IOCTL_VIRTGPU_MAP \
 140         DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
 141
 142 #define DRM_IOCTL_VIRTGPU_EXECBUFFER \
 143         DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
 144                 struct drm_virtgpu_execbuffer)
 145
 146 #define DRM_IOCTL_VIRTGPU_GETPARAM \
 147         DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
 148                 struct drm_virtgpu_getparam)
 149
 150 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE                       \
 151         DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE,        \
 152                 struct drm_virtgpu_resource_create)
 153
 154 #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \
 155         DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \
 156                  struct drm_virtgpu_resource_info)
 157
 158 #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \
 159         DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST,     \
 160                 struct drm_virtgpu_3d_transfer_from_host)
 161
 162 #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \
 163         DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST,       \
 164                 struct drm_virtgpu_3d_transfer_to_host)
 165
 166 #define DRM_IOCTL_VIRTGPU_WAIT                          \
 167         DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT,   \
 168                 struct drm_virtgpu_3d_wait)
 169
 170 #define DRM_IOCTL_VIRTGPU_GET_CAPS \
 171         DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
 172         struct drm_virtgpu_get_caps)
 173
 174 #endif