virgl: fix vtest regression since fencing changes.
[mesa.git] / src / gallium / winsys / virgl / vtest / virgl_vtest_winsys.c
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include "util/u_memory.h"
25 #include "util/u_format.h"
26 #include "util/u_inlines.h"
27 #include "util/os_time.h"
28 #include "state_tracker/sw_winsys.h"
29
30 #include "virgl_vtest_winsys.h"
31 #include "virgl_vtest_public.h"
32
33 static void *virgl_vtest_resource_map(struct virgl_winsys *vws,
34 struct virgl_hw_res *res);
35 static void virgl_vtest_resource_unmap(struct virgl_winsys *vws,
36 struct virgl_hw_res *res);
37
38 static inline boolean can_cache_resource(struct virgl_hw_res *res)
39 {
40 return res->cacheable == TRUE;
41 }
42
43 static uint32_t vtest_get_transfer_size(struct virgl_hw_res *res,
44 const struct pipe_box *box,
45 uint32_t stride, uint32_t layer_stride,
46 uint32_t level, uint32_t *valid_stride_p)
47 {
48 uint32_t valid_stride, valid_layer_stride;
49
50 valid_stride = util_format_get_stride(res->format, box->width);
51 if (stride) {
52 if (box->height > 1)
53 valid_stride = stride;
54 }
55
56 valid_layer_stride = util_format_get_2d_size(res->format, valid_stride,
57 box->height);
58 if (layer_stride) {
59 if (box->depth > 1)
60 valid_layer_stride = layer_stride;
61 }
62
63 *valid_stride_p = valid_stride;
64 return valid_layer_stride * box->depth;
65 }
66
67 static int
68 virgl_vtest_transfer_put(struct virgl_winsys *vws,
69 struct virgl_hw_res *res,
70 const struct pipe_box *box,
71 uint32_t stride, uint32_t layer_stride,
72 uint32_t buf_offset, uint32_t level)
73 {
74 struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
75 uint32_t size;
76 void *ptr;
77 uint32_t valid_stride;
78
79 size = vtest_get_transfer_size(res, box, stride, layer_stride, level,
80 &valid_stride);
81
82 /* The size calculated above is the full box size, but if this box origin
83 * is not zero we may have to correct the transfer size to not read past the
84 * end of the resource. The correct adjustment depends on various factors
85 * that are not documented, so instead of going though all the hops to get
86 * the size right up-front, we just make sure we don't read past the end.
87 * FIXME: figure out what it takes to actually get this right.
88 */
89 if (size + buf_offset > res->size)
90 size = res->size - buf_offset;
91
92 virgl_vtest_send_transfer_put(vtws, res->res_handle,
93 level, stride, layer_stride,
94 box, size, buf_offset);
95 ptr = virgl_vtest_resource_map(vws, res);
96 virgl_vtest_send_transfer_put_data(vtws, ptr + buf_offset, size);
97 virgl_vtest_resource_unmap(vws, res);
98 return 0;
99 }
100
101 static int
102 virgl_vtest_transfer_get(struct virgl_winsys *vws,
103 struct virgl_hw_res *res,
104 const struct pipe_box *box,
105 uint32_t stride, uint32_t layer_stride,
106 uint32_t buf_offset, uint32_t level)
107 {
108 struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
109 uint32_t size;
110 void *ptr;
111 uint32_t valid_stride;
112
113 size = vtest_get_transfer_size(res, box, stride, layer_stride, level,
114 &valid_stride);
115 /* Don't ask for more pixels than available (see above) */
116 if (size + buf_offset > res->size)
117 size = res->size - buf_offset;
118
119 virgl_vtest_send_transfer_get(vtws, res->res_handle,
120 level, stride, layer_stride,
121 box, size, buf_offset);
122
123 ptr = virgl_vtest_resource_map(vws, res);
124
125 /* This functions seems to be using a specific transfer resource that
126 * has exactly the box size and hence its src stride is equal to the target
127 * stride */
128 virgl_vtest_recv_transfer_get_data(vtws, ptr + buf_offset, size,
129 valid_stride, box, res->format, valid_stride);
130
131 virgl_vtest_resource_unmap(vws, res);
132 return 0;
133 }
134
135 static void virgl_hw_res_destroy(struct virgl_vtest_winsys *vtws,
136 struct virgl_hw_res *res)
137 {
138 virgl_vtest_send_resource_unref(vtws, res->res_handle);
139 if (res->dt)
140 vtws->sws->displaytarget_destroy(vtws->sws, res->dt);
141 free(res->ptr);
142 FREE(res);
143 }
144
145 static boolean virgl_vtest_resource_is_busy(struct virgl_vtest_winsys *vtws,
146 struct virgl_hw_res *res)
147 {
148 /* implement busy check */
149 int ret;
150 ret = virgl_vtest_busy_wait(vtws, res->res_handle, 0);
151
152 if (ret < 0)
153 return FALSE;
154
155 return ret == 1 ? TRUE : FALSE;
156 }
157
158 static void
159 virgl_cache_flush(struct virgl_vtest_winsys *vtws)
160 {
161 struct list_head *curr, *next;
162 struct virgl_hw_res *res;
163
164 mtx_lock(&vtws->mutex);
165 curr = vtws->delayed.next;
166 next = curr->next;
167
168 while (curr != &vtws->delayed) {
169 res = LIST_ENTRY(struct virgl_hw_res, curr, head);
170 LIST_DEL(&res->head);
171 virgl_hw_res_destroy(vtws, res);
172 curr = next;
173 next = curr->next;
174 }
175 mtx_unlock(&vtws->mutex);
176 }
177
178 static void
179 virgl_cache_list_check_free(struct virgl_vtest_winsys *vtws)
180 {
181 struct list_head *curr, *next;
182 struct virgl_hw_res *res;
183 int64_t now;
184
185 now = os_time_get();
186 curr = vtws->delayed.next;
187 next = curr->next;
188 while (curr != &vtws->delayed) {
189 res = LIST_ENTRY(struct virgl_hw_res, curr, head);
190 if (!os_time_timeout(res->start, res->end, now))
191 break;
192
193 LIST_DEL(&res->head);
194 virgl_hw_res_destroy(vtws, res);
195 curr = next;
196 next = curr->next;
197 }
198 }
199
200 static void virgl_vtest_resource_reference(struct virgl_vtest_winsys *vtws,
201 struct virgl_hw_res **dres,
202 struct virgl_hw_res *sres)
203 {
204 struct virgl_hw_res *old = *dres;
205 if (pipe_reference(&(*dres)->reference, &sres->reference)) {
206 if (!can_cache_resource(old)) {
207 virgl_hw_res_destroy(vtws, old);
208 } else {
209 mtx_lock(&vtws->mutex);
210 virgl_cache_list_check_free(vtws);
211
212 old->start = os_time_get();
213 old->end = old->start + vtws->usecs;
214 LIST_ADDTAIL(&old->head, &vtws->delayed);
215 vtws->num_delayed++;
216 mtx_unlock(&vtws->mutex);
217 }
218 }
219 *dres = sres;
220 }
221
222 static struct virgl_hw_res *
223 virgl_vtest_winsys_resource_create(struct virgl_winsys *vws,
224 enum pipe_texture_target target,
225 uint32_t format,
226 uint32_t bind,
227 uint32_t width,
228 uint32_t height,
229 uint32_t depth,
230 uint32_t array_size,
231 uint32_t last_level,
232 uint32_t nr_samples,
233 uint32_t size)
234 {
235 struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
236 struct virgl_hw_res *res;
237 static int handle = 1;
238
239 res = CALLOC_STRUCT(virgl_hw_res);
240 if (!res)
241 return NULL;
242
243 if (bind & (VIRGL_BIND_DISPLAY_TARGET | VIRGL_BIND_SCANOUT)) {
244 res->dt = vtws->sws->displaytarget_create(vtws->sws, bind, format,
245 width, height, 64, NULL,
246 &res->stride);
247
248 } else {
249 res->ptr = align_malloc(size, 64);
250 if (!res->ptr) {
251 FREE(res);
252 return NULL;
253 }
254 }
255
256 res->bind = bind;
257 res->format = format;
258 res->height = height;
259 res->width = width;
260 res->size = size;
261 virgl_vtest_send_resource_create(vtws, handle, target, format, bind,
262 width, height, depth, array_size,
263 last_level, nr_samples, size);
264
265 res->res_handle = handle++;
266 pipe_reference_init(&res->reference, 1);
267 return res;
268 }
269
270 static void virgl_vtest_winsys_resource_unref(struct virgl_winsys *vws,
271 struct virgl_hw_res *hres)
272 {
273 struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
274 virgl_vtest_resource_reference(vtws, &hres, NULL);
275 }
276
277 static void *virgl_vtest_resource_map(struct virgl_winsys *vws,
278 struct virgl_hw_res *res)
279 {
280 struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
281
282 if (res->dt) {
283 return vtws->sws->displaytarget_map(vtws->sws, res->dt, 0);
284 } else {
285 res->mapped = res->ptr;
286 return res->mapped;
287 }
288 }
289
290 static void virgl_vtest_resource_unmap(struct virgl_winsys *vws,
291 struct virgl_hw_res *res)
292 {
293 struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
294 if (res->mapped)
295 res->mapped = NULL;
296
297 if (res->dt)
298 vtws->sws->displaytarget_unmap(vtws->sws, res->dt);
299 }
300
301 static void virgl_vtest_resource_wait(struct virgl_winsys *vws,
302 struct virgl_hw_res *res)
303 {
304 struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
305
306 virgl_vtest_busy_wait(vtws, res->res_handle, VCMD_BUSY_WAIT_FLAG_WAIT);
307 }
308
309 static inline int virgl_is_res_compat(struct virgl_vtest_winsys *vtws,
310 struct virgl_hw_res *res,
311 uint32_t size, uint32_t bind,
312 uint32_t format)
313 {
314 if (res->bind != bind)
315 return 0;
316 if (res->format != format)
317 return 0;
318 if (res->size < size)
319 return 0;
320 if (res->size > size * 2)
321 return 0;
322
323 if (virgl_vtest_resource_is_busy(vtws, res)) {
324 return -1;
325 }
326
327 return 1;
328 }
329
330 static struct virgl_hw_res *
331 virgl_vtest_winsys_resource_cache_create(struct virgl_winsys *vws,
332 enum pipe_texture_target target,
333 uint32_t format,
334 uint32_t bind,
335 uint32_t width,
336 uint32_t height,
337 uint32_t depth,
338 uint32_t array_size,
339 uint32_t last_level,
340 uint32_t nr_samples,
341 uint32_t size)
342 {
343 struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
344 struct virgl_hw_res *res, *curr_res;
345 struct list_head *curr, *next;
346 int64_t now;
347 int ret;
348
349 /* only store binds for vertex/index/const buffers */
350 if (bind != VIRGL_BIND_CONSTANT_BUFFER && bind != VIRGL_BIND_INDEX_BUFFER &&
351 bind != VIRGL_BIND_VERTEX_BUFFER && bind != VIRGL_BIND_CUSTOM)
352 goto alloc;
353
354 mtx_lock(&vtws->mutex);
355
356 res = NULL;
357 curr = vtws->delayed.next;
358 next = curr->next;
359
360 now = os_time_get();
361 while (curr != &vtws->delayed) {
362 curr_res = LIST_ENTRY(struct virgl_hw_res, curr, head);
363
364 if (!res && ((ret = virgl_is_res_compat(vtws, curr_res, size, bind, format)) > 0))
365 res = curr_res;
366 else if (os_time_timeout(curr_res->start, curr_res->end, now)) {
367 LIST_DEL(&curr_res->head);
368 virgl_hw_res_destroy(vtws, curr_res);
369 } else
370 break;
371
372 if (ret == -1)
373 break;
374
375 curr = next;
376 next = curr->next;
377 }
378
379 if (!res && ret != -1) {
380 while (curr != &vtws->delayed) {
381 curr_res = LIST_ENTRY(struct virgl_hw_res, curr, head);
382 ret = virgl_is_res_compat(vtws, curr_res, size, bind, format);
383 if (ret > 0) {
384 res = curr_res;
385 break;
386 }
387 if (ret == -1)
388 break;
389 curr = next;
390 next = curr->next;
391 }
392 }
393
394 if (res) {
395 LIST_DEL(&res->head);
396 --vtws->num_delayed;
397 mtx_unlock(&vtws->mutex);
398 pipe_reference_init(&res->reference, 1);
399 return res;
400 }
401
402 mtx_unlock(&vtws->mutex);
403
404 alloc:
405 res = virgl_vtest_winsys_resource_create(vws, target, format, bind,
406 width, height, depth, array_size,
407 last_level, nr_samples, size);
408 if (bind == VIRGL_BIND_CONSTANT_BUFFER || bind == VIRGL_BIND_INDEX_BUFFER ||
409 bind == VIRGL_BIND_VERTEX_BUFFER)
410 res->cacheable = TRUE;
411 return res;
412 }
413
414 static struct virgl_cmd_buf *virgl_vtest_cmd_buf_create(struct virgl_winsys *vws)
415 {
416 struct virgl_vtest_cmd_buf *cbuf;
417
418 cbuf = CALLOC_STRUCT(virgl_vtest_cmd_buf);
419 if (!cbuf)
420 return NULL;
421
422 cbuf->nres = 512;
423 cbuf->res_bo = CALLOC(cbuf->nres, sizeof(struct virgl_hw_buf*));
424 if (!cbuf->res_bo) {
425 FREE(cbuf);
426 return NULL;
427 }
428 cbuf->ws = vws;
429 cbuf->base.buf = cbuf->buf;
430 cbuf->base.in_fence_fd = -1;
431 return &cbuf->base;
432 }
433
434 static void virgl_vtest_cmd_buf_destroy(struct virgl_cmd_buf *_cbuf)
435 {
436 struct virgl_vtest_cmd_buf *cbuf = virgl_vtest_cmd_buf(_cbuf);
437
438 FREE(cbuf->res_bo);
439 FREE(cbuf);
440 }
441
442 static boolean virgl_vtest_lookup_res(struct virgl_vtest_cmd_buf *cbuf,
443 struct virgl_hw_res *res)
444 {
445 unsigned hash = res->res_handle & (sizeof(cbuf->is_handle_added)-1);
446 int i;
447
448 if (cbuf->is_handle_added[hash]) {
449 i = cbuf->reloc_indices_hashlist[hash];
450 if (cbuf->res_bo[i] == res)
451 return true;
452
453 for (i = 0; i < cbuf->cres; i++) {
454 if (cbuf->res_bo[i] == res) {
455 cbuf->reloc_indices_hashlist[hash] = i;
456 return true;
457 }
458 }
459 }
460 return false;
461 }
462
463 static void virgl_vtest_release_all_res(struct virgl_vtest_winsys *vtws,
464 struct virgl_vtest_cmd_buf *cbuf)
465 {
466 int i;
467
468 for (i = 0; i < cbuf->cres; i++) {
469 p_atomic_dec(&cbuf->res_bo[i]->num_cs_references);
470 virgl_vtest_resource_reference(vtws, &cbuf->res_bo[i], NULL);
471 }
472 cbuf->cres = 0;
473 }
474
475 static void virgl_vtest_add_res(struct virgl_vtest_winsys *vtws,
476 struct virgl_vtest_cmd_buf *cbuf,
477 struct virgl_hw_res *res)
478 {
479 unsigned hash = res->res_handle & (sizeof(cbuf->is_handle_added)-1);
480
481 if (cbuf->cres >= cbuf->nres) {
482 unsigned new_nres = cbuf->nres + 256;
483 struct virgl_hw_res **new_re_bo = REALLOC(cbuf->res_bo,
484 cbuf->nres * sizeof(struct virgl_hw_buf*),
485 new_nres * sizeof(struct virgl_hw_buf*));
486 if (!new_re_bo) {
487 fprintf(stderr,"failure to add relocation %d, %d\n", cbuf->cres, cbuf->nres);
488 return;
489 }
490
491 cbuf->res_bo = new_re_bo;
492 cbuf->nres = new_nres;
493 }
494
495 cbuf->res_bo[cbuf->cres] = NULL;
496 virgl_vtest_resource_reference(vtws, &cbuf->res_bo[cbuf->cres], res);
497 cbuf->is_handle_added[hash] = TRUE;
498
499 cbuf->reloc_indices_hashlist[hash] = cbuf->cres;
500 p_atomic_inc(&res->num_cs_references);
501 cbuf->cres++;
502 }
503
504 static int virgl_vtest_winsys_submit_cmd(struct virgl_winsys *vws,
505 struct virgl_cmd_buf *_cbuf,
506 int in_fence_fd, int *out_fence_fd)
507 {
508 struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
509 struct virgl_vtest_cmd_buf *cbuf = virgl_vtest_cmd_buf(_cbuf);
510 int ret;
511
512 if (cbuf->base.cdw == 0)
513 return 0;
514
515 assert(in_fence_fd == -1);
516 assert(out_fence_fd == NULL);
517
518 ret = virgl_vtest_submit_cmd(vtws, cbuf);
519
520 virgl_vtest_release_all_res(vtws, cbuf);
521 memset(cbuf->is_handle_added, 0, sizeof(cbuf->is_handle_added));
522 cbuf->base.cdw = 0;
523 return ret;
524 }
525
526 static void virgl_vtest_emit_res(struct virgl_winsys *vws,
527 struct virgl_cmd_buf *_cbuf,
528 struct virgl_hw_res *res, boolean write_buf)
529 {
530 struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
531 struct virgl_vtest_cmd_buf *cbuf = virgl_vtest_cmd_buf(_cbuf);
532 boolean already_in_list = virgl_vtest_lookup_res(cbuf, res);
533
534 if (write_buf)
535 cbuf->base.buf[cbuf->base.cdw++] = res->res_handle;
536 if (!already_in_list)
537 virgl_vtest_add_res(vtws, cbuf, res);
538 }
539
540 static boolean virgl_vtest_res_is_ref(struct virgl_winsys *vws,
541 struct virgl_cmd_buf *_cbuf,
542 struct virgl_hw_res *res)
543 {
544 if (!res->num_cs_references)
545 return FALSE;
546
547 return TRUE;
548 }
549
550 static int virgl_vtest_get_caps(struct virgl_winsys *vws,
551 struct virgl_drm_caps *caps)
552 {
553 struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
554
555 virgl_ws_fill_new_caps_defaults(caps);
556 return virgl_vtest_send_get_caps(vtws, caps);
557 }
558
559 static struct pipe_fence_handle *
560 virgl_cs_create_fence(struct virgl_winsys *vws, int fd)
561 {
562 struct virgl_hw_res *res;
563
564 res = virgl_vtest_winsys_resource_cache_create(vws,
565 PIPE_BUFFER,
566 PIPE_FORMAT_R8_UNORM,
567 VIRGL_BIND_CUSTOM,
568 8, 1, 1, 0, 0, 0, 8);
569
570 return (struct pipe_fence_handle *)res;
571 }
572
573 static bool virgl_fence_wait(struct virgl_winsys *vws,
574 struct pipe_fence_handle *fence,
575 uint64_t timeout)
576 {
577 struct virgl_vtest_winsys *vdws = virgl_vtest_winsys(vws);
578 struct virgl_hw_res *res = virgl_hw_res(fence);
579
580 if (timeout == 0)
581 return !virgl_vtest_resource_is_busy(vdws, res);
582
583 if (timeout != PIPE_TIMEOUT_INFINITE) {
584 int64_t start_time = os_time_get();
585 timeout /= 1000;
586 while (virgl_vtest_resource_is_busy(vdws, res)) {
587 if (os_time_get() - start_time >= timeout)
588 return FALSE;
589 os_time_sleep(10);
590 }
591 return TRUE;
592 }
593 virgl_vtest_resource_wait(vws, res);
594 return TRUE;
595 }
596
597 static void virgl_fence_reference(struct virgl_winsys *vws,
598 struct pipe_fence_handle **dst,
599 struct pipe_fence_handle *src)
600 {
601 struct virgl_vtest_winsys *vdws = virgl_vtest_winsys(vws);
602 virgl_vtest_resource_reference(vdws, (struct virgl_hw_res **)dst,
603 virgl_hw_res(src));
604 }
605
606 static void virgl_vtest_flush_frontbuffer(struct virgl_winsys *vws,
607 struct virgl_hw_res *res,
608 unsigned level, unsigned layer,
609 void *winsys_drawable_handle,
610 struct pipe_box *sub_box)
611 {
612 struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
613 struct pipe_box box;
614 void *map;
615 uint32_t size;
616 uint32_t offset = 0, valid_stride;
617 if (!res->dt)
618 return;
619
620 memset(&box, 0, sizeof(box));
621
622 if (sub_box) {
623 box = *sub_box;
624 offset = box.y / util_format_get_blockheight(res->format) * res->stride +
625 box.x / util_format_get_blockwidth(res->format) * util_format_get_blocksize(res->format);
626 } else {
627 box.z = layer;
628 box.width = res->width;
629 box.height = res->height;
630 box.depth = 1;
631 }
632
633 size = vtest_get_transfer_size(res, &box, res->stride, 0, level, &valid_stride);
634
635 virgl_vtest_busy_wait(vtws, res->res_handle, VCMD_BUSY_WAIT_FLAG_WAIT);
636 map = vtws->sws->displaytarget_map(vtws->sws, res->dt, 0);
637
638 /* execute a transfer */
639 virgl_vtest_send_transfer_get(vtws, res->res_handle,
640 level, res->stride, 0, &box, size, offset);
641
642 /* This functions gets the resource from the hardware backend that may have
643 * a hardware imposed stride that is different from the IOV stride used to
644 * get the data. */
645 virgl_vtest_recv_transfer_get_data(vtws, map + offset, size, valid_stride,
646 &box, res->format,
647 util_format_get_stride(res->format, res->width));
648
649 vtws->sws->displaytarget_unmap(vtws->sws, res->dt);
650
651 vtws->sws->displaytarget_display(vtws->sws, res->dt, winsys_drawable_handle,
652 sub_box);
653 }
654
655 static void
656 virgl_vtest_winsys_destroy(struct virgl_winsys *vws)
657 {
658 struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
659
660 virgl_cache_flush(vtws);
661
662 mtx_destroy(&vtws->mutex);
663 FREE(vtws);
664 }
665
666 struct virgl_winsys *
667 virgl_vtest_winsys_wrap(struct sw_winsys *sws)
668 {
669 struct virgl_vtest_winsys *vtws;
670
671 vtws = CALLOC_STRUCT(virgl_vtest_winsys);
672 if (!vtws)
673 return NULL;
674
675 virgl_vtest_connect(vtws);
676 vtws->sws = sws;
677
678 vtws->usecs = 1000000;
679 LIST_INITHEAD(&vtws->delayed);
680 (void) mtx_init(&vtws->mutex, mtx_plain);
681
682 vtws->base.destroy = virgl_vtest_winsys_destroy;
683
684 vtws->base.transfer_put = virgl_vtest_transfer_put;
685 vtws->base.transfer_get = virgl_vtest_transfer_get;
686
687 vtws->base.resource_create = virgl_vtest_winsys_resource_cache_create;
688 vtws->base.resource_unref = virgl_vtest_winsys_resource_unref;
689 vtws->base.resource_map = virgl_vtest_resource_map;
690 vtws->base.resource_wait = virgl_vtest_resource_wait;
691 vtws->base.cmd_buf_create = virgl_vtest_cmd_buf_create;
692 vtws->base.cmd_buf_destroy = virgl_vtest_cmd_buf_destroy;
693 vtws->base.submit_cmd = virgl_vtest_winsys_submit_cmd;
694
695 vtws->base.emit_res = virgl_vtest_emit_res;
696 vtws->base.res_is_referenced = virgl_vtest_res_is_ref;
697 vtws->base.get_caps = virgl_vtest_get_caps;
698
699 vtws->base.cs_create_fence = virgl_cs_create_fence;
700 vtws->base.fence_wait = virgl_fence_wait;
701 vtws->base.fence_reference = virgl_fence_reference;
702 vtws->base.supports_fences = 0;
703
704 vtws->base.flush_frontbuffer = virgl_vtest_flush_frontbuffer;
705
706 return &vtws->base;
707 }