nir: add nir_var_all enum
[mesa.git] / src / glsl / nir / nir.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Connor Abbott (cwabbott0@gmail.com)
25 *
26 */
27
28 #include "nir.h"
29 #include "nir_control_flow_private.h"
30 #include <assert.h>
31
32 nir_shader *
33 nir_shader_create(void *mem_ctx,
34 gl_shader_stage stage,
35 const nir_shader_compiler_options *options)
36 {
37 nir_shader *shader = ralloc(mem_ctx, nir_shader);
38
39 exec_list_make_empty(&shader->uniforms);
40 exec_list_make_empty(&shader->inputs);
41 exec_list_make_empty(&shader->outputs);
42
43 shader->options = options;
44 memset(&shader->info, 0, sizeof(shader->info));
45
46 exec_list_make_empty(&shader->functions);
47 exec_list_make_empty(&shader->registers);
48 exec_list_make_empty(&shader->globals);
49 exec_list_make_empty(&shader->system_values);
50 shader->reg_alloc = 0;
51
52 shader->num_inputs = 0;
53 shader->num_outputs = 0;
54 shader->num_uniforms = 0;
55
56 shader->stage = stage;
57
58 return shader;
59 }
60
61 static nir_register *
62 reg_create(void *mem_ctx, struct exec_list *list)
63 {
64 nir_register *reg = ralloc(mem_ctx, nir_register);
65
66 list_inithead(&reg->uses);
67 list_inithead(&reg->defs);
68 list_inithead(&reg->if_uses);
69
70 reg->num_components = 0;
71 reg->num_array_elems = 0;
72 reg->is_packed = false;
73 reg->name = NULL;
74
75 exec_list_push_tail(list, &reg->node);
76
77 return reg;
78 }
79
80 nir_register *
81 nir_global_reg_create(nir_shader *shader)
82 {
83 nir_register *reg = reg_create(shader, &shader->registers);
84 reg->index = shader->reg_alloc++;
85 reg->is_global = true;
86
87 return reg;
88 }
89
90 nir_register *
91 nir_local_reg_create(nir_function_impl *impl)
92 {
93 nir_register *reg = reg_create(ralloc_parent(impl), &impl->registers);
94 reg->index = impl->reg_alloc++;
95 reg->is_global = false;
96
97 return reg;
98 }
99
100 void
101 nir_reg_remove(nir_register *reg)
102 {
103 exec_node_remove(&reg->node);
104 }
105
106 void
107 nir_shader_add_variable(nir_shader *shader, nir_variable *var)
108 {
109 switch (var->data.mode) {
110 case nir_var_all:
111 assert(!"invalid mode");
112 break;
113
114 case nir_var_local:
115 assert(!"nir_shader_add_variable cannot be used for local variables");
116 break;
117
118 case nir_var_global:
119 exec_list_push_tail(&shader->globals, &var->node);
120 break;
121
122 case nir_var_shader_in:
123 exec_list_push_tail(&shader->inputs, &var->node);
124 break;
125
126 case nir_var_shader_out:
127 exec_list_push_tail(&shader->outputs, &var->node);
128 break;
129
130 case nir_var_uniform:
131 case nir_var_shader_storage:
132 exec_list_push_tail(&shader->uniforms, &var->node);
133 break;
134
135 case nir_var_system_value:
136 exec_list_push_tail(&shader->system_values, &var->node);
137 break;
138 }
139 }
140
141 nir_variable *
142 nir_variable_create(nir_shader *shader, nir_variable_mode mode,
143 const struct glsl_type *type, const char *name)
144 {
145 nir_variable *var = rzalloc(shader, nir_variable);
146 var->name = ralloc_strdup(var, name);
147 var->type = type;
148 var->data.mode = mode;
149
150 if ((mode == nir_var_shader_in && shader->stage != MESA_SHADER_VERTEX) ||
151 (mode == nir_var_shader_out && shader->stage != MESA_SHADER_FRAGMENT))
152 var->data.interpolation = INTERP_QUALIFIER_SMOOTH;
153
154 if (mode == nir_var_shader_in || mode == nir_var_uniform)
155 var->data.read_only = true;
156
157 nir_shader_add_variable(shader, var);
158
159 return var;
160 }
161
162 nir_variable *
163 nir_local_variable_create(nir_function_impl *impl,
164 const struct glsl_type *type, const char *name)
165 {
166 nir_variable *var = rzalloc(impl->overload->function->shader, nir_variable);
167 var->name = ralloc_strdup(var, name);
168 var->type = type;
169 var->data.mode = nir_var_local;
170
171 nir_function_impl_add_variable(impl, var);
172
173 return var;
174 }
175
176 nir_function *
177 nir_function_create(nir_shader *shader, const char *name)
178 {
179 nir_function *func = ralloc(shader, nir_function);
180
181 exec_list_push_tail(&shader->functions, &func->node);
182 exec_list_make_empty(&func->overload_list);
183 func->name = ralloc_strdup(func, name);
184 func->shader = shader;
185
186 return func;
187 }
188
189 nir_function_overload *
190 nir_function_overload_create(nir_function *func)
191 {
192 void *mem_ctx = ralloc_parent(func);
193
194 nir_function_overload *overload = ralloc(mem_ctx, nir_function_overload);
195
196 overload->num_params = 0;
197 overload->params = NULL;
198 overload->return_type = glsl_void_type();
199 overload->impl = NULL;
200
201 exec_list_push_tail(&func->overload_list, &overload->node);
202 overload->function = func;
203
204 return overload;
205 }
206
207 void nir_src_copy(nir_src *dest, const nir_src *src, void *mem_ctx)
208 {
209 dest->is_ssa = src->is_ssa;
210 if (src->is_ssa) {
211 dest->ssa = src->ssa;
212 } else {
213 dest->reg.base_offset = src->reg.base_offset;
214 dest->reg.reg = src->reg.reg;
215 if (src->reg.indirect) {
216 dest->reg.indirect = ralloc(mem_ctx, nir_src);
217 nir_src_copy(dest->reg.indirect, src->reg.indirect, mem_ctx);
218 } else {
219 dest->reg.indirect = NULL;
220 }
221 }
222 }
223
224 void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr)
225 {
226 /* Copying an SSA definition makes no sense whatsoever. */
227 assert(!src->is_ssa);
228
229 dest->is_ssa = false;
230
231 dest->reg.base_offset = src->reg.base_offset;
232 dest->reg.reg = src->reg.reg;
233 if (src->reg.indirect) {
234 dest->reg.indirect = ralloc(instr, nir_src);
235 nir_src_copy(dest->reg.indirect, src->reg.indirect, instr);
236 } else {
237 dest->reg.indirect = NULL;
238 }
239 }
240
241 void
242 nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
243 nir_alu_instr *instr)
244 {
245 nir_src_copy(&dest->src, &src->src, &instr->instr);
246 dest->abs = src->abs;
247 dest->negate = src->negate;
248 for (unsigned i = 0; i < 4; i++)
249 dest->swizzle[i] = src->swizzle[i];
250 }
251
252 void
253 nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
254 nir_alu_instr *instr)
255 {
256 nir_dest_copy(&dest->dest, &src->dest, &instr->instr);
257 dest->write_mask = src->write_mask;
258 dest->saturate = src->saturate;
259 }
260
261
262 static void
263 cf_init(nir_cf_node *node, nir_cf_node_type type)
264 {
265 exec_node_init(&node->node);
266 node->parent = NULL;
267 node->type = type;
268 }
269
270 nir_function_impl *
271 nir_function_impl_create(nir_function_overload *overload)
272 {
273 assert(overload->impl == NULL);
274
275 void *mem_ctx = ralloc_parent(overload);
276
277 nir_function_impl *impl = ralloc(mem_ctx, nir_function_impl);
278
279 overload->impl = impl;
280 impl->overload = overload;
281
282 cf_init(&impl->cf_node, nir_cf_node_function);
283
284 exec_list_make_empty(&impl->body);
285 exec_list_make_empty(&impl->registers);
286 exec_list_make_empty(&impl->locals);
287 impl->num_params = 0;
288 impl->params = NULL;
289 impl->return_var = NULL;
290 impl->reg_alloc = 0;
291 impl->ssa_alloc = 0;
292 impl->valid_metadata = nir_metadata_none;
293
294 /* create start & end blocks */
295 nir_block *start_block = nir_block_create(mem_ctx);
296 nir_block *end_block = nir_block_create(mem_ctx);
297 start_block->cf_node.parent = &impl->cf_node;
298 end_block->cf_node.parent = &impl->cf_node;
299 impl->end_block = end_block;
300
301 exec_list_push_tail(&impl->body, &start_block->cf_node.node);
302
303 start_block->successors[0] = end_block;
304 _mesa_set_add(end_block->predecessors, start_block);
305 return impl;
306 }
307
308 nir_block *
309 nir_block_create(nir_shader *shader)
310 {
311 nir_block *block = ralloc(shader, nir_block);
312
313 cf_init(&block->cf_node, nir_cf_node_block);
314
315 block->successors[0] = block->successors[1] = NULL;
316 block->predecessors = _mesa_set_create(block, _mesa_hash_pointer,
317 _mesa_key_pointer_equal);
318 block->imm_dom = NULL;
319 /* XXX maybe it would be worth it to defer allocation? This
320 * way it doesn't get allocated for shader ref's that never run
321 * nir_calc_dominance? For example, state-tracker creates an
322 * initial IR, clones that, runs appropriate lowering pass, passes
323 * to driver which does common lowering/opt, and then stores ref
324 * which is later used to do state specific lowering and futher
325 * opt. Do any of the references not need dominance metadata?
326 */
327 block->dom_frontier = _mesa_set_create(block, _mesa_hash_pointer,
328 _mesa_key_pointer_equal);
329
330 exec_list_make_empty(&block->instr_list);
331
332 return block;
333 }
334
335 static inline void
336 src_init(nir_src *src)
337 {
338 src->is_ssa = false;
339 src->reg.reg = NULL;
340 src->reg.indirect = NULL;
341 src->reg.base_offset = 0;
342 }
343
344 nir_if *
345 nir_if_create(nir_shader *shader)
346 {
347 nir_if *if_stmt = ralloc(shader, nir_if);
348
349 cf_init(&if_stmt->cf_node, nir_cf_node_if);
350 src_init(&if_stmt->condition);
351
352 nir_block *then = nir_block_create(shader);
353 exec_list_make_empty(&if_stmt->then_list);
354 exec_list_push_tail(&if_stmt->then_list, &then->cf_node.node);
355 then->cf_node.parent = &if_stmt->cf_node;
356
357 nir_block *else_stmt = nir_block_create(shader);
358 exec_list_make_empty(&if_stmt->else_list);
359 exec_list_push_tail(&if_stmt->else_list, &else_stmt->cf_node.node);
360 else_stmt->cf_node.parent = &if_stmt->cf_node;
361
362 return if_stmt;
363 }
364
365 nir_loop *
366 nir_loop_create(nir_shader *shader)
367 {
368 nir_loop *loop = ralloc(shader, nir_loop);
369
370 cf_init(&loop->cf_node, nir_cf_node_loop);
371
372 nir_block *body = nir_block_create(shader);
373 exec_list_make_empty(&loop->body);
374 exec_list_push_tail(&loop->body, &body->cf_node.node);
375 body->cf_node.parent = &loop->cf_node;
376
377 body->successors[0] = body;
378 _mesa_set_add(body->predecessors, body);
379
380 return loop;
381 }
382
383 static void
384 instr_init(nir_instr *instr, nir_instr_type type)
385 {
386 instr->type = type;
387 instr->block = NULL;
388 exec_node_init(&instr->node);
389 }
390
391 static void
392 dest_init(nir_dest *dest)
393 {
394 dest->is_ssa = false;
395 dest->reg.reg = NULL;
396 dest->reg.indirect = NULL;
397 dest->reg.base_offset = 0;
398 }
399
400 static void
401 alu_dest_init(nir_alu_dest *dest)
402 {
403 dest_init(&dest->dest);
404 dest->saturate = false;
405 dest->write_mask = 0xf;
406 }
407
408 static void
409 alu_src_init(nir_alu_src *src)
410 {
411 src_init(&src->src);
412 src->abs = src->negate = false;
413 src->swizzle[0] = 0;
414 src->swizzle[1] = 1;
415 src->swizzle[2] = 2;
416 src->swizzle[3] = 3;
417 }
418
419 nir_alu_instr *
420 nir_alu_instr_create(nir_shader *shader, nir_op op)
421 {
422 unsigned num_srcs = nir_op_infos[op].num_inputs;
423 nir_alu_instr *instr =
424 ralloc_size(shader,
425 sizeof(nir_alu_instr) + num_srcs * sizeof(nir_alu_src));
426
427 instr_init(&instr->instr, nir_instr_type_alu);
428 instr->op = op;
429 alu_dest_init(&instr->dest);
430 for (unsigned i = 0; i < num_srcs; i++)
431 alu_src_init(&instr->src[i]);
432
433 return instr;
434 }
435
436 nir_jump_instr *
437 nir_jump_instr_create(nir_shader *shader, nir_jump_type type)
438 {
439 nir_jump_instr *instr = ralloc(shader, nir_jump_instr);
440 instr_init(&instr->instr, nir_instr_type_jump);
441 instr->type = type;
442 return instr;
443 }
444
445 nir_load_const_instr *
446 nir_load_const_instr_create(nir_shader *shader, unsigned num_components)
447 {
448 nir_load_const_instr *instr = ralloc(shader, nir_load_const_instr);
449 instr_init(&instr->instr, nir_instr_type_load_const);
450
451 nir_ssa_def_init(&instr->instr, &instr->def, num_components, NULL);
452
453 return instr;
454 }
455
456 nir_intrinsic_instr *
457 nir_intrinsic_instr_create(nir_shader *shader, nir_intrinsic_op op)
458 {
459 unsigned num_srcs = nir_intrinsic_infos[op].num_srcs;
460 nir_intrinsic_instr *instr =
461 ralloc_size(shader,
462 sizeof(nir_intrinsic_instr) + num_srcs * sizeof(nir_src));
463
464 instr_init(&instr->instr, nir_instr_type_intrinsic);
465 instr->intrinsic = op;
466
467 if (nir_intrinsic_infos[op].has_dest)
468 dest_init(&instr->dest);
469
470 for (unsigned i = 0; i < num_srcs; i++)
471 src_init(&instr->src[i]);
472
473 return instr;
474 }
475
476 nir_call_instr *
477 nir_call_instr_create(nir_shader *shader, nir_function_overload *callee)
478 {
479 nir_call_instr *instr = ralloc(shader, nir_call_instr);
480 instr_init(&instr->instr, nir_instr_type_call);
481
482 instr->callee = callee;
483 instr->num_params = callee->num_params;
484 instr->params = ralloc_array(instr, nir_deref_var *, instr->num_params);
485 instr->return_deref = NULL;
486
487 return instr;
488 }
489
490 nir_tex_instr *
491 nir_tex_instr_create(nir_shader *shader, unsigned num_srcs)
492 {
493 nir_tex_instr *instr = rzalloc(shader, nir_tex_instr);
494 instr_init(&instr->instr, nir_instr_type_tex);
495
496 dest_init(&instr->dest);
497
498 instr->num_srcs = num_srcs;
499 instr->src = ralloc_array(instr, nir_tex_src, num_srcs);
500 for (unsigned i = 0; i < num_srcs; i++)
501 src_init(&instr->src[i].src);
502
503 instr->sampler_index = 0;
504 instr->sampler_array_size = 0;
505 instr->sampler = NULL;
506
507 return instr;
508 }
509
510 nir_phi_instr *
511 nir_phi_instr_create(nir_shader *shader)
512 {
513 nir_phi_instr *instr = ralloc(shader, nir_phi_instr);
514 instr_init(&instr->instr, nir_instr_type_phi);
515
516 dest_init(&instr->dest);
517 exec_list_make_empty(&instr->srcs);
518 return instr;
519 }
520
521 nir_parallel_copy_instr *
522 nir_parallel_copy_instr_create(nir_shader *shader)
523 {
524 nir_parallel_copy_instr *instr = ralloc(shader, nir_parallel_copy_instr);
525 instr_init(&instr->instr, nir_instr_type_parallel_copy);
526
527 exec_list_make_empty(&instr->entries);
528
529 return instr;
530 }
531
532 nir_ssa_undef_instr *
533 nir_ssa_undef_instr_create(nir_shader *shader, unsigned num_components)
534 {
535 nir_ssa_undef_instr *instr = ralloc(shader, nir_ssa_undef_instr);
536 instr_init(&instr->instr, nir_instr_type_ssa_undef);
537
538 nir_ssa_def_init(&instr->instr, &instr->def, num_components, NULL);
539
540 return instr;
541 }
542
543 nir_deref_var *
544 nir_deref_var_create(void *mem_ctx, nir_variable *var)
545 {
546 nir_deref_var *deref = ralloc(mem_ctx, nir_deref_var);
547 deref->deref.deref_type = nir_deref_type_var;
548 deref->deref.child = NULL;
549 deref->deref.type = var->type;
550 deref->var = var;
551 return deref;
552 }
553
554 nir_deref_array *
555 nir_deref_array_create(void *mem_ctx)
556 {
557 nir_deref_array *deref = ralloc(mem_ctx, nir_deref_array);
558 deref->deref.deref_type = nir_deref_type_array;
559 deref->deref.child = NULL;
560 deref->deref_array_type = nir_deref_array_type_direct;
561 src_init(&deref->indirect);
562 deref->base_offset = 0;
563 return deref;
564 }
565
566 nir_deref_struct *
567 nir_deref_struct_create(void *mem_ctx, unsigned field_index)
568 {
569 nir_deref_struct *deref = ralloc(mem_ctx, nir_deref_struct);
570 deref->deref.deref_type = nir_deref_type_struct;
571 deref->deref.child = NULL;
572 deref->index = field_index;
573 return deref;
574 }
575
576 static nir_deref_var *
577 copy_deref_var(void *mem_ctx, nir_deref_var *deref)
578 {
579 nir_deref_var *ret = nir_deref_var_create(mem_ctx, deref->var);
580 ret->deref.type = deref->deref.type;
581 if (deref->deref.child)
582 ret->deref.child = nir_copy_deref(ret, deref->deref.child);
583 return ret;
584 }
585
586 static nir_deref_array *
587 copy_deref_array(void *mem_ctx, nir_deref_array *deref)
588 {
589 nir_deref_array *ret = nir_deref_array_create(mem_ctx);
590 ret->base_offset = deref->base_offset;
591 ret->deref_array_type = deref->deref_array_type;
592 if (deref->deref_array_type == nir_deref_array_type_indirect) {
593 nir_src_copy(&ret->indirect, &deref->indirect, mem_ctx);
594 }
595 ret->deref.type = deref->deref.type;
596 if (deref->deref.child)
597 ret->deref.child = nir_copy_deref(ret, deref->deref.child);
598 return ret;
599 }
600
601 static nir_deref_struct *
602 copy_deref_struct(void *mem_ctx, nir_deref_struct *deref)
603 {
604 nir_deref_struct *ret = nir_deref_struct_create(mem_ctx, deref->index);
605 ret->deref.type = deref->deref.type;
606 if (deref->deref.child)
607 ret->deref.child = nir_copy_deref(ret, deref->deref.child);
608 return ret;
609 }
610
611 nir_deref *
612 nir_copy_deref(void *mem_ctx, nir_deref *deref)
613 {
614 switch (deref->deref_type) {
615 case nir_deref_type_var:
616 return &copy_deref_var(mem_ctx, nir_deref_as_var(deref))->deref;
617 case nir_deref_type_array:
618 return &copy_deref_array(mem_ctx, nir_deref_as_array(deref))->deref;
619 case nir_deref_type_struct:
620 return &copy_deref_struct(mem_ctx, nir_deref_as_struct(deref))->deref;
621 default:
622 unreachable("Invalid dereference type");
623 }
624
625 return NULL;
626 }
627
628 /* Returns a load_const instruction that represents the constant
629 * initializer for the given deref chain. The caller is responsible for
630 * ensuring that there actually is a constant initializer.
631 */
632 nir_load_const_instr *
633 nir_deref_get_const_initializer_load(nir_shader *shader, nir_deref_var *deref)
634 {
635 nir_constant *constant = deref->var->constant_initializer;
636 assert(constant);
637
638 const nir_deref *tail = &deref->deref;
639 unsigned matrix_offset = 0;
640 while (tail->child) {
641 switch (tail->child->deref_type) {
642 case nir_deref_type_array: {
643 nir_deref_array *arr = nir_deref_as_array(tail->child);
644 assert(arr->deref_array_type == nir_deref_array_type_direct);
645 if (glsl_type_is_matrix(tail->type)) {
646 assert(arr->deref.child == NULL);
647 matrix_offset = arr->base_offset;
648 } else {
649 constant = constant->elements[arr->base_offset];
650 }
651 break;
652 }
653
654 case nir_deref_type_struct: {
655 constant = constant->elements[nir_deref_as_struct(tail->child)->index];
656 break;
657 }
658
659 default:
660 unreachable("Invalid deref child type");
661 }
662
663 tail = tail->child;
664 }
665
666 nir_load_const_instr *load =
667 nir_load_const_instr_create(shader, glsl_get_vector_elements(tail->type));
668
669 matrix_offset *= load->def.num_components;
670 for (unsigned i = 0; i < load->def.num_components; i++) {
671 switch (glsl_get_base_type(tail->type)) {
672 case GLSL_TYPE_FLOAT:
673 case GLSL_TYPE_INT:
674 case GLSL_TYPE_UINT:
675 load->value.u[i] = constant->value.u[matrix_offset + i];
676 break;
677 case GLSL_TYPE_BOOL:
678 load->value.u[i] = constant->value.b[matrix_offset + i] ?
679 NIR_TRUE : NIR_FALSE;
680 break;
681 default:
682 unreachable("Invalid immediate type");
683 }
684 }
685
686 return load;
687 }
688
689 nir_function_impl *
690 nir_cf_node_get_function(nir_cf_node *node)
691 {
692 while (node->type != nir_cf_node_function) {
693 node = node->parent;
694 }
695
696 return nir_cf_node_as_function(node);
697 }
698
699 static bool
700 add_use_cb(nir_src *src, void *state)
701 {
702 nir_instr *instr = state;
703
704 src->parent_instr = instr;
705 list_addtail(&src->use_link,
706 src->is_ssa ? &src->ssa->uses : &src->reg.reg->uses);
707
708 return true;
709 }
710
711 static bool
712 add_ssa_def_cb(nir_ssa_def *def, void *state)
713 {
714 nir_instr *instr = state;
715
716 if (instr->block && def->index == UINT_MAX) {
717 nir_function_impl *impl =
718 nir_cf_node_get_function(&instr->block->cf_node);
719
720 def->index = impl->ssa_alloc++;
721 }
722
723 return true;
724 }
725
726 static bool
727 add_reg_def_cb(nir_dest *dest, void *state)
728 {
729 nir_instr *instr = state;
730
731 if (!dest->is_ssa) {
732 dest->reg.parent_instr = instr;
733 list_addtail(&dest->reg.def_link, &dest->reg.reg->defs);
734 }
735
736 return true;
737 }
738
739 static void
740 add_defs_uses(nir_instr *instr)
741 {
742 nir_foreach_src(instr, add_use_cb, instr);
743 nir_foreach_dest(instr, add_reg_def_cb, instr);
744 nir_foreach_ssa_def(instr, add_ssa_def_cb, instr);
745 }
746
747 void
748 nir_instr_insert(nir_cursor cursor, nir_instr *instr)
749 {
750 switch (cursor.option) {
751 case nir_cursor_before_block:
752 /* Only allow inserting jumps into empty blocks. */
753 if (instr->type == nir_instr_type_jump)
754 assert(exec_list_is_empty(&cursor.block->instr_list));
755
756 instr->block = cursor.block;
757 add_defs_uses(instr);
758 exec_list_push_head(&cursor.block->instr_list, &instr->node);
759 break;
760 case nir_cursor_after_block: {
761 /* Inserting instructions after a jump is illegal. */
762 nir_instr *last = nir_block_last_instr(cursor.block);
763 assert(last == NULL || last->type != nir_instr_type_jump);
764 (void) last;
765
766 instr->block = cursor.block;
767 add_defs_uses(instr);
768 exec_list_push_tail(&cursor.block->instr_list, &instr->node);
769 break;
770 }
771 case nir_cursor_before_instr:
772 assert(instr->type != nir_instr_type_jump);
773 instr->block = cursor.instr->block;
774 add_defs_uses(instr);
775 exec_node_insert_node_before(&cursor.instr->node, &instr->node);
776 break;
777 case nir_cursor_after_instr:
778 /* Inserting instructions after a jump is illegal. */
779 assert(cursor.instr->type != nir_instr_type_jump);
780
781 /* Only allow inserting jumps at the end of the block. */
782 if (instr->type == nir_instr_type_jump)
783 assert(cursor.instr == nir_block_last_instr(cursor.instr->block));
784
785 instr->block = cursor.instr->block;
786 add_defs_uses(instr);
787 exec_node_insert_after(&cursor.instr->node, &instr->node);
788 break;
789 }
790
791 if (instr->type == nir_instr_type_jump)
792 nir_handle_add_jump(instr->block);
793 }
794
795 static bool
796 src_is_valid(const nir_src *src)
797 {
798 return src->is_ssa ? (src->ssa != NULL) : (src->reg.reg != NULL);
799 }
800
801 static bool
802 remove_use_cb(nir_src *src, void *state)
803 {
804 if (src_is_valid(src))
805 list_del(&src->use_link);
806
807 return true;
808 }
809
810 static bool
811 remove_def_cb(nir_dest *dest, void *state)
812 {
813 if (!dest->is_ssa)
814 list_del(&dest->reg.def_link);
815
816 return true;
817 }
818
819 static void
820 remove_defs_uses(nir_instr *instr)
821 {
822 nir_foreach_dest(instr, remove_def_cb, instr);
823 nir_foreach_src(instr, remove_use_cb, instr);
824 }
825
826 void nir_instr_remove(nir_instr *instr)
827 {
828 remove_defs_uses(instr);
829 exec_node_remove(&instr->node);
830
831 if (instr->type == nir_instr_type_jump) {
832 nir_jump_instr *jump_instr = nir_instr_as_jump(instr);
833 nir_handle_remove_jump(instr->block, jump_instr->type);
834 }
835 }
836
837 /*@}*/
838
839 void
840 nir_index_local_regs(nir_function_impl *impl)
841 {
842 unsigned index = 0;
843 foreach_list_typed(nir_register, reg, node, &impl->registers) {
844 reg->index = index++;
845 }
846 impl->reg_alloc = index;
847 }
848
849 void
850 nir_index_global_regs(nir_shader *shader)
851 {
852 unsigned index = 0;
853 foreach_list_typed(nir_register, reg, node, &shader->registers) {
854 reg->index = index++;
855 }
856 shader->reg_alloc = index;
857 }
858
859 static bool
860 visit_alu_dest(nir_alu_instr *instr, nir_foreach_dest_cb cb, void *state)
861 {
862 return cb(&instr->dest.dest, state);
863 }
864
865 static bool
866 visit_intrinsic_dest(nir_intrinsic_instr *instr, nir_foreach_dest_cb cb,
867 void *state)
868 {
869 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
870 return cb(&instr->dest, state);
871
872 return true;
873 }
874
875 static bool
876 visit_texture_dest(nir_tex_instr *instr, nir_foreach_dest_cb cb,
877 void *state)
878 {
879 return cb(&instr->dest, state);
880 }
881
882 static bool
883 visit_phi_dest(nir_phi_instr *instr, nir_foreach_dest_cb cb, void *state)
884 {
885 return cb(&instr->dest, state);
886 }
887
888 static bool
889 visit_parallel_copy_dest(nir_parallel_copy_instr *instr,
890 nir_foreach_dest_cb cb, void *state)
891 {
892 nir_foreach_parallel_copy_entry(instr, entry) {
893 if (!cb(&entry->dest, state))
894 return false;
895 }
896
897 return true;
898 }
899
900 bool
901 nir_foreach_dest(nir_instr *instr, nir_foreach_dest_cb cb, void *state)
902 {
903 switch (instr->type) {
904 case nir_instr_type_alu:
905 return visit_alu_dest(nir_instr_as_alu(instr), cb, state);
906 case nir_instr_type_intrinsic:
907 return visit_intrinsic_dest(nir_instr_as_intrinsic(instr), cb, state);
908 case nir_instr_type_tex:
909 return visit_texture_dest(nir_instr_as_tex(instr), cb, state);
910 case nir_instr_type_phi:
911 return visit_phi_dest(nir_instr_as_phi(instr), cb, state);
912 case nir_instr_type_parallel_copy:
913 return visit_parallel_copy_dest(nir_instr_as_parallel_copy(instr),
914 cb, state);
915
916 case nir_instr_type_load_const:
917 case nir_instr_type_ssa_undef:
918 case nir_instr_type_call:
919 case nir_instr_type_jump:
920 break;
921
922 default:
923 unreachable("Invalid instruction type");
924 break;
925 }
926
927 return true;
928 }
929
930 struct foreach_ssa_def_state {
931 nir_foreach_ssa_def_cb cb;
932 void *client_state;
933 };
934
935 static inline bool
936 nir_ssa_def_visitor(nir_dest *dest, void *void_state)
937 {
938 struct foreach_ssa_def_state *state = void_state;
939
940 if (dest->is_ssa)
941 return state->cb(&dest->ssa, state->client_state);
942 else
943 return true;
944 }
945
946 bool
947 nir_foreach_ssa_def(nir_instr *instr, nir_foreach_ssa_def_cb cb, void *state)
948 {
949 switch (instr->type) {
950 case nir_instr_type_alu:
951 case nir_instr_type_tex:
952 case nir_instr_type_intrinsic:
953 case nir_instr_type_phi:
954 case nir_instr_type_parallel_copy: {
955 struct foreach_ssa_def_state foreach_state = {cb, state};
956 return nir_foreach_dest(instr, nir_ssa_def_visitor, &foreach_state);
957 }
958
959 case nir_instr_type_load_const:
960 return cb(&nir_instr_as_load_const(instr)->def, state);
961 case nir_instr_type_ssa_undef:
962 return cb(&nir_instr_as_ssa_undef(instr)->def, state);
963 case nir_instr_type_call:
964 case nir_instr_type_jump:
965 return true;
966 default:
967 unreachable("Invalid instruction type");
968 }
969 }
970
971 static bool
972 visit_src(nir_src *src, nir_foreach_src_cb cb, void *state)
973 {
974 if (!cb(src, state))
975 return false;
976 if (!src->is_ssa && src->reg.indirect)
977 return cb(src->reg.indirect, state);
978 return true;
979 }
980
981 static bool
982 visit_deref_array_src(nir_deref_array *deref, nir_foreach_src_cb cb,
983 void *state)
984 {
985 if (deref->deref_array_type == nir_deref_array_type_indirect)
986 return visit_src(&deref->indirect, cb, state);
987 return true;
988 }
989
990 static bool
991 visit_deref_src(nir_deref_var *deref, nir_foreach_src_cb cb, void *state)
992 {
993 nir_deref *cur = &deref->deref;
994 while (cur != NULL) {
995 if (cur->deref_type == nir_deref_type_array)
996 if (!visit_deref_array_src(nir_deref_as_array(cur), cb, state))
997 return false;
998
999 cur = cur->child;
1000 }
1001
1002 return true;
1003 }
1004
1005 static bool
1006 visit_alu_src(nir_alu_instr *instr, nir_foreach_src_cb cb, void *state)
1007 {
1008 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1009 if (!visit_src(&instr->src[i].src, cb, state))
1010 return false;
1011
1012 return true;
1013 }
1014
1015 static bool
1016 visit_tex_src(nir_tex_instr *instr, nir_foreach_src_cb cb, void *state)
1017 {
1018 for (unsigned i = 0; i < instr->num_srcs; i++)
1019 if (!visit_src(&instr->src[i].src, cb, state))
1020 return false;
1021
1022 if (instr->sampler != NULL)
1023 if (!visit_deref_src(instr->sampler, cb, state))
1024 return false;
1025
1026 return true;
1027 }
1028
1029 static bool
1030 visit_intrinsic_src(nir_intrinsic_instr *instr, nir_foreach_src_cb cb,
1031 void *state)
1032 {
1033 unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs;
1034 for (unsigned i = 0; i < num_srcs; i++)
1035 if (!visit_src(&instr->src[i], cb, state))
1036 return false;
1037
1038 unsigned num_vars =
1039 nir_intrinsic_infos[instr->intrinsic].num_variables;
1040 for (unsigned i = 0; i < num_vars; i++)
1041 if (!visit_deref_src(instr->variables[i], cb, state))
1042 return false;
1043
1044 return true;
1045 }
1046
1047 static bool
1048 visit_call_src(nir_call_instr *instr, nir_foreach_src_cb cb, void *state)
1049 {
1050 return true;
1051 }
1052
1053 static bool
1054 visit_load_const_src(nir_load_const_instr *instr, nir_foreach_src_cb cb,
1055 void *state)
1056 {
1057 return true;
1058 }
1059
1060 static bool
1061 visit_phi_src(nir_phi_instr *instr, nir_foreach_src_cb cb, void *state)
1062 {
1063 nir_foreach_phi_src(instr, src) {
1064 if (!visit_src(&src->src, cb, state))
1065 return false;
1066 }
1067
1068 return true;
1069 }
1070
1071 static bool
1072 visit_parallel_copy_src(nir_parallel_copy_instr *instr,
1073 nir_foreach_src_cb cb, void *state)
1074 {
1075 nir_foreach_parallel_copy_entry(instr, entry) {
1076 if (!visit_src(&entry->src, cb, state))
1077 return false;
1078 }
1079
1080 return true;
1081 }
1082
1083 typedef struct {
1084 void *state;
1085 nir_foreach_src_cb cb;
1086 } visit_dest_indirect_state;
1087
1088 static bool
1089 visit_dest_indirect(nir_dest *dest, void *_state)
1090 {
1091 visit_dest_indirect_state *state = (visit_dest_indirect_state *) _state;
1092
1093 if (!dest->is_ssa && dest->reg.indirect)
1094 return state->cb(dest->reg.indirect, state->state);
1095
1096 return true;
1097 }
1098
1099 bool
1100 nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state)
1101 {
1102 switch (instr->type) {
1103 case nir_instr_type_alu:
1104 if (!visit_alu_src(nir_instr_as_alu(instr), cb, state))
1105 return false;
1106 break;
1107 case nir_instr_type_intrinsic:
1108 if (!visit_intrinsic_src(nir_instr_as_intrinsic(instr), cb, state))
1109 return false;
1110 break;
1111 case nir_instr_type_tex:
1112 if (!visit_tex_src(nir_instr_as_tex(instr), cb, state))
1113 return false;
1114 break;
1115 case nir_instr_type_call:
1116 if (!visit_call_src(nir_instr_as_call(instr), cb, state))
1117 return false;
1118 break;
1119 case nir_instr_type_load_const:
1120 if (!visit_load_const_src(nir_instr_as_load_const(instr), cb, state))
1121 return false;
1122 break;
1123 case nir_instr_type_phi:
1124 if (!visit_phi_src(nir_instr_as_phi(instr), cb, state))
1125 return false;
1126 break;
1127 case nir_instr_type_parallel_copy:
1128 if (!visit_parallel_copy_src(nir_instr_as_parallel_copy(instr),
1129 cb, state))
1130 return false;
1131 break;
1132 case nir_instr_type_jump:
1133 case nir_instr_type_ssa_undef:
1134 return true;
1135
1136 default:
1137 unreachable("Invalid instruction type");
1138 break;
1139 }
1140
1141 visit_dest_indirect_state dest_state;
1142 dest_state.state = state;
1143 dest_state.cb = cb;
1144 return nir_foreach_dest(instr, visit_dest_indirect, &dest_state);
1145 }
1146
1147 nir_const_value *
1148 nir_src_as_const_value(nir_src src)
1149 {
1150 if (!src.is_ssa)
1151 return NULL;
1152
1153 if (src.ssa->parent_instr->type != nir_instr_type_load_const)
1154 return NULL;
1155
1156 nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
1157
1158 return &load->value;
1159 }
1160
1161 /**
1162 * Returns true if the source is known to be dynamically uniform. Otherwise it
1163 * returns false which means it may or may not be dynamically uniform but it
1164 * can't be determined.
1165 */
1166 bool
1167 nir_src_is_dynamically_uniform(nir_src src)
1168 {
1169 if (!src.is_ssa)
1170 return false;
1171
1172 /* Constants are trivially dynamically uniform */
1173 if (src.ssa->parent_instr->type == nir_instr_type_load_const)
1174 return true;
1175
1176 /* As are uniform variables */
1177 if (src.ssa->parent_instr->type == nir_instr_type_intrinsic) {
1178 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(src.ssa->parent_instr);
1179
1180 if (intr->intrinsic == nir_intrinsic_load_uniform)
1181 return true;
1182 }
1183
1184 /* XXX: this could have many more tests, such as when a sampler function is
1185 * called with dynamically uniform arguments.
1186 */
1187 return false;
1188 }
1189
1190 static void
1191 src_remove_all_uses(nir_src *src)
1192 {
1193 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1194 if (!src_is_valid(src))
1195 continue;
1196
1197 list_del(&src->use_link);
1198 }
1199 }
1200
1201 static void
1202 src_add_all_uses(nir_src *src, nir_instr *parent_instr, nir_if *parent_if)
1203 {
1204 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1205 if (!src_is_valid(src))
1206 continue;
1207
1208 if (parent_instr) {
1209 src->parent_instr = parent_instr;
1210 if (src->is_ssa)
1211 list_addtail(&src->use_link, &src->ssa->uses);
1212 else
1213 list_addtail(&src->use_link, &src->reg.reg->uses);
1214 } else {
1215 assert(parent_if);
1216 src->parent_if = parent_if;
1217 if (src->is_ssa)
1218 list_addtail(&src->use_link, &src->ssa->if_uses);
1219 else
1220 list_addtail(&src->use_link, &src->reg.reg->if_uses);
1221 }
1222 }
1223 }
1224
1225 void
1226 nir_instr_rewrite_src(nir_instr *instr, nir_src *src, nir_src new_src)
1227 {
1228 assert(!src_is_valid(src) || src->parent_instr == instr);
1229
1230 src_remove_all_uses(src);
1231 *src = new_src;
1232 src_add_all_uses(src, instr, NULL);
1233 }
1234
1235 void
1236 nir_instr_move_src(nir_instr *dest_instr, nir_src *dest, nir_src *src)
1237 {
1238 assert(!src_is_valid(dest) || dest->parent_instr == dest_instr);
1239
1240 src_remove_all_uses(dest);
1241 src_remove_all_uses(src);
1242 *dest = *src;
1243 *src = NIR_SRC_INIT;
1244 src_add_all_uses(dest, dest_instr, NULL);
1245 }
1246
1247 void
1248 nir_if_rewrite_condition(nir_if *if_stmt, nir_src new_src)
1249 {
1250 nir_src *src = &if_stmt->condition;
1251 assert(!src_is_valid(src) || src->parent_if == if_stmt);
1252
1253 src_remove_all_uses(src);
1254 *src = new_src;
1255 src_add_all_uses(src, NULL, if_stmt);
1256 }
1257
1258 void
1259 nir_instr_rewrite_dest(nir_instr *instr, nir_dest *dest, nir_dest new_dest)
1260 {
1261 if (dest->is_ssa) {
1262 /* We can only overwrite an SSA destination if it has no uses. */
1263 assert(list_empty(&dest->ssa.uses) && list_empty(&dest->ssa.if_uses));
1264 } else {
1265 list_del(&dest->reg.def_link);
1266 if (dest->reg.indirect)
1267 src_remove_all_uses(dest->reg.indirect);
1268 }
1269
1270 /* We can't re-write with an SSA def */
1271 assert(!new_dest.is_ssa);
1272
1273 nir_dest_copy(dest, &new_dest, instr);
1274
1275 dest->reg.parent_instr = instr;
1276 list_addtail(&dest->reg.def_link, &new_dest.reg.reg->defs);
1277
1278 if (dest->reg.indirect)
1279 src_add_all_uses(dest->reg.indirect, instr, NULL);
1280 }
1281
1282 void
1283 nir_ssa_def_init(nir_instr *instr, nir_ssa_def *def,
1284 unsigned num_components, const char *name)
1285 {
1286 def->name = name;
1287 def->parent_instr = instr;
1288 list_inithead(&def->uses);
1289 list_inithead(&def->if_uses);
1290 def->num_components = num_components;
1291
1292 if (instr->block) {
1293 nir_function_impl *impl =
1294 nir_cf_node_get_function(&instr->block->cf_node);
1295
1296 def->index = impl->ssa_alloc++;
1297 } else {
1298 def->index = UINT_MAX;
1299 }
1300 }
1301
1302 void
1303 nir_ssa_dest_init(nir_instr *instr, nir_dest *dest,
1304 unsigned num_components, const char *name)
1305 {
1306 dest->is_ssa = true;
1307 nir_ssa_def_init(instr, &dest->ssa, num_components, name);
1308 }
1309
1310 void
1311 nir_ssa_def_rewrite_uses(nir_ssa_def *def, nir_src new_src)
1312 {
1313 assert(!new_src.is_ssa || def != new_src.ssa);
1314
1315 nir_foreach_use_safe(def, use_src) {
1316 nir_instr *src_parent_instr = use_src->parent_instr;
1317 list_del(&use_src->use_link);
1318 nir_src_copy(use_src, &new_src, src_parent_instr);
1319 src_add_all_uses(use_src, src_parent_instr, NULL);
1320 }
1321
1322 nir_foreach_if_use_safe(def, use_src) {
1323 nir_if *src_parent_if = use_src->parent_if;
1324 list_del(&use_src->use_link);
1325 nir_src_copy(use_src, &new_src, src_parent_if);
1326 src_add_all_uses(use_src, NULL, src_parent_if);
1327 }
1328 }
1329
1330
1331 static bool foreach_cf_node(nir_cf_node *node, nir_foreach_block_cb cb,
1332 bool reverse, void *state);
1333
1334 static inline bool
1335 foreach_if(nir_if *if_stmt, nir_foreach_block_cb cb, bool reverse, void *state)
1336 {
1337 if (reverse) {
1338 foreach_list_typed_safe_reverse(nir_cf_node, node, node,
1339 &if_stmt->else_list) {
1340 if (!foreach_cf_node(node, cb, reverse, state))
1341 return false;
1342 }
1343
1344 foreach_list_typed_safe_reverse(nir_cf_node, node, node,
1345 &if_stmt->then_list) {
1346 if (!foreach_cf_node(node, cb, reverse, state))
1347 return false;
1348 }
1349 } else {
1350 foreach_list_typed_safe(nir_cf_node, node, node, &if_stmt->then_list) {
1351 if (!foreach_cf_node(node, cb, reverse, state))
1352 return false;
1353 }
1354
1355 foreach_list_typed_safe(nir_cf_node, node, node, &if_stmt->else_list) {
1356 if (!foreach_cf_node(node, cb, reverse, state))
1357 return false;
1358 }
1359 }
1360
1361 return true;
1362 }
1363
1364 static inline bool
1365 foreach_loop(nir_loop *loop, nir_foreach_block_cb cb, bool reverse, void *state)
1366 {
1367 if (reverse) {
1368 foreach_list_typed_safe_reverse(nir_cf_node, node, node, &loop->body) {
1369 if (!foreach_cf_node(node, cb, reverse, state))
1370 return false;
1371 }
1372 } else {
1373 foreach_list_typed_safe(nir_cf_node, node, node, &loop->body) {
1374 if (!foreach_cf_node(node, cb, reverse, state))
1375 return false;
1376 }
1377 }
1378
1379 return true;
1380 }
1381
1382 static bool
1383 foreach_cf_node(nir_cf_node *node, nir_foreach_block_cb cb,
1384 bool reverse, void *state)
1385 {
1386 switch (node->type) {
1387 case nir_cf_node_block:
1388 return cb(nir_cf_node_as_block(node), state);
1389 case nir_cf_node_if:
1390 return foreach_if(nir_cf_node_as_if(node), cb, reverse, state);
1391 case nir_cf_node_loop:
1392 return foreach_loop(nir_cf_node_as_loop(node), cb, reverse, state);
1393 break;
1394
1395 default:
1396 unreachable("Invalid CFG node type");
1397 break;
1398 }
1399
1400 return false;
1401 }
1402
1403 bool
1404 nir_foreach_block_in_cf_node(nir_cf_node *node, nir_foreach_block_cb cb,
1405 void *state)
1406 {
1407 return foreach_cf_node(node, cb, false, state);
1408 }
1409
1410 bool
1411 nir_foreach_block(nir_function_impl *impl, nir_foreach_block_cb cb, void *state)
1412 {
1413 foreach_list_typed_safe(nir_cf_node, node, node, &impl->body) {
1414 if (!foreach_cf_node(node, cb, false, state))
1415 return false;
1416 }
1417
1418 return cb(impl->end_block, state);
1419 }
1420
1421 bool
1422 nir_foreach_block_reverse(nir_function_impl *impl, nir_foreach_block_cb cb,
1423 void *state)
1424 {
1425 if (!cb(impl->end_block, state))
1426 return false;
1427
1428 foreach_list_typed_safe_reverse(nir_cf_node, node, node, &impl->body) {
1429 if (!foreach_cf_node(node, cb, true, state))
1430 return false;
1431 }
1432
1433 return true;
1434 }
1435
1436 nir_if *
1437 nir_block_get_following_if(nir_block *block)
1438 {
1439 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1440 return NULL;
1441
1442 if (nir_cf_node_is_last(&block->cf_node))
1443 return NULL;
1444
1445 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1446
1447 if (next_node->type != nir_cf_node_if)
1448 return NULL;
1449
1450 return nir_cf_node_as_if(next_node);
1451 }
1452
1453 nir_loop *
1454 nir_block_get_following_loop(nir_block *block)
1455 {
1456 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1457 return NULL;
1458
1459 if (nir_cf_node_is_last(&block->cf_node))
1460 return NULL;
1461
1462 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1463
1464 if (next_node->type != nir_cf_node_loop)
1465 return NULL;
1466
1467 return nir_cf_node_as_loop(next_node);
1468 }
1469 static bool
1470 index_block(nir_block *block, void *state)
1471 {
1472 unsigned *index = state;
1473 block->index = (*index)++;
1474 return true;
1475 }
1476
1477 void
1478 nir_index_blocks(nir_function_impl *impl)
1479 {
1480 unsigned index = 0;
1481
1482 if (impl->valid_metadata & nir_metadata_block_index)
1483 return;
1484
1485 nir_foreach_block(impl, index_block, &index);
1486
1487 impl->num_blocks = index;
1488 }
1489
1490 static bool
1491 index_ssa_def_cb(nir_ssa_def *def, void *state)
1492 {
1493 unsigned *index = (unsigned *) state;
1494 def->index = (*index)++;
1495
1496 return true;
1497 }
1498
1499 static bool
1500 index_ssa_block(nir_block *block, void *state)
1501 {
1502 nir_foreach_instr(block, instr)
1503 nir_foreach_ssa_def(instr, index_ssa_def_cb, state);
1504
1505 return true;
1506 }
1507
1508 /**
1509 * The indices are applied top-to-bottom which has the very nice property
1510 * that, if A dominates B, then A->index <= B->index.
1511 */
1512 void
1513 nir_index_ssa_defs(nir_function_impl *impl)
1514 {
1515 unsigned index = 0;
1516 nir_foreach_block(impl, index_ssa_block, &index);
1517 impl->ssa_alloc = index;
1518 }
1519
1520 static bool
1521 index_instrs_block(nir_block *block, void *state)
1522 {
1523 unsigned *index = state;
1524 nir_foreach_instr(block, instr)
1525 instr->index = (*index)++;
1526
1527 return true;
1528 }
1529
1530 /**
1531 * The indices are applied top-to-bottom which has the very nice property
1532 * that, if A dominates B, then A->index <= B->index.
1533 */
1534 unsigned
1535 nir_index_instrs(nir_function_impl *impl)
1536 {
1537 unsigned index = 0;
1538 nir_foreach_block(impl, index_instrs_block, &index);
1539 return index;
1540 }
1541
1542 nir_intrinsic_op
1543 nir_intrinsic_from_system_value(gl_system_value val)
1544 {
1545 switch (val) {
1546 case SYSTEM_VALUE_VERTEX_ID:
1547 return nir_intrinsic_load_vertex_id;
1548 case SYSTEM_VALUE_INSTANCE_ID:
1549 return nir_intrinsic_load_instance_id;
1550 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
1551 return nir_intrinsic_load_vertex_id_zero_base;
1552 case SYSTEM_VALUE_BASE_VERTEX:
1553 return nir_intrinsic_load_base_vertex;
1554 case SYSTEM_VALUE_INVOCATION_ID:
1555 return nir_intrinsic_load_invocation_id;
1556 case SYSTEM_VALUE_FRONT_FACE:
1557 return nir_intrinsic_load_front_face;
1558 case SYSTEM_VALUE_SAMPLE_ID:
1559 return nir_intrinsic_load_sample_id;
1560 case SYSTEM_VALUE_SAMPLE_POS:
1561 return nir_intrinsic_load_sample_pos;
1562 case SYSTEM_VALUE_SAMPLE_MASK_IN:
1563 return nir_intrinsic_load_sample_mask_in;
1564 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
1565 return nir_intrinsic_load_local_invocation_id;
1566 case SYSTEM_VALUE_WORK_GROUP_ID:
1567 return nir_intrinsic_load_work_group_id;
1568 case SYSTEM_VALUE_NUM_WORK_GROUPS:
1569 return nir_intrinsic_load_num_work_groups;
1570 case SYSTEM_VALUE_PRIMITIVE_ID:
1571 return nir_intrinsic_load_primitive_id;
1572 case SYSTEM_VALUE_TESS_COORD:
1573 return nir_intrinsic_load_tess_coord;
1574 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
1575 return nir_intrinsic_load_tess_level_outer;
1576 case SYSTEM_VALUE_TESS_LEVEL_INNER:
1577 return nir_intrinsic_load_tess_level_inner;
1578 case SYSTEM_VALUE_VERTICES_IN:
1579 return nir_intrinsic_load_patch_vertices_in;
1580 default:
1581 unreachable("system value does not directly correspond to intrinsic");
1582 }
1583 }
1584
1585 gl_system_value
1586 nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
1587 {
1588 switch (intrin) {
1589 case nir_intrinsic_load_vertex_id:
1590 return SYSTEM_VALUE_VERTEX_ID;
1591 case nir_intrinsic_load_instance_id:
1592 return SYSTEM_VALUE_INSTANCE_ID;
1593 case nir_intrinsic_load_vertex_id_zero_base:
1594 return SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1595 case nir_intrinsic_load_base_vertex:
1596 return SYSTEM_VALUE_BASE_VERTEX;
1597 case nir_intrinsic_load_invocation_id:
1598 return SYSTEM_VALUE_INVOCATION_ID;
1599 case nir_intrinsic_load_front_face:
1600 return SYSTEM_VALUE_FRONT_FACE;
1601 case nir_intrinsic_load_sample_id:
1602 return SYSTEM_VALUE_SAMPLE_ID;
1603 case nir_intrinsic_load_sample_pos:
1604 return SYSTEM_VALUE_SAMPLE_POS;
1605 case nir_intrinsic_load_sample_mask_in:
1606 return SYSTEM_VALUE_SAMPLE_MASK_IN;
1607 case nir_intrinsic_load_local_invocation_id:
1608 return SYSTEM_VALUE_LOCAL_INVOCATION_ID;
1609 case nir_intrinsic_load_num_work_groups:
1610 return SYSTEM_VALUE_NUM_WORK_GROUPS;
1611 case nir_intrinsic_load_work_group_id:
1612 return SYSTEM_VALUE_WORK_GROUP_ID;
1613 case nir_intrinsic_load_primitive_id:
1614 return SYSTEM_VALUE_PRIMITIVE_ID;
1615 case nir_intrinsic_load_tess_coord:
1616 return SYSTEM_VALUE_TESS_COORD;
1617 case nir_intrinsic_load_tess_level_outer:
1618 return SYSTEM_VALUE_TESS_LEVEL_OUTER;
1619 case nir_intrinsic_load_tess_level_inner:
1620 return SYSTEM_VALUE_TESS_LEVEL_INNER;
1621 case nir_intrinsic_load_patch_vertices_in:
1622 return SYSTEM_VALUE_VERTICES_IN;
1623 default:
1624 unreachable("intrinsic doesn't produce a system value");
1625 }
1626 }