nir: Move GS data to nir_shader_info
[mesa.git] / src / glsl / nir / nir.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Connor Abbott (cwabbott0@gmail.com)
25 *
26 */
27
28 #include "nir.h"
29 #include "nir_control_flow_private.h"
30 #include <assert.h>
31
32 nir_shader *
33 nir_shader_create(void *mem_ctx,
34 gl_shader_stage stage,
35 const nir_shader_compiler_options *options)
36 {
37 nir_shader *shader = ralloc(mem_ctx, nir_shader);
38
39 exec_list_make_empty(&shader->uniforms);
40 exec_list_make_empty(&shader->inputs);
41 exec_list_make_empty(&shader->outputs);
42
43 shader->options = options;
44 memset(&shader->info, 0, sizeof(shader->info));
45
46 exec_list_make_empty(&shader->functions);
47 exec_list_make_empty(&shader->registers);
48 exec_list_make_empty(&shader->globals);
49 exec_list_make_empty(&shader->system_values);
50 shader->reg_alloc = 0;
51
52 shader->num_inputs = 0;
53 shader->num_outputs = 0;
54 shader->num_uniforms = 0;
55
56 shader->stage = stage;
57
58 return shader;
59 }
60
61 static nir_register *
62 reg_create(void *mem_ctx, struct exec_list *list)
63 {
64 nir_register *reg = ralloc(mem_ctx, nir_register);
65
66 list_inithead(&reg->uses);
67 list_inithead(&reg->defs);
68 list_inithead(&reg->if_uses);
69
70 reg->num_components = 0;
71 reg->num_array_elems = 0;
72 reg->is_packed = false;
73 reg->name = NULL;
74
75 exec_list_push_tail(list, &reg->node);
76
77 return reg;
78 }
79
80 nir_register *
81 nir_global_reg_create(nir_shader *shader)
82 {
83 nir_register *reg = reg_create(shader, &shader->registers);
84 reg->index = shader->reg_alloc++;
85 reg->is_global = true;
86
87 return reg;
88 }
89
90 nir_register *
91 nir_local_reg_create(nir_function_impl *impl)
92 {
93 nir_register *reg = reg_create(ralloc_parent(impl), &impl->registers);
94 reg->index = impl->reg_alloc++;
95 reg->is_global = false;
96
97 return reg;
98 }
99
100 void
101 nir_reg_remove(nir_register *reg)
102 {
103 exec_node_remove(&reg->node);
104 }
105
106 nir_function *
107 nir_function_create(nir_shader *shader, const char *name)
108 {
109 nir_function *func = ralloc(shader, nir_function);
110
111 exec_list_push_tail(&shader->functions, &func->node);
112 exec_list_make_empty(&func->overload_list);
113 func->name = ralloc_strdup(func, name);
114 func->shader = shader;
115
116 return func;
117 }
118
119 nir_function_overload *
120 nir_function_overload_create(nir_function *func)
121 {
122 void *mem_ctx = ralloc_parent(func);
123
124 nir_function_overload *overload = ralloc(mem_ctx, nir_function_overload);
125
126 overload->num_params = 0;
127 overload->params = NULL;
128 overload->return_type = glsl_void_type();
129 overload->impl = NULL;
130
131 exec_list_push_tail(&func->overload_list, &overload->node);
132 overload->function = func;
133
134 return overload;
135 }
136
137 void nir_src_copy(nir_src *dest, const nir_src *src, void *mem_ctx)
138 {
139 dest->is_ssa = src->is_ssa;
140 if (src->is_ssa) {
141 dest->ssa = src->ssa;
142 } else {
143 dest->reg.base_offset = src->reg.base_offset;
144 dest->reg.reg = src->reg.reg;
145 if (src->reg.indirect) {
146 dest->reg.indirect = ralloc(mem_ctx, nir_src);
147 nir_src_copy(dest->reg.indirect, src->reg.indirect, mem_ctx);
148 } else {
149 dest->reg.indirect = NULL;
150 }
151 }
152 }
153
154 void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr)
155 {
156 /* Copying an SSA definition makes no sense whatsoever. */
157 assert(!src->is_ssa);
158
159 dest->is_ssa = false;
160
161 dest->reg.base_offset = src->reg.base_offset;
162 dest->reg.reg = src->reg.reg;
163 if (src->reg.indirect) {
164 dest->reg.indirect = ralloc(instr, nir_src);
165 nir_src_copy(dest->reg.indirect, src->reg.indirect, instr);
166 } else {
167 dest->reg.indirect = NULL;
168 }
169 }
170
171 void
172 nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
173 nir_alu_instr *instr)
174 {
175 nir_src_copy(&dest->src, &src->src, &instr->instr);
176 dest->abs = src->abs;
177 dest->negate = src->negate;
178 for (unsigned i = 0; i < 4; i++)
179 dest->swizzle[i] = src->swizzle[i];
180 }
181
182 void
183 nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
184 nir_alu_instr *instr)
185 {
186 nir_dest_copy(&dest->dest, &src->dest, &instr->instr);
187 dest->write_mask = src->write_mask;
188 dest->saturate = src->saturate;
189 }
190
191
192 static void
193 cf_init(nir_cf_node *node, nir_cf_node_type type)
194 {
195 exec_node_init(&node->node);
196 node->parent = NULL;
197 node->type = type;
198 }
199
200 nir_function_impl *
201 nir_function_impl_create(nir_function_overload *overload)
202 {
203 assert(overload->impl == NULL);
204
205 void *mem_ctx = ralloc_parent(overload);
206
207 nir_function_impl *impl = ralloc(mem_ctx, nir_function_impl);
208
209 overload->impl = impl;
210 impl->overload = overload;
211
212 cf_init(&impl->cf_node, nir_cf_node_function);
213
214 exec_list_make_empty(&impl->body);
215 exec_list_make_empty(&impl->registers);
216 exec_list_make_empty(&impl->locals);
217 impl->num_params = 0;
218 impl->params = NULL;
219 impl->return_var = NULL;
220 impl->reg_alloc = 0;
221 impl->ssa_alloc = 0;
222 impl->valid_metadata = nir_metadata_none;
223
224 /* create start & end blocks */
225 nir_block *start_block = nir_block_create(mem_ctx);
226 nir_block *end_block = nir_block_create(mem_ctx);
227 start_block->cf_node.parent = &impl->cf_node;
228 end_block->cf_node.parent = &impl->cf_node;
229 impl->end_block = end_block;
230
231 exec_list_push_tail(&impl->body, &start_block->cf_node.node);
232
233 start_block->successors[0] = end_block;
234 _mesa_set_add(end_block->predecessors, start_block);
235 return impl;
236 }
237
238 nir_block *
239 nir_block_create(void *mem_ctx)
240 {
241 nir_block *block = ralloc(mem_ctx, nir_block);
242
243 cf_init(&block->cf_node, nir_cf_node_block);
244
245 block->successors[0] = block->successors[1] = NULL;
246 block->predecessors = _mesa_set_create(block, _mesa_hash_pointer,
247 _mesa_key_pointer_equal);
248 block->imm_dom = NULL;
249 block->dom_frontier = _mesa_set_create(block, _mesa_hash_pointer,
250 _mesa_key_pointer_equal);
251
252 exec_list_make_empty(&block->instr_list);
253
254 return block;
255 }
256
257 static inline void
258 src_init(nir_src *src)
259 {
260 src->is_ssa = false;
261 src->reg.reg = NULL;
262 src->reg.indirect = NULL;
263 src->reg.base_offset = 0;
264 }
265
266 nir_if *
267 nir_if_create(void *mem_ctx)
268 {
269 nir_if *if_stmt = ralloc(mem_ctx, nir_if);
270
271 cf_init(&if_stmt->cf_node, nir_cf_node_if);
272 src_init(&if_stmt->condition);
273
274 nir_block *then = nir_block_create(mem_ctx);
275 exec_list_make_empty(&if_stmt->then_list);
276 exec_list_push_tail(&if_stmt->then_list, &then->cf_node.node);
277 then->cf_node.parent = &if_stmt->cf_node;
278
279 nir_block *else_stmt = nir_block_create(mem_ctx);
280 exec_list_make_empty(&if_stmt->else_list);
281 exec_list_push_tail(&if_stmt->else_list, &else_stmt->cf_node.node);
282 else_stmt->cf_node.parent = &if_stmt->cf_node;
283
284 return if_stmt;
285 }
286
287 nir_loop *
288 nir_loop_create(void *mem_ctx)
289 {
290 nir_loop *loop = ralloc(mem_ctx, nir_loop);
291
292 cf_init(&loop->cf_node, nir_cf_node_loop);
293
294 nir_block *body = nir_block_create(mem_ctx);
295 exec_list_make_empty(&loop->body);
296 exec_list_push_tail(&loop->body, &body->cf_node.node);
297 body->cf_node.parent = &loop->cf_node;
298
299 body->successors[0] = body;
300 _mesa_set_add(body->predecessors, body);
301
302 return loop;
303 }
304
305 static void
306 instr_init(nir_instr *instr, nir_instr_type type)
307 {
308 instr->type = type;
309 instr->block = NULL;
310 exec_node_init(&instr->node);
311 }
312
313 static void
314 dest_init(nir_dest *dest)
315 {
316 dest->is_ssa = false;
317 dest->reg.reg = NULL;
318 dest->reg.indirect = NULL;
319 dest->reg.base_offset = 0;
320 }
321
322 static void
323 alu_dest_init(nir_alu_dest *dest)
324 {
325 dest_init(&dest->dest);
326 dest->saturate = false;
327 dest->write_mask = 0xf;
328 }
329
330 static void
331 alu_src_init(nir_alu_src *src)
332 {
333 src_init(&src->src);
334 src->abs = src->negate = false;
335 src->swizzle[0] = 0;
336 src->swizzle[1] = 1;
337 src->swizzle[2] = 2;
338 src->swizzle[3] = 3;
339 }
340
341 nir_alu_instr *
342 nir_alu_instr_create(nir_shader *shader, nir_op op)
343 {
344 unsigned num_srcs = nir_op_infos[op].num_inputs;
345 nir_alu_instr *instr =
346 ralloc_size(shader,
347 sizeof(nir_alu_instr) + num_srcs * sizeof(nir_alu_src));
348
349 instr_init(&instr->instr, nir_instr_type_alu);
350 instr->op = op;
351 alu_dest_init(&instr->dest);
352 for (unsigned i = 0; i < num_srcs; i++)
353 alu_src_init(&instr->src[i]);
354
355 return instr;
356 }
357
358 nir_jump_instr *
359 nir_jump_instr_create(nir_shader *shader, nir_jump_type type)
360 {
361 nir_jump_instr *instr = ralloc(shader, nir_jump_instr);
362 instr_init(&instr->instr, nir_instr_type_jump);
363 instr->type = type;
364 return instr;
365 }
366
367 nir_load_const_instr *
368 nir_load_const_instr_create(nir_shader *shader, unsigned num_components)
369 {
370 nir_load_const_instr *instr = ralloc(shader, nir_load_const_instr);
371 instr_init(&instr->instr, nir_instr_type_load_const);
372
373 nir_ssa_def_init(&instr->instr, &instr->def, num_components, NULL);
374
375 return instr;
376 }
377
378 nir_intrinsic_instr *
379 nir_intrinsic_instr_create(nir_shader *shader, nir_intrinsic_op op)
380 {
381 unsigned num_srcs = nir_intrinsic_infos[op].num_srcs;
382 nir_intrinsic_instr *instr =
383 ralloc_size(shader,
384 sizeof(nir_intrinsic_instr) + num_srcs * sizeof(nir_src));
385
386 instr_init(&instr->instr, nir_instr_type_intrinsic);
387 instr->intrinsic = op;
388
389 if (nir_intrinsic_infos[op].has_dest)
390 dest_init(&instr->dest);
391
392 for (unsigned i = 0; i < num_srcs; i++)
393 src_init(&instr->src[i]);
394
395 return instr;
396 }
397
398 nir_call_instr *
399 nir_call_instr_create(nir_shader *shader, nir_function_overload *callee)
400 {
401 nir_call_instr *instr = ralloc(shader, nir_call_instr);
402 instr_init(&instr->instr, nir_instr_type_call);
403
404 instr->callee = callee;
405 instr->num_params = callee->num_params;
406 instr->params = ralloc_array(instr, nir_deref_var *, instr->num_params);
407 instr->return_deref = NULL;
408
409 return instr;
410 }
411
412 nir_tex_instr *
413 nir_tex_instr_create(nir_shader *shader, unsigned num_srcs)
414 {
415 nir_tex_instr *instr = rzalloc(shader, nir_tex_instr);
416 instr_init(&instr->instr, nir_instr_type_tex);
417
418 dest_init(&instr->dest);
419
420 instr->num_srcs = num_srcs;
421 instr->src = ralloc_array(instr, nir_tex_src, num_srcs);
422 for (unsigned i = 0; i < num_srcs; i++)
423 src_init(&instr->src[i].src);
424
425 instr->sampler_index = 0;
426 instr->sampler_array_size = 0;
427 instr->sampler = NULL;
428
429 return instr;
430 }
431
432 nir_phi_instr *
433 nir_phi_instr_create(nir_shader *shader)
434 {
435 nir_phi_instr *instr = ralloc(shader, nir_phi_instr);
436 instr_init(&instr->instr, nir_instr_type_phi);
437
438 dest_init(&instr->dest);
439 exec_list_make_empty(&instr->srcs);
440 return instr;
441 }
442
443 nir_parallel_copy_instr *
444 nir_parallel_copy_instr_create(nir_shader *shader)
445 {
446 nir_parallel_copy_instr *instr = ralloc(shader, nir_parallel_copy_instr);
447 instr_init(&instr->instr, nir_instr_type_parallel_copy);
448
449 exec_list_make_empty(&instr->entries);
450
451 return instr;
452 }
453
454 nir_ssa_undef_instr *
455 nir_ssa_undef_instr_create(nir_shader *shader, unsigned num_components)
456 {
457 nir_ssa_undef_instr *instr = ralloc(shader, nir_ssa_undef_instr);
458 instr_init(&instr->instr, nir_instr_type_ssa_undef);
459
460 nir_ssa_def_init(&instr->instr, &instr->def, num_components, NULL);
461
462 return instr;
463 }
464
465 nir_deref_var *
466 nir_deref_var_create(void *mem_ctx, nir_variable *var)
467 {
468 nir_deref_var *deref = ralloc(mem_ctx, nir_deref_var);
469 deref->deref.deref_type = nir_deref_type_var;
470 deref->deref.child = NULL;
471 deref->deref.type = var->type;
472 deref->var = var;
473 return deref;
474 }
475
476 nir_deref_array *
477 nir_deref_array_create(void *mem_ctx)
478 {
479 nir_deref_array *deref = ralloc(mem_ctx, nir_deref_array);
480 deref->deref.deref_type = nir_deref_type_array;
481 deref->deref.child = NULL;
482 deref->deref_array_type = nir_deref_array_type_direct;
483 src_init(&deref->indirect);
484 deref->base_offset = 0;
485 return deref;
486 }
487
488 nir_deref_struct *
489 nir_deref_struct_create(void *mem_ctx, unsigned field_index)
490 {
491 nir_deref_struct *deref = ralloc(mem_ctx, nir_deref_struct);
492 deref->deref.deref_type = nir_deref_type_struct;
493 deref->deref.child = NULL;
494 deref->index = field_index;
495 return deref;
496 }
497
498 static nir_deref_var *
499 copy_deref_var(void *mem_ctx, nir_deref_var *deref)
500 {
501 nir_deref_var *ret = nir_deref_var_create(mem_ctx, deref->var);
502 ret->deref.type = deref->deref.type;
503 if (deref->deref.child)
504 ret->deref.child = nir_copy_deref(ret, deref->deref.child);
505 return ret;
506 }
507
508 static nir_deref_array *
509 copy_deref_array(void *mem_ctx, nir_deref_array *deref)
510 {
511 nir_deref_array *ret = nir_deref_array_create(mem_ctx);
512 ret->base_offset = deref->base_offset;
513 ret->deref_array_type = deref->deref_array_type;
514 if (deref->deref_array_type == nir_deref_array_type_indirect) {
515 nir_src_copy(&ret->indirect, &deref->indirect, mem_ctx);
516 }
517 ret->deref.type = deref->deref.type;
518 if (deref->deref.child)
519 ret->deref.child = nir_copy_deref(ret, deref->deref.child);
520 return ret;
521 }
522
523 static nir_deref_struct *
524 copy_deref_struct(void *mem_ctx, nir_deref_struct *deref)
525 {
526 nir_deref_struct *ret = nir_deref_struct_create(mem_ctx, deref->index);
527 ret->deref.type = deref->deref.type;
528 if (deref->deref.child)
529 ret->deref.child = nir_copy_deref(ret, deref->deref.child);
530 return ret;
531 }
532
533 nir_deref *
534 nir_copy_deref(void *mem_ctx, nir_deref *deref)
535 {
536 switch (deref->deref_type) {
537 case nir_deref_type_var:
538 return &copy_deref_var(mem_ctx, nir_deref_as_var(deref))->deref;
539 case nir_deref_type_array:
540 return &copy_deref_array(mem_ctx, nir_deref_as_array(deref))->deref;
541 case nir_deref_type_struct:
542 return &copy_deref_struct(mem_ctx, nir_deref_as_struct(deref))->deref;
543 default:
544 unreachable("Invalid dereference type");
545 }
546
547 return NULL;
548 }
549
550 /* Returns a load_const instruction that represents the constant
551 * initializer for the given deref chain. The caller is responsible for
552 * ensuring that there actually is a constant initializer.
553 */
554 nir_load_const_instr *
555 nir_deref_get_const_initializer_load(nir_shader *shader, nir_deref_var *deref)
556 {
557 nir_constant *constant = deref->var->constant_initializer;
558 assert(constant);
559
560 const nir_deref *tail = &deref->deref;
561 unsigned matrix_offset = 0;
562 while (tail->child) {
563 switch (tail->child->deref_type) {
564 case nir_deref_type_array: {
565 nir_deref_array *arr = nir_deref_as_array(tail->child);
566 assert(arr->deref_array_type == nir_deref_array_type_direct);
567 if (glsl_type_is_matrix(tail->type)) {
568 assert(arr->deref.child == NULL);
569 matrix_offset = arr->base_offset;
570 } else {
571 constant = constant->elements[arr->base_offset];
572 }
573 break;
574 }
575
576 case nir_deref_type_struct: {
577 constant = constant->elements[nir_deref_as_struct(tail->child)->index];
578 break;
579 }
580
581 default:
582 unreachable("Invalid deref child type");
583 }
584
585 tail = tail->child;
586 }
587
588 nir_load_const_instr *load =
589 nir_load_const_instr_create(shader, glsl_get_vector_elements(tail->type));
590
591 matrix_offset *= load->def.num_components;
592 for (unsigned i = 0; i < load->def.num_components; i++) {
593 switch (glsl_get_base_type(tail->type)) {
594 case GLSL_TYPE_FLOAT:
595 case GLSL_TYPE_INT:
596 case GLSL_TYPE_UINT:
597 load->value.u[i] = constant->value.u[matrix_offset + i];
598 break;
599 case GLSL_TYPE_BOOL:
600 load->value.u[i] = constant->value.b[matrix_offset + i] ?
601 NIR_TRUE : NIR_FALSE;
602 break;
603 default:
604 unreachable("Invalid immediate type");
605 }
606 }
607
608 return load;
609 }
610
611 nir_function_impl *
612 nir_cf_node_get_function(nir_cf_node *node)
613 {
614 while (node->type != nir_cf_node_function) {
615 node = node->parent;
616 }
617
618 return nir_cf_node_as_function(node);
619 }
620
621 static bool
622 add_use_cb(nir_src *src, void *state)
623 {
624 nir_instr *instr = state;
625
626 src->parent_instr = instr;
627 list_addtail(&src->use_link,
628 src->is_ssa ? &src->ssa->uses : &src->reg.reg->uses);
629
630 return true;
631 }
632
633 static bool
634 add_ssa_def_cb(nir_ssa_def *def, void *state)
635 {
636 nir_instr *instr = state;
637
638 if (instr->block && def->index == UINT_MAX) {
639 nir_function_impl *impl =
640 nir_cf_node_get_function(&instr->block->cf_node);
641
642 def->index = impl->ssa_alloc++;
643 }
644
645 return true;
646 }
647
648 static bool
649 add_reg_def_cb(nir_dest *dest, void *state)
650 {
651 nir_instr *instr = state;
652
653 if (!dest->is_ssa) {
654 dest->reg.parent_instr = instr;
655 list_addtail(&dest->reg.def_link, &dest->reg.reg->defs);
656 }
657
658 return true;
659 }
660
661 static void
662 add_defs_uses(nir_instr *instr)
663 {
664 nir_foreach_src(instr, add_use_cb, instr);
665 nir_foreach_dest(instr, add_reg_def_cb, instr);
666 nir_foreach_ssa_def(instr, add_ssa_def_cb, instr);
667 }
668
669 void
670 nir_instr_insert(nir_cursor cursor, nir_instr *instr)
671 {
672 switch (cursor.option) {
673 case nir_cursor_before_block:
674 /* Only allow inserting jumps into empty blocks. */
675 if (instr->type == nir_instr_type_jump)
676 assert(exec_list_is_empty(&cursor.block->instr_list));
677
678 instr->block = cursor.block;
679 add_defs_uses(instr);
680 exec_list_push_head(&cursor.block->instr_list, &instr->node);
681 break;
682 case nir_cursor_after_block: {
683 /* Inserting instructions after a jump is illegal. */
684 nir_instr *last = nir_block_last_instr(cursor.block);
685 assert(last == NULL || last->type != nir_instr_type_jump);
686 (void) last;
687
688 instr->block = cursor.block;
689 add_defs_uses(instr);
690 exec_list_push_tail(&cursor.block->instr_list, &instr->node);
691 break;
692 }
693 case nir_cursor_before_instr:
694 assert(instr->type != nir_instr_type_jump);
695 instr->block = cursor.instr->block;
696 add_defs_uses(instr);
697 exec_node_insert_node_before(&cursor.instr->node, &instr->node);
698 break;
699 case nir_cursor_after_instr:
700 /* Inserting instructions after a jump is illegal. */
701 assert(cursor.instr->type != nir_instr_type_jump);
702
703 /* Only allow inserting jumps at the end of the block. */
704 if (instr->type == nir_instr_type_jump)
705 assert(cursor.instr == nir_block_last_instr(cursor.instr->block));
706
707 instr->block = cursor.instr->block;
708 add_defs_uses(instr);
709 exec_node_insert_after(&cursor.instr->node, &instr->node);
710 break;
711 }
712
713 if (instr->type == nir_instr_type_jump)
714 nir_handle_add_jump(instr->block);
715 }
716
717 static bool
718 src_is_valid(const nir_src *src)
719 {
720 return src->is_ssa ? (src->ssa != NULL) : (src->reg.reg != NULL);
721 }
722
723 static bool
724 remove_use_cb(nir_src *src, void *state)
725 {
726 if (src_is_valid(src))
727 list_del(&src->use_link);
728
729 return true;
730 }
731
732 static bool
733 remove_def_cb(nir_dest *dest, void *state)
734 {
735 if (!dest->is_ssa)
736 list_del(&dest->reg.def_link);
737
738 return true;
739 }
740
741 static void
742 remove_defs_uses(nir_instr *instr)
743 {
744 nir_foreach_dest(instr, remove_def_cb, instr);
745 nir_foreach_src(instr, remove_use_cb, instr);
746 }
747
748 void nir_instr_remove(nir_instr *instr)
749 {
750 remove_defs_uses(instr);
751 exec_node_remove(&instr->node);
752
753 if (instr->type == nir_instr_type_jump) {
754 nir_jump_instr *jump_instr = nir_instr_as_jump(instr);
755 nir_handle_remove_jump(instr->block, jump_instr->type);
756 }
757 }
758
759 /*@}*/
760
761 void
762 nir_index_local_regs(nir_function_impl *impl)
763 {
764 unsigned index = 0;
765 foreach_list_typed(nir_register, reg, node, &impl->registers) {
766 reg->index = index++;
767 }
768 impl->reg_alloc = index;
769 }
770
771 void
772 nir_index_global_regs(nir_shader *shader)
773 {
774 unsigned index = 0;
775 foreach_list_typed(nir_register, reg, node, &shader->registers) {
776 reg->index = index++;
777 }
778 shader->reg_alloc = index;
779 }
780
781 static bool
782 visit_alu_dest(nir_alu_instr *instr, nir_foreach_dest_cb cb, void *state)
783 {
784 return cb(&instr->dest.dest, state);
785 }
786
787 static bool
788 visit_intrinsic_dest(nir_intrinsic_instr *instr, nir_foreach_dest_cb cb,
789 void *state)
790 {
791 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
792 return cb(&instr->dest, state);
793
794 return true;
795 }
796
797 static bool
798 visit_texture_dest(nir_tex_instr *instr, nir_foreach_dest_cb cb,
799 void *state)
800 {
801 return cb(&instr->dest, state);
802 }
803
804 static bool
805 visit_phi_dest(nir_phi_instr *instr, nir_foreach_dest_cb cb, void *state)
806 {
807 return cb(&instr->dest, state);
808 }
809
810 static bool
811 visit_parallel_copy_dest(nir_parallel_copy_instr *instr,
812 nir_foreach_dest_cb cb, void *state)
813 {
814 nir_foreach_parallel_copy_entry(instr, entry) {
815 if (!cb(&entry->dest, state))
816 return false;
817 }
818
819 return true;
820 }
821
822 bool
823 nir_foreach_dest(nir_instr *instr, nir_foreach_dest_cb cb, void *state)
824 {
825 switch (instr->type) {
826 case nir_instr_type_alu:
827 return visit_alu_dest(nir_instr_as_alu(instr), cb, state);
828 case nir_instr_type_intrinsic:
829 return visit_intrinsic_dest(nir_instr_as_intrinsic(instr), cb, state);
830 case nir_instr_type_tex:
831 return visit_texture_dest(nir_instr_as_tex(instr), cb, state);
832 case nir_instr_type_phi:
833 return visit_phi_dest(nir_instr_as_phi(instr), cb, state);
834 case nir_instr_type_parallel_copy:
835 return visit_parallel_copy_dest(nir_instr_as_parallel_copy(instr),
836 cb, state);
837
838 case nir_instr_type_load_const:
839 case nir_instr_type_ssa_undef:
840 case nir_instr_type_call:
841 case nir_instr_type_jump:
842 break;
843
844 default:
845 unreachable("Invalid instruction type");
846 break;
847 }
848
849 return true;
850 }
851
852 struct foreach_ssa_def_state {
853 nir_foreach_ssa_def_cb cb;
854 void *client_state;
855 };
856
857 static inline bool
858 nir_ssa_def_visitor(nir_dest *dest, void *void_state)
859 {
860 struct foreach_ssa_def_state *state = void_state;
861
862 if (dest->is_ssa)
863 return state->cb(&dest->ssa, state->client_state);
864 else
865 return true;
866 }
867
868 bool
869 nir_foreach_ssa_def(nir_instr *instr, nir_foreach_ssa_def_cb cb, void *state)
870 {
871 switch (instr->type) {
872 case nir_instr_type_alu:
873 case nir_instr_type_tex:
874 case nir_instr_type_intrinsic:
875 case nir_instr_type_phi:
876 case nir_instr_type_parallel_copy: {
877 struct foreach_ssa_def_state foreach_state = {cb, state};
878 return nir_foreach_dest(instr, nir_ssa_def_visitor, &foreach_state);
879 }
880
881 case nir_instr_type_load_const:
882 return cb(&nir_instr_as_load_const(instr)->def, state);
883 case nir_instr_type_ssa_undef:
884 return cb(&nir_instr_as_ssa_undef(instr)->def, state);
885 case nir_instr_type_call:
886 case nir_instr_type_jump:
887 return true;
888 default:
889 unreachable("Invalid instruction type");
890 }
891 }
892
893 static bool
894 visit_src(nir_src *src, nir_foreach_src_cb cb, void *state)
895 {
896 if (!cb(src, state))
897 return false;
898 if (!src->is_ssa && src->reg.indirect)
899 return cb(src->reg.indirect, state);
900 return true;
901 }
902
903 static bool
904 visit_deref_array_src(nir_deref_array *deref, nir_foreach_src_cb cb,
905 void *state)
906 {
907 if (deref->deref_array_type == nir_deref_array_type_indirect)
908 return visit_src(&deref->indirect, cb, state);
909 return true;
910 }
911
912 static bool
913 visit_deref_src(nir_deref_var *deref, nir_foreach_src_cb cb, void *state)
914 {
915 nir_deref *cur = &deref->deref;
916 while (cur != NULL) {
917 if (cur->deref_type == nir_deref_type_array)
918 if (!visit_deref_array_src(nir_deref_as_array(cur), cb, state))
919 return false;
920
921 cur = cur->child;
922 }
923
924 return true;
925 }
926
927 static bool
928 visit_alu_src(nir_alu_instr *instr, nir_foreach_src_cb cb, void *state)
929 {
930 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
931 if (!visit_src(&instr->src[i].src, cb, state))
932 return false;
933
934 return true;
935 }
936
937 static bool
938 visit_tex_src(nir_tex_instr *instr, nir_foreach_src_cb cb, void *state)
939 {
940 for (unsigned i = 0; i < instr->num_srcs; i++)
941 if (!visit_src(&instr->src[i].src, cb, state))
942 return false;
943
944 if (instr->sampler != NULL)
945 if (!visit_deref_src(instr->sampler, cb, state))
946 return false;
947
948 return true;
949 }
950
951 static bool
952 visit_intrinsic_src(nir_intrinsic_instr *instr, nir_foreach_src_cb cb,
953 void *state)
954 {
955 unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs;
956 for (unsigned i = 0; i < num_srcs; i++)
957 if (!visit_src(&instr->src[i], cb, state))
958 return false;
959
960 unsigned num_vars =
961 nir_intrinsic_infos[instr->intrinsic].num_variables;
962 for (unsigned i = 0; i < num_vars; i++)
963 if (!visit_deref_src(instr->variables[i], cb, state))
964 return false;
965
966 return true;
967 }
968
969 static bool
970 visit_call_src(nir_call_instr *instr, nir_foreach_src_cb cb, void *state)
971 {
972 return true;
973 }
974
975 static bool
976 visit_load_const_src(nir_load_const_instr *instr, nir_foreach_src_cb cb,
977 void *state)
978 {
979 return true;
980 }
981
982 static bool
983 visit_phi_src(nir_phi_instr *instr, nir_foreach_src_cb cb, void *state)
984 {
985 nir_foreach_phi_src(instr, src) {
986 if (!visit_src(&src->src, cb, state))
987 return false;
988 }
989
990 return true;
991 }
992
993 static bool
994 visit_parallel_copy_src(nir_parallel_copy_instr *instr,
995 nir_foreach_src_cb cb, void *state)
996 {
997 nir_foreach_parallel_copy_entry(instr, entry) {
998 if (!visit_src(&entry->src, cb, state))
999 return false;
1000 }
1001
1002 return true;
1003 }
1004
1005 typedef struct {
1006 void *state;
1007 nir_foreach_src_cb cb;
1008 } visit_dest_indirect_state;
1009
1010 static bool
1011 visit_dest_indirect(nir_dest *dest, void *_state)
1012 {
1013 visit_dest_indirect_state *state = (visit_dest_indirect_state *) _state;
1014
1015 if (!dest->is_ssa && dest->reg.indirect)
1016 return state->cb(dest->reg.indirect, state->state);
1017
1018 return true;
1019 }
1020
1021 bool
1022 nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state)
1023 {
1024 switch (instr->type) {
1025 case nir_instr_type_alu:
1026 if (!visit_alu_src(nir_instr_as_alu(instr), cb, state))
1027 return false;
1028 break;
1029 case nir_instr_type_intrinsic:
1030 if (!visit_intrinsic_src(nir_instr_as_intrinsic(instr), cb, state))
1031 return false;
1032 break;
1033 case nir_instr_type_tex:
1034 if (!visit_tex_src(nir_instr_as_tex(instr), cb, state))
1035 return false;
1036 break;
1037 case nir_instr_type_call:
1038 if (!visit_call_src(nir_instr_as_call(instr), cb, state))
1039 return false;
1040 break;
1041 case nir_instr_type_load_const:
1042 if (!visit_load_const_src(nir_instr_as_load_const(instr), cb, state))
1043 return false;
1044 break;
1045 case nir_instr_type_phi:
1046 if (!visit_phi_src(nir_instr_as_phi(instr), cb, state))
1047 return false;
1048 break;
1049 case nir_instr_type_parallel_copy:
1050 if (!visit_parallel_copy_src(nir_instr_as_parallel_copy(instr),
1051 cb, state))
1052 return false;
1053 break;
1054 case nir_instr_type_jump:
1055 case nir_instr_type_ssa_undef:
1056 return true;
1057
1058 default:
1059 unreachable("Invalid instruction type");
1060 break;
1061 }
1062
1063 visit_dest_indirect_state dest_state;
1064 dest_state.state = state;
1065 dest_state.cb = cb;
1066 return nir_foreach_dest(instr, visit_dest_indirect, &dest_state);
1067 }
1068
1069 nir_const_value *
1070 nir_src_as_const_value(nir_src src)
1071 {
1072 if (!src.is_ssa)
1073 return NULL;
1074
1075 if (src.ssa->parent_instr->type != nir_instr_type_load_const)
1076 return NULL;
1077
1078 nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
1079
1080 return &load->value;
1081 }
1082
1083 bool
1084 nir_srcs_equal(nir_src src1, nir_src src2)
1085 {
1086 if (src1.is_ssa) {
1087 if (src2.is_ssa) {
1088 return src1.ssa == src2.ssa;
1089 } else {
1090 return false;
1091 }
1092 } else {
1093 if (src2.is_ssa) {
1094 return false;
1095 } else {
1096 if ((src1.reg.indirect == NULL) != (src2.reg.indirect == NULL))
1097 return false;
1098
1099 if (src1.reg.indirect) {
1100 if (!nir_srcs_equal(*src1.reg.indirect, *src2.reg.indirect))
1101 return false;
1102 }
1103
1104 return src1.reg.reg == src2.reg.reg &&
1105 src1.reg.base_offset == src2.reg.base_offset;
1106 }
1107 }
1108 }
1109
1110 static void
1111 src_remove_all_uses(nir_src *src)
1112 {
1113 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1114 if (!src_is_valid(src))
1115 continue;
1116
1117 list_del(&src->use_link);
1118 }
1119 }
1120
1121 static void
1122 src_add_all_uses(nir_src *src, nir_instr *parent_instr, nir_if *parent_if)
1123 {
1124 for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1125 if (!src_is_valid(src))
1126 continue;
1127
1128 if (parent_instr) {
1129 src->parent_instr = parent_instr;
1130 if (src->is_ssa)
1131 list_addtail(&src->use_link, &src->ssa->uses);
1132 else
1133 list_addtail(&src->use_link, &src->reg.reg->uses);
1134 } else {
1135 assert(parent_if);
1136 src->parent_if = parent_if;
1137 if (src->is_ssa)
1138 list_addtail(&src->use_link, &src->ssa->if_uses);
1139 else
1140 list_addtail(&src->use_link, &src->reg.reg->if_uses);
1141 }
1142 }
1143 }
1144
1145 void
1146 nir_instr_rewrite_src(nir_instr *instr, nir_src *src, nir_src new_src)
1147 {
1148 assert(!src_is_valid(src) || src->parent_instr == instr);
1149
1150 src_remove_all_uses(src);
1151 *src = new_src;
1152 src_add_all_uses(src, instr, NULL);
1153 }
1154
1155 void
1156 nir_instr_move_src(nir_instr *dest_instr, nir_src *dest, nir_src *src)
1157 {
1158 assert(!src_is_valid(dest) || dest->parent_instr == dest_instr);
1159
1160 src_remove_all_uses(dest);
1161 src_remove_all_uses(src);
1162 *dest = *src;
1163 *src = NIR_SRC_INIT;
1164 src_add_all_uses(dest, dest_instr, NULL);
1165 }
1166
1167 void
1168 nir_if_rewrite_condition(nir_if *if_stmt, nir_src new_src)
1169 {
1170 nir_src *src = &if_stmt->condition;
1171 assert(!src_is_valid(src) || src->parent_if == if_stmt);
1172
1173 src_remove_all_uses(src);
1174 *src = new_src;
1175 src_add_all_uses(src, NULL, if_stmt);
1176 }
1177
1178 void
1179 nir_instr_rewrite_dest(nir_instr *instr, nir_dest *dest, nir_dest new_dest)
1180 {
1181 if (dest->is_ssa) {
1182 /* We can only overwrite an SSA destination if it has no uses. */
1183 assert(list_empty(&dest->ssa.uses) && list_empty(&dest->ssa.if_uses));
1184 } else {
1185 list_del(&dest->reg.def_link);
1186 if (dest->reg.indirect)
1187 src_remove_all_uses(dest->reg.indirect);
1188 }
1189
1190 /* We can't re-write with an SSA def */
1191 assert(!new_dest.is_ssa);
1192
1193 nir_dest_copy(dest, &new_dest, instr);
1194
1195 dest->reg.parent_instr = instr;
1196 list_addtail(&dest->reg.def_link, &new_dest.reg.reg->defs);
1197
1198 if (dest->reg.indirect)
1199 src_add_all_uses(dest->reg.indirect, instr, NULL);
1200 }
1201
1202 void
1203 nir_ssa_def_init(nir_instr *instr, nir_ssa_def *def,
1204 unsigned num_components, const char *name)
1205 {
1206 def->name = name;
1207 def->parent_instr = instr;
1208 list_inithead(&def->uses);
1209 list_inithead(&def->if_uses);
1210 def->num_components = num_components;
1211
1212 if (instr->block) {
1213 nir_function_impl *impl =
1214 nir_cf_node_get_function(&instr->block->cf_node);
1215
1216 def->index = impl->ssa_alloc++;
1217 } else {
1218 def->index = UINT_MAX;
1219 }
1220 }
1221
1222 void
1223 nir_ssa_dest_init(nir_instr *instr, nir_dest *dest,
1224 unsigned num_components, const char *name)
1225 {
1226 dest->is_ssa = true;
1227 nir_ssa_def_init(instr, &dest->ssa, num_components, name);
1228 }
1229
1230 void
1231 nir_ssa_def_rewrite_uses(nir_ssa_def *def, nir_src new_src)
1232 {
1233 assert(!new_src.is_ssa || def != new_src.ssa);
1234
1235 nir_foreach_use_safe(def, use_src) {
1236 nir_instr *src_parent_instr = use_src->parent_instr;
1237 list_del(&use_src->use_link);
1238 nir_src_copy(use_src, &new_src, src_parent_instr);
1239 src_add_all_uses(use_src, src_parent_instr, NULL);
1240 }
1241
1242 nir_foreach_if_use_safe(def, use_src) {
1243 nir_if *src_parent_if = use_src->parent_if;
1244 list_del(&use_src->use_link);
1245 nir_src_copy(use_src, &new_src, src_parent_if);
1246 src_add_all_uses(use_src, NULL, src_parent_if);
1247 }
1248 }
1249
1250
1251 static bool foreach_cf_node(nir_cf_node *node, nir_foreach_block_cb cb,
1252 bool reverse, void *state);
1253
1254 static inline bool
1255 foreach_if(nir_if *if_stmt, nir_foreach_block_cb cb, bool reverse, void *state)
1256 {
1257 if (reverse) {
1258 foreach_list_typed_safe_reverse(nir_cf_node, node, node,
1259 &if_stmt->else_list) {
1260 if (!foreach_cf_node(node, cb, reverse, state))
1261 return false;
1262 }
1263
1264 foreach_list_typed_safe_reverse(nir_cf_node, node, node,
1265 &if_stmt->then_list) {
1266 if (!foreach_cf_node(node, cb, reverse, state))
1267 return false;
1268 }
1269 } else {
1270 foreach_list_typed_safe(nir_cf_node, node, node, &if_stmt->then_list) {
1271 if (!foreach_cf_node(node, cb, reverse, state))
1272 return false;
1273 }
1274
1275 foreach_list_typed_safe(nir_cf_node, node, node, &if_stmt->else_list) {
1276 if (!foreach_cf_node(node, cb, reverse, state))
1277 return false;
1278 }
1279 }
1280
1281 return true;
1282 }
1283
1284 static inline bool
1285 foreach_loop(nir_loop *loop, nir_foreach_block_cb cb, bool reverse, void *state)
1286 {
1287 if (reverse) {
1288 foreach_list_typed_safe_reverse(nir_cf_node, node, node, &loop->body) {
1289 if (!foreach_cf_node(node, cb, reverse, state))
1290 return false;
1291 }
1292 } else {
1293 foreach_list_typed_safe(nir_cf_node, node, node, &loop->body) {
1294 if (!foreach_cf_node(node, cb, reverse, state))
1295 return false;
1296 }
1297 }
1298
1299 return true;
1300 }
1301
1302 static bool
1303 foreach_cf_node(nir_cf_node *node, nir_foreach_block_cb cb,
1304 bool reverse, void *state)
1305 {
1306 switch (node->type) {
1307 case nir_cf_node_block:
1308 return cb(nir_cf_node_as_block(node), state);
1309 case nir_cf_node_if:
1310 return foreach_if(nir_cf_node_as_if(node), cb, reverse, state);
1311 case nir_cf_node_loop:
1312 return foreach_loop(nir_cf_node_as_loop(node), cb, reverse, state);
1313 break;
1314
1315 default:
1316 unreachable("Invalid CFG node type");
1317 break;
1318 }
1319
1320 return false;
1321 }
1322
1323 bool
1324 nir_foreach_block_in_cf_node(nir_cf_node *node, nir_foreach_block_cb cb,
1325 void *state)
1326 {
1327 return foreach_cf_node(node, cb, false, state);
1328 }
1329
1330 bool
1331 nir_foreach_block(nir_function_impl *impl, nir_foreach_block_cb cb, void *state)
1332 {
1333 foreach_list_typed_safe(nir_cf_node, node, node, &impl->body) {
1334 if (!foreach_cf_node(node, cb, false, state))
1335 return false;
1336 }
1337
1338 return cb(impl->end_block, state);
1339 }
1340
1341 bool
1342 nir_foreach_block_reverse(nir_function_impl *impl, nir_foreach_block_cb cb,
1343 void *state)
1344 {
1345 if (!cb(impl->end_block, state))
1346 return false;
1347
1348 foreach_list_typed_safe_reverse(nir_cf_node, node, node, &impl->body) {
1349 if (!foreach_cf_node(node, cb, true, state))
1350 return false;
1351 }
1352
1353 return true;
1354 }
1355
1356 nir_if *
1357 nir_block_get_following_if(nir_block *block)
1358 {
1359 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1360 return NULL;
1361
1362 if (nir_cf_node_is_last(&block->cf_node))
1363 return NULL;
1364
1365 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1366
1367 if (next_node->type != nir_cf_node_if)
1368 return NULL;
1369
1370 return nir_cf_node_as_if(next_node);
1371 }
1372
1373 nir_loop *
1374 nir_block_get_following_loop(nir_block *block)
1375 {
1376 if (exec_node_is_tail_sentinel(&block->cf_node.node))
1377 return NULL;
1378
1379 if (nir_cf_node_is_last(&block->cf_node))
1380 return NULL;
1381
1382 nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1383
1384 if (next_node->type != nir_cf_node_loop)
1385 return NULL;
1386
1387 return nir_cf_node_as_loop(next_node);
1388 }
1389 static bool
1390 index_block(nir_block *block, void *state)
1391 {
1392 unsigned *index = state;
1393 block->index = (*index)++;
1394 return true;
1395 }
1396
1397 void
1398 nir_index_blocks(nir_function_impl *impl)
1399 {
1400 unsigned index = 0;
1401
1402 if (impl->valid_metadata & nir_metadata_block_index)
1403 return;
1404
1405 nir_foreach_block(impl, index_block, &index);
1406
1407 impl->num_blocks = index;
1408 }
1409
1410 static bool
1411 index_ssa_def_cb(nir_ssa_def *def, void *state)
1412 {
1413 unsigned *index = (unsigned *) state;
1414 def->index = (*index)++;
1415
1416 return true;
1417 }
1418
1419 static bool
1420 index_ssa_block(nir_block *block, void *state)
1421 {
1422 nir_foreach_instr(block, instr)
1423 nir_foreach_ssa_def(instr, index_ssa_def_cb, state);
1424
1425 return true;
1426 }
1427
1428 /**
1429 * The indices are applied top-to-bottom which has the very nice property
1430 * that, if A dominates B, then A->index <= B->index.
1431 */
1432 void
1433 nir_index_ssa_defs(nir_function_impl *impl)
1434 {
1435 unsigned index = 0;
1436 nir_foreach_block(impl, index_ssa_block, &index);
1437 impl->ssa_alloc = index;
1438 }
1439
1440 static bool
1441 index_instrs_block(nir_block *block, void *state)
1442 {
1443 unsigned *index = state;
1444 nir_foreach_instr(block, instr)
1445 instr->index = (*index)++;
1446
1447 return true;
1448 }
1449
1450 /**
1451 * The indices are applied top-to-bottom which has the very nice property
1452 * that, if A dominates B, then A->index <= B->index.
1453 */
1454 unsigned
1455 nir_index_instrs(nir_function_impl *impl)
1456 {
1457 unsigned index = 0;
1458 nir_foreach_block(impl, index_instrs_block, &index);
1459 return index;
1460 }
1461
1462 nir_intrinsic_op
1463 nir_intrinsic_from_system_value(gl_system_value val)
1464 {
1465 switch (val) {
1466 case SYSTEM_VALUE_VERTEX_ID:
1467 return nir_intrinsic_load_vertex_id;
1468 case SYSTEM_VALUE_INSTANCE_ID:
1469 return nir_intrinsic_load_instance_id;
1470 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
1471 return nir_intrinsic_load_vertex_id_zero_base;
1472 case SYSTEM_VALUE_BASE_VERTEX:
1473 return nir_intrinsic_load_base_vertex;
1474 case SYSTEM_VALUE_INVOCATION_ID:
1475 return nir_intrinsic_load_invocation_id;
1476 case SYSTEM_VALUE_FRONT_FACE:
1477 return nir_intrinsic_load_front_face;
1478 case SYSTEM_VALUE_SAMPLE_ID:
1479 return nir_intrinsic_load_sample_id;
1480 case SYSTEM_VALUE_SAMPLE_POS:
1481 return nir_intrinsic_load_sample_pos;
1482 case SYSTEM_VALUE_SAMPLE_MASK_IN:
1483 return nir_intrinsic_load_sample_mask_in;
1484 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
1485 return nir_intrinsic_load_local_invocation_id;
1486 case SYSTEM_VALUE_WORK_GROUP_ID:
1487 return nir_intrinsic_load_work_group_id;
1488 case SYSTEM_VALUE_NUM_WORK_GROUPS:
1489 return nir_intrinsic_load_num_work_groups;
1490 case SYSTEM_VALUE_PRIMITIVE_ID:
1491 return nir_intrinsic_load_primitive_id;
1492 /* FINISHME: Add tessellation intrinsics.
1493 case SYSTEM_VALUE_TESS_COORD:
1494 case SYSTEM_VALUE_VERTICES_IN:
1495 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
1496 case SYSTEM_VALUE_TESS_LEVEL_INNER:
1497 */
1498 default:
1499 unreachable("system value does not directly correspond to intrinsic");
1500 }
1501 }
1502
1503 gl_system_value
1504 nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
1505 {
1506 switch (intrin) {
1507 case nir_intrinsic_load_vertex_id:
1508 return SYSTEM_VALUE_VERTEX_ID;
1509 case nir_intrinsic_load_instance_id:
1510 return SYSTEM_VALUE_INSTANCE_ID;
1511 case nir_intrinsic_load_vertex_id_zero_base:
1512 return SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1513 case nir_intrinsic_load_base_vertex:
1514 return SYSTEM_VALUE_BASE_VERTEX;
1515 case nir_intrinsic_load_invocation_id:
1516 return SYSTEM_VALUE_INVOCATION_ID;
1517 case nir_intrinsic_load_front_face:
1518 return SYSTEM_VALUE_FRONT_FACE;
1519 case nir_intrinsic_load_sample_id:
1520 return SYSTEM_VALUE_SAMPLE_ID;
1521 case nir_intrinsic_load_sample_pos:
1522 return SYSTEM_VALUE_SAMPLE_POS;
1523 case nir_intrinsic_load_sample_mask_in:
1524 return SYSTEM_VALUE_SAMPLE_MASK_IN;
1525 case nir_intrinsic_load_local_invocation_id:
1526 return SYSTEM_VALUE_LOCAL_INVOCATION_ID;
1527 case nir_intrinsic_load_num_work_groups:
1528 return SYSTEM_VALUE_NUM_WORK_GROUPS;
1529 case nir_intrinsic_load_work_group_id:
1530 return SYSTEM_VALUE_WORK_GROUP_ID;
1531 case nir_intrinsic_load_primitive_id:
1532 return SYSTEM_VALUE_PRIMITIVE_ID;
1533 /* FINISHME: Add tessellation intrinsics.
1534 return SYSTEM_VALUE_TESS_COORD;
1535 return SYSTEM_VALUE_VERTICES_IN;
1536 return SYSTEM_VALUE_PRIMITIVE_ID;
1537 return SYSTEM_VALUE_TESS_LEVEL_OUTER;
1538 return SYSTEM_VALUE_TESS_LEVEL_INNER;
1539 */
1540 default:
1541 unreachable("intrinsic doesn't produce a system value");
1542 }
1543 }