src/glsl/nir/nir_intrinsics.h

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Connor Abbott (cwabbott0@gmail.com)
  25  *
  26  */
  27
  28 /**
  29  * This header file defines all the available intrinsics in one place. It
  30  * expands to a list of macros of the form:
  31  *
  32  * INTRINSIC(name, num_srcs, src_components, has_dest, dest_components,
  33  *              num_variables, num_indices, flags)
  34  *
  35  * Which should correspond one-to-one with the nir_intrinsic_info structure. It
  36  * is included in both ir.h to create the nir_intrinsic enum (with members of
  37  * the form nir_intrinsic_(name)) and and in opcodes.c to create
  38  * nir_intrinsic_infos, which is a const array of nir_intrinsic_info structures
  39  * for each intrinsic.
  40  */
  41
  42 #define ARR(...) { __VA_ARGS__ }
  43
  44
  45 INTRINSIC(load_var_vec1,   0, ARR(), true, 1, 1, 0,
  46           NIR_INTRINSIC_CAN_ELIMINATE)
  47 INTRINSIC(load_var_vec2,   0, ARR(), true, 2, 1, 0,
  48           NIR_INTRINSIC_CAN_ELIMINATE)
  49 INTRINSIC(load_var_vec3,   0, ARR(), true, 3, 1, 0,
  50           NIR_INTRINSIC_CAN_ELIMINATE)
  51 INTRINSIC(load_var_vec4,   0, ARR(), true, 4, 1, 0,
  52           NIR_INTRINSIC_CAN_ELIMINATE)
  53 INTRINSIC(store_var_vec1, 1, ARR(1), false, 0, 1, 0, 0)
  54 INTRINSIC(store_var_vec2, 1, ARR(2), false, 0, 1, 0, 0)
  55 INTRINSIC(store_var_vec3, 1, ARR(3), false, 0, 1, 0, 0)
  56 INTRINSIC(store_var_vec4, 1, ARR(4), false, 0, 1, 0, 0)
  57 INTRINSIC(copy_var,       0, ARR(),  false, 0, 2, 0, 0)
  58
  59 /*
  60  * a barrier is an intrinsic with no inputs/outputs but which can't be moved
  61  * around/optimized in general
  62  */
  63 #define BARRIER(name) INTRINSIC(name, 0, ARR(), false, 0, 0, 0, 0)
  64
  65 BARRIER(discard)
  66
  67 INTRINSIC(emit_vertex,   0, ARR(), false, 0, 0, 1, 0)
  68 INTRINSIC(end_primitive, 0, ARR(), false, 0, 0, 1, 0)
  69
  70 /*
  71  * Atomic counters
  72  *
  73  * The *_var variants take an atomic_uint nir_variable, while the other,
  74  * lowered, variants take a constant buffer index and register offset.
  75  */
  76
  77 #define ATOMIC(name, flags) \
  78    INTRINSIC(atomic_counter_##name##_var, 0, ARR(), true, 1, 1, 0, flags) \
  79    INTRINSIC(atomic_counter_##name, 1, ARR(1), true, 1, 0, 1, flags)
  80
  81 ATOMIC(inc, 0)
  82 ATOMIC(dec, 0)
  83 ATOMIC(read, NIR_INTRINSIC_CAN_ELIMINATE)
  84
  85 #define SYSTEM_VALUE(name, components) \
  86    INTRINSIC(load_##name, 0, ARR(), true, components, 0, 0, \
  87    NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
  88
  89 SYSTEM_VALUE(front_face, 1)
  90 SYSTEM_VALUE(vertex_id, 1)
  91 SYSTEM_VALUE(instance_id, 1)
  92 SYSTEM_VALUE(sample_id, 1)
  93 SYSTEM_VALUE(sample_pos, 2)
  94 SYSTEM_VALUE(sample_mask_in, 1)
  95 SYSTEM_VALUE(invocation_id, 1)
  96
  97 #define LOAD(name, num_indices, flags) \
  98    INTRINSIC(load_##name##_vec1, 0, ARR(), true, 1, 0, num_indices, \
  99              NIR_INTRINSIC_CAN_ELIMINATE | flags) \
 100    INTRINSIC(load_##name##_vec2, 0, ARR(), true, 2, 0, num_indices, \
 101              NIR_INTRINSIC_CAN_ELIMINATE | flags) \
 102    INTRINSIC(load_##name##_vec3, 0, ARR(), true, 3, 0, num_indices, \
 103              NIR_INTRINSIC_CAN_ELIMINATE | flags) \
 104    INTRINSIC(load_##name##_vec4, 0, ARR(), true, 4, 0, num_indices, \
 105              NIR_INTRINSIC_CAN_ELIMINATE | flags) \
 106    INTRINSIC(load_##name##_vec1_indirect, 1, ARR(1), true, 1, 0, num_indices, \
 107              NIR_INTRINSIC_CAN_ELIMINATE | flags) \
 108    INTRINSIC(load_##name##_vec2_indirect, 1, ARR(1), true, 2, 0, num_indices, \
 109              NIR_INTRINSIC_CAN_ELIMINATE | flags) \
 110    INTRINSIC(load_##name##_vec3_indirect, 1, ARR(1), true, 3, 0, num_indices, \
 111              NIR_INTRINSIC_CAN_ELIMINATE | flags) \
 112    INTRINSIC(load_##name##_vec4_indirect, 1, ARR(1), true, 4, 0, num_indices, \
 113              NIR_INTRINSIC_CAN_ELIMINATE | flags) \
 114
 115
 116 /*
 117  * The first index is the address to load from, and the second index is the
 118  * number of array elements to load. For UBO's (and SSBO's), the first index
 119  * is the UBO buffer index (TODO nonconstant UBO buffer index) and the second
 120  * and third indices play the role of the first and second indices in the other
 121  * loads. Indirect loads have an additional register input, which is added
 122  * to the constant address to compute the final address to load from.
 123  *
 124  * For vector backends, the address is in terms of one vec4, and so each array
 125  * element is +4 scalar components from the previous array element. For scalar
 126  * backends, the address is in terms of a single 4-byte float/int and arrays
 127  * elements begin immediately after the previous array element.
 128  */
 129
 130 LOAD(uniform, 2, NIR_INTRINSIC_CAN_REORDER)
 131 LOAD(ubo, 3, NIR_INTRINSIC_CAN_REORDER)
 132 LOAD(input, 2, NIR_INTRINSIC_CAN_REORDER)
 133 /* LOAD(ssbo, 2, 0) */
 134
 135 #define STORE(name, num_indices, flags) \
 136    INTRINSIC(store_##name##_vec1, 1, ARR(1), false, 0, 0, num_indices, flags) \
 137    INTRINSIC(store_##name##_vec2, 1, ARR(2), false, 0, 0, num_indices, flags) \
 138    INTRINSIC(store_##name##_vec3, 1, ARR(3), false, 0, 0, num_indices, flags) \
 139    INTRINSIC(store_##name##_vec4, 1, ARR(4), false, 0, 0, num_indices, flags) \
 140    INTRINSIC(store_##name##_vec1_indirect, 2, ARR(1, 1), false, 0, 0, \
 141              num_indices, flags) \
 142    INTRINSIC(store_##name##_vec2_indirect, 2, ARR(2, 1), false, 0, 0, \
 143              num_indices, flags) \
 144    INTRINSIC(store_##name##_vec3_indirect, 2, ARR(3, 1), false, 0, 0, \
 145              num_indices, flags) \
 146    INTRINSIC(store_##name##_vec4_indirect, 2, ARR(4, 1), false, 0, 0, \
 147              num_indices, flags) \
 148
 149 /*
 150  * Stores work the same way as loads, except now the first register input is
 151  * the value or array to store and the optional second input is the indirect
 152  * offset.
 153  */
 154
 155 STORE(output, 2, 0)
 156 /* STORE(ssbo, 3, 0) */
 157
 158 LAST_INTRINSIC(store_output_vec4_indirect)