2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Connor Abbott (cwabbott0@gmail.com)
29 * This header file defines all the available intrinsics in one place. It
30 * expands to a list of macros of the form:
32 * INTRINSIC(name, num_srcs, src_components, has_dest, dest_components,
33 * num_variables, num_indices, flags)
35 * Which should correspond one-to-one with the nir_intrinsic_info structure. It
36 * is included in both ir.h to create the nir_intrinsic enum (with members of
37 * the form nir_intrinsic_(name)) and and in opcodes.c to create
38 * nir_intrinsic_infos, which is a const array of nir_intrinsic_info structures
42 #define ARR(...) { __VA_ARGS__ }
45 INTRINSIC(load_var
, 0, ARR(), true, 0, 1, 0, NIR_INTRINSIC_CAN_ELIMINATE
)
46 INTRINSIC(store_var
, 1, ARR(0), false, 0, 1, 0, 0)
47 INTRINSIC(copy_var
, 0, ARR(), false, 0, 2, 0, 0)
50 * Interpolation of input. The interp_var_at* intrinsics are similar to the
51 * load_var intrinsic acting an a shader input except that they interpolate
52 * the input differently. The at_sample and at_offset intrinsics take an
53 * aditional source that is a integer sample id or a vec2 position offset
57 INTRINSIC(interp_var_at_centroid
, 0, ARR(0), true, 0, 1, 0,
58 NIR_INTRINSIC_CAN_ELIMINATE
| NIR_INTRINSIC_CAN_REORDER
)
59 INTRINSIC(interp_var_at_sample
, 1, ARR(1), true, 0, 1, 0,
60 NIR_INTRINSIC_CAN_ELIMINATE
| NIR_INTRINSIC_CAN_REORDER
)
61 INTRINSIC(interp_var_at_offset
, 1, ARR(2), true, 0, 1, 0,
62 NIR_INTRINSIC_CAN_ELIMINATE
| NIR_INTRINSIC_CAN_REORDER
)
65 * a barrier is an intrinsic with no inputs/outputs but which can't be moved
66 * around/optimized in general
68 #define BARRIER(name) INTRINSIC(name, 0, ARR(), false, 0, 0, 0, 0)
72 INTRINSIC(emit_vertex
, 0, ARR(), false, 0, 0, 1, 0)
73 INTRINSIC(end_primitive
, 0, ARR(), false, 0, 0, 1, 0)
78 * The *_var variants take an atomic_uint nir_variable, while the other,
79 * lowered, variants take a constant buffer index and register offset.
82 #define ATOMIC(name, flags) \
83 INTRINSIC(atomic_counter_##name##_var, 0, ARR(), true, 1, 1, 0, flags) \
84 INTRINSIC(atomic_counter_##name, 1, ARR(1), true, 1, 0, 1, flags)
88 ATOMIC(read
, NIR_INTRINSIC_CAN_ELIMINATE
)
90 #define SYSTEM_VALUE(name, components) \
91 INTRINSIC(load_##name, 0, ARR(), true, components, 0, 0, \
92 NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
94 SYSTEM_VALUE(front_face
, 1)
95 SYSTEM_VALUE(vertex_id
, 1)
96 SYSTEM_VALUE(instance_id
, 1)
97 SYSTEM_VALUE(sample_id
, 1)
98 SYSTEM_VALUE(sample_pos
, 2)
99 SYSTEM_VALUE(sample_mask_in
, 1)
100 SYSTEM_VALUE(invocation_id
, 1)
103 * The first index is the address to load from, and the second index is the
104 * number of array elements to load. For UBO's (and SSBO's), the first index
105 * is the UBO buffer index (TODO nonconstant UBO buffer index) and the second
106 * and third indices play the role of the first and second indices in the other
107 * loads. Indirect loads have an additional register input, which is added
108 * to the constant address to compute the final address to load from.
110 * For vector backends, the address is in terms of one vec4, and so each array
111 * element is +4 scalar components from the previous array element. For scalar
112 * backends, the address is in terms of a single 4-byte float/int and arrays
113 * elements begin immediately after the previous array element.
116 #define LOAD(name, num_indices, flags) \
117 INTRINSIC(load_##name, 0, ARR(), true, 0, 0, num_indices, \
118 NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) \
119 INTRINSIC(load_##name##_indirect, 1, ARR(1), true, 0, 0, num_indices, \
120 NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) \
122 LOAD(uniform, 2, NIR_INTRINSIC_CAN_REORDER)
123 LOAD(ubo
, 3, NIR_INTRINSIC_CAN_REORDER
)
124 LOAD(input
, 2, NIR_INTRINSIC_CAN_REORDER
)
125 /* LOAD(ssbo, 2, 0) */
128 * Stores work the same way as loads, except now the first register input is
129 * the value or array to store and the optional second input is the indirect
133 #define STORE(name, num_indices, flags) \
134 INTRINSIC(store_##name, 1, ARR(0), false, 0, 0, num_indices, flags) \
135 INTRINSIC(store_##name##_indirect, 2, ARR(0, 1), false, 0, 0, \
136 num_indices, flags) \
139 /* STORE(ssbo, 3, 0) */
141 LAST_INTRINSIC(store_output_indirect
)