src/glsl/nir/nir_opt_cse.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Jason Ekstrand (jason@jlekstrand.net)
  25  *
  26  */
  27
  28 #include "nir.h"
  29
  30 /*
  31  * Implements common subexpression elimination
  32  */
  33
  34 struct cse_state {
  35    void *mem_ctx;
  36    bool progress;
  37 };
  38
  39 static bool
  40 nir_alu_srcs_equal(nir_alu_src src1, nir_alu_src src2, uint8_t read_mask)
  41 {
  42    if (src1.abs != src2.abs || src1.negate != src2.negate)
  43       return false;
  44
  45    for (int i = 0; i < 4; ++i) {
  46       if (!(read_mask & (1 << i)))
  47          continue;
  48
  49       if (src1.swizzle[i] != src2.swizzle[i])
  50          return false;
  51    }
  52
  53    return nir_srcs_equal(src1.src, src2.src);
  54 }
  55
  56 static bool
  57 nir_instrs_equal(nir_instr *instr1, nir_instr *instr2)
  58 {
  59    if (instr1->type != instr2->type)
  60       return false;
  61
  62    switch (instr1->type) {
  63    case nir_instr_type_alu: {
  64       nir_alu_instr *alu1 = nir_instr_as_alu(instr1);
  65       nir_alu_instr *alu2 = nir_instr_as_alu(instr2);
  66
  67       if (alu1->op != alu2->op)
  68          return false;
  69
  70       /* TODO: We can probably acutally do something more inteligent such
  71        * as allowing different numbers and taking a maximum or something
  72        * here */
  73       if (alu1->dest.dest.ssa.num_components != alu2->dest.dest.ssa.num_components)
  74          return false;
  75
  76       for (unsigned i = 0; i < nir_op_infos[alu1->op].num_inputs; i++) {
  77          if (!nir_alu_srcs_equal(alu1->src[i], alu2->src[i],
  78                                  (1 << alu1->dest.dest.ssa.num_components) - 1))
  79             return false;
  80       }
  81       return true;
  82    }
  83    case nir_instr_type_tex:
  84       return false;
  85    case nir_instr_type_load_const: {
  86       nir_load_const_instr *load1 = nir_instr_as_load_const(instr1);
  87       nir_load_const_instr *load2 = nir_instr_as_load_const(instr2);
  88
  89       if (load1->def.num_components != load2->def.num_components)
  90          return false;
  91
  92       return memcmp(load1->value.f, load2->value.f,
  93                     load1->def.num_components * sizeof(*load2->value.f)) == 0;
  94    }
  95    case nir_instr_type_phi: {
  96       nir_phi_instr *phi1 = nir_instr_as_phi(instr1);
  97       nir_phi_instr *phi2 = nir_instr_as_phi(instr2);
  98
  99       if (phi1->instr.block != phi2->instr.block)
 100          return false;
 101
 102       nir_foreach_phi_src(phi1, src1) {
 103          nir_foreach_phi_src(phi2, src2) {
 104             if (src1->pred == src2->pred) {
 105                if (!nir_srcs_equal(src1->src, src2->src))
 106                   return false;
 107
 108                break;
 109             }
 110          }
 111       }
 112
 113       return true;
 114    }
 115    case nir_instr_type_intrinsic: {
 116       nir_intrinsic_instr *intrinsic1 = nir_instr_as_intrinsic(instr1);
 117       nir_intrinsic_instr *intrinsic2 = nir_instr_as_intrinsic(instr2);
 118       const nir_intrinsic_info *info =
 119          &nir_intrinsic_infos[intrinsic1->intrinsic];
 120
 121       if (intrinsic1->intrinsic != intrinsic2->intrinsic ||
 122           intrinsic1->num_components != intrinsic2->num_components)
 123          return false;
 124
 125       if (info->has_dest && intrinsic1->dest.ssa.num_components !=
 126                             intrinsic2->dest.ssa.num_components)
 127          return false;
 128
 129       for (unsigned i = 0; i < info->num_srcs; i++) {
 130          if (!nir_srcs_equal(intrinsic1->src[i], intrinsic2->src[i]))
 131             return false;
 132       }
 133
 134       assert(info->num_variables == 0);
 135
 136       for (unsigned i = 0; i < info->num_indices; i++) {
 137          if (intrinsic1->const_index[i] != intrinsic2->const_index[i])
 138             return false;
 139       }
 140
 141       return true;
 142    }
 143    case nir_instr_type_call:
 144    case nir_instr_type_jump:
 145    case nir_instr_type_ssa_undef:
 146    case nir_instr_type_parallel_copy:
 147    default:
 148       unreachable("Invalid instruction type");
 149    }
 150
 151    return false;
 152 }
 153
 154 static bool
 155 src_is_ssa(nir_src *src, void *data)
 156 {
 157    return src->is_ssa;
 158 }
 159
 160 static bool
 161 dest_is_ssa(nir_dest *dest, void *data)
 162 {
 163    return dest->is_ssa;
 164 }
 165
 166 static bool
 167 nir_instr_can_cse(nir_instr *instr)
 168 {
 169    /* We only handle SSA. */
 170    if (!nir_foreach_dest(instr, dest_is_ssa, NULL) ||
 171        !nir_foreach_src(instr, src_is_ssa, NULL))
 172       return false;
 173
 174    switch (instr->type) {
 175    case nir_instr_type_alu:
 176    case nir_instr_type_load_const:
 177    case nir_instr_type_phi:
 178       return true;
 179    case nir_instr_type_tex:
 180       return false; /* TODO */
 181    case nir_instr_type_intrinsic: {
 182       const nir_intrinsic_info *info =
 183          &nir_intrinsic_infos[nir_instr_as_intrinsic(instr)->intrinsic];
 184       return (info->flags & NIR_INTRINSIC_CAN_ELIMINATE) &&
 185              (info->flags & NIR_INTRINSIC_CAN_REORDER) &&
 186              info->num_variables == 0; /* not implemented yet */
 187    }
 188    case nir_instr_type_call:
 189    case nir_instr_type_jump:
 190    case nir_instr_type_ssa_undef:
 191       return false;
 192    case nir_instr_type_parallel_copy:
 193    default:
 194       unreachable("Invalid instruction type");
 195    }
 196
 197    return false;
 198 }
 199
 200 static nir_ssa_def *
 201 nir_instr_get_dest_ssa_def(nir_instr *instr)
 202 {
 203    switch (instr->type) {
 204    case nir_instr_type_alu:
 205       assert(nir_instr_as_alu(instr)->dest.dest.is_ssa);
 206       return &nir_instr_as_alu(instr)->dest.dest.ssa;
 207    case nir_instr_type_load_const:
 208       return &nir_instr_as_load_const(instr)->def;
 209    case nir_instr_type_phi:
 210       assert(nir_instr_as_phi(instr)->dest.is_ssa);
 211       return &nir_instr_as_phi(instr)->dest.ssa;
 212    case nir_instr_type_intrinsic:
 213       assert(nir_instr_as_intrinsic(instr)->dest.is_ssa);
 214       return &nir_instr_as_intrinsic(instr)->dest.ssa;
 215    default:
 216       unreachable("We never ask for any of these");
 217    }
 218 }
 219
 220 static void
 221 nir_opt_cse_instr(nir_instr *instr, struct cse_state *state)
 222 {
 223    if (!nir_instr_can_cse(instr))
 224       return;
 225
 226    for (struct exec_node *node = instr->node.prev;
 227         !exec_node_is_head_sentinel(node); node = node->prev) {
 228       nir_instr *other = exec_node_data(nir_instr, node, node);
 229       if (nir_instrs_equal(instr, other)) {
 230          nir_ssa_def *other_def = nir_instr_get_dest_ssa_def(other);
 231          nir_ssa_def_rewrite_uses(nir_instr_get_dest_ssa_def(instr),
 232                                   nir_src_for_ssa(other_def),
 233                                   state->mem_ctx);
 234          nir_instr_remove(instr);
 235          state->progress = true;
 236          return;
 237       }
 238    }
 239
 240    for (nir_block *block = instr->block->imm_dom;
 241         block != NULL; block = block->imm_dom) {
 242       nir_foreach_instr_reverse(block, other) {
 243          if (nir_instrs_equal(instr, other)) {
 244             nir_ssa_def *other_def = nir_instr_get_dest_ssa_def(other);
 245             nir_ssa_def_rewrite_uses(nir_instr_get_dest_ssa_def(instr),
 246                                      nir_src_for_ssa(other_def),
 247                                      state->mem_ctx);
 248             nir_instr_remove(instr);
 249             state->progress = true;
 250             return;
 251          }
 252       }
 253    }
 254 }
 255
 256 static bool
 257 nir_opt_cse_block(nir_block *block, void *void_state)
 258 {
 259    struct cse_state *state = void_state;
 260
 261    nir_foreach_instr_safe(block, instr)
 262       nir_opt_cse_instr(instr, state);
 263
 264    return true;
 265 }
 266
 267 static bool
 268 nir_opt_cse_impl(nir_function_impl *impl)
 269 {
 270    struct cse_state state;
 271
 272    state.mem_ctx = ralloc_parent(impl);
 273    state.progress = false;
 274
 275    nir_metadata_require(impl, nir_metadata_dominance);
 276
 277    nir_foreach_block(impl, nir_opt_cse_block, &state);
 278
 279    if (state.progress)
 280       nir_metadata_preserve(impl, nir_metadata_block_index |
 281                                   nir_metadata_dominance);
 282
 283    return state.progress;
 284 }
 285
 286 bool
 287 nir_opt_cse(nir_shader *shader)
 288 {
 289    bool progress = false;
 290
 291    nir_foreach_overload(shader, overload) {
 292       if (overload->impl)
 293          progress |= nir_opt_cse_impl(overload->impl);
 294    }
 295
 296    return progress;
 297 }