src/glsl/nir/nir_opt_gcm.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Jason Ekstrand (jason@jlekstrand.net)
  25  *
  26  */
  27
  28 #include "nir.h"
  29
  30 /*
  31  * Implements Global Code Motion.  A description of GCM can be found in
  32  * "Global Code Motion; Global Value Numbering" by Cliff Click.
  33  * Unfortunately, the algorithm presented in the paper is broken in a
  34  * number of ways.  The algorithm used here differs substantially from the
  35  * one in the paper but it is, in my opinion, much easier to read and
  36  * verify correcness.
  37  */
  38
  39 struct gcm_block_info {
  40    /* Number of loops this block is inside */
  41    unsigned loop_depth;
  42
  43    /* The last instruction inserted into this block.  This is used as we
  44     * traverse the instructions and insert them back into the program to
  45     * put them in the right order.
  46     */
  47    nir_instr *last_instr;
  48 };
  49
  50 /* Flags used in the instr->pass_flags field for various instruction states */
  51 enum {
  52    GCM_INSTR_PINNED =            (1 << 0),
  53    GCM_INSTR_SCHEDULED_EARLY =   (1 << 1),
  54    GCM_INSTR_SCHEDULED_LATE =    (1 << 2),
  55    GCM_INSTR_PLACED =            (1 << 3),
  56 };
  57
  58 struct gcm_state {
  59    nir_function_impl *impl;
  60    nir_instr *instr;
  61
  62    /* The list of non-pinned instructions.  As we do the late scheduling,
  63     * we pull non-pinned instructions out of their blocks and place them in
  64     * this list.  This saves us from having linked-list problems when we go
  65     * to put instructions back in their blocks.
  66     */
  67    struct exec_list instrs;
  68
  69    struct gcm_block_info *blocks;
  70 };
  71
  72 /* Recursively walks the CFG and builds the block_info structure */
  73 static void
  74 gcm_build_block_info(struct exec_list *cf_list, struct gcm_state *state,
  75                      unsigned loop_depth)
  76 {
  77    foreach_list_typed(nir_cf_node, node, node, cf_list) {
  78       switch (node->type) {
  79       case nir_cf_node_block: {
  80          nir_block *block = nir_cf_node_as_block(node);
  81          state->blocks[block->index].loop_depth = loop_depth;
  82          break;
  83       }
  84       case nir_cf_node_if: {
  85          nir_if *if_stmt = nir_cf_node_as_if(node);
  86          gcm_build_block_info(&if_stmt->then_list, state, loop_depth);
  87          gcm_build_block_info(&if_stmt->else_list, state, loop_depth);
  88          break;
  89       }
  90       case nir_cf_node_loop: {
  91          nir_loop *loop = nir_cf_node_as_loop(node);
  92          gcm_build_block_info(&loop->body, state, loop_depth + 1);
  93          break;
  94       }
  95       default:
  96          unreachable("Invalid CF node type");
  97       }
  98    }
  99 }
 100
 101 /* Walks the instruction list and marks immovable instructions as pinned
 102  *
 103  * This function also serves to initialize the instr->pass_flags field.
 104  * After this is completed, all instructions' pass_flags fields will be set
 105  * to either GCM_INSTR_PINNED or 0.
 106  */
 107 static bool
 108 gcm_pin_instructions_block(nir_block *block, void *void_state)
 109 {
 110    struct gcm_state *state = void_state;
 111
 112    nir_foreach_instr_safe(block, instr) {
 113       switch (instr->type) {
 114       case nir_instr_type_alu:
 115          switch (nir_instr_as_alu(instr)->op) {
 116          case nir_op_fddx:
 117          case nir_op_fddy:
 118          case nir_op_fddx_fine:
 119          case nir_op_fddy_fine:
 120          case nir_op_fddx_coarse:
 121          case nir_op_fddy_coarse:
 122             /* These can only go in uniform control flow; pin them for now */
 123             instr->pass_flags = GCM_INSTR_PINNED;
 124
 125          default:
 126             instr->pass_flags = 0;
 127          }
 128          break;
 129
 130       case nir_instr_type_tex:
 131          switch (nir_instr_as_tex(instr)->op) {
 132          case nir_texop_tex:
 133          case nir_texop_txb:
 134          case nir_texop_lod:
 135             /* These two take implicit derivatives so they need to be pinned */
 136             instr->pass_flags = GCM_INSTR_PINNED;
 137
 138          default:
 139             instr->pass_flags = 0;
 140          }
 141          break;
 142
 143       case nir_instr_type_load_const:
 144          instr->pass_flags = 0;
 145          break;
 146
 147       case nir_instr_type_intrinsic: {
 148          const nir_intrinsic_info *info =
 149             &nir_intrinsic_infos[nir_instr_as_intrinsic(instr)->intrinsic];
 150
 151          if ((info->flags & NIR_INTRINSIC_CAN_ELIMINATE) &&
 152              (info->flags & NIR_INTRINSIC_CAN_REORDER)) {
 153             instr->pass_flags = 0;
 154          } else {
 155             instr->pass_flags = GCM_INSTR_PINNED;
 156          }
 157          break;
 158       }
 159
 160       case nir_instr_type_jump:
 161       case nir_instr_type_ssa_undef:
 162       case nir_instr_type_phi:
 163          instr->pass_flags = GCM_INSTR_PINNED;
 164          break;
 165
 166       default:
 167          unreachable("Invalid instruction type in GCM");
 168       }
 169
 170       if (!(instr->pass_flags & GCM_INSTR_PINNED)) {
 171          /* If this is an unpinned instruction, go ahead and pull it out of
 172           * the program and put it on the instrs list.  This has a couple
 173           * of benifits.  First, it makes the scheduling algorithm more
 174           * efficient because we can avoid walking over basic blocks and
 175           * pinned instructions.  Second, it keeps us from causing linked
 176           * list confusion when we're trying to put everything in its
 177           * proper place at the end of the pass.
 178           *
 179           * Note that we don't use nir_instr_remove here because that also
 180           * cleans up uses and defs and we want to keep that information.
 181           */
 182          exec_node_remove(&instr->node);
 183          exec_list_push_tail(&state->instrs, &instr->node);
 184       }
 185    }
 186
 187    return true;
 188 }
 189
 190 static void
 191 gcm_schedule_early_instr(nir_instr *instr, struct gcm_state *state);
 192
 193 /** Update an instructions schedule for the given source
 194  *
 195  * This function is called iteratively as we walk the sources of an
 196  * instruction.  It ensures that the given source instruction has been
 197  * scheduled and then update this instruction's block if the source
 198  * instruction is lower down the tree.
 199  */
 200 static bool
 201 gcm_schedule_early_src(nir_src *src, void *void_state)
 202 {
 203    struct gcm_state *state = void_state;
 204    nir_instr *instr = state->instr;
 205
 206    assert(src->is_ssa);
 207
 208    gcm_schedule_early_instr(src->ssa->parent_instr, void_state);
 209
 210    /* While the index isn't a proper dominance depth, it does have the
 211     * property that if A dominates B then A->index <= B->index.  Since we
 212     * know that this instruction must have been dominated by all of its
 213     * sources at some point (even if it's gone through value-numbering),
 214     * all of the sources must lie on the same branch of the dominance tree.
 215     * Therefore, we can just go ahead and just compare indices.
 216     */
 217    if (instr->block->index < src->ssa->parent_instr->block->index)
 218       instr->block = src->ssa->parent_instr->block;
 219
 220    /* We need to restore the state instruction because it may have been
 221     * changed through the gcm_schedule_early_instr call above.  Since we
 222     * may still be iterating through sources and future calls to
 223     * gcm_schedule_early_src for the same instruction will still need it.
 224     */
 225    state->instr = instr;
 226
 227    return true;
 228 }
 229
 230 /** Schedules an instruction early
 231  *
 232  * This function performs a recursive depth-first search starting at the
 233  * given instruction and proceeding through the sources to schedule
 234  * instructions as early as they can possibly go in the dominance tree.
 235  * The instructions are "scheduled" by updating their instr->block field.
 236  */
 237 static void
 238 gcm_schedule_early_instr(nir_instr *instr, struct gcm_state *state)
 239 {
 240    if (instr->pass_flags & GCM_INSTR_SCHEDULED_EARLY)
 241       return;
 242
 243    instr->pass_flags |= GCM_INSTR_SCHEDULED_EARLY;
 244
 245    /* Pinned instructions are already scheduled so we don't need to do
 246     * anything.  Also, bailing here keeps us from ever following the
 247     * sources of phi nodes which can be back-edges.
 248     */
 249    if (instr->pass_flags & GCM_INSTR_PINNED)
 250       return;
 251
 252    /* Start with the instruction at the top.  As we iterate over the
 253     * sources, it will get moved down as needed.
 254     */
 255    instr->block = state->impl->start_block;
 256    state->instr = instr;
 257
 258    nir_foreach_src(instr, gcm_schedule_early_src, state);
 259 }
 260
 261 static void
 262 gcm_schedule_late_instr(nir_instr *instr, struct gcm_state *state);
 263
 264 /** Schedules the instruction associated with the given SSA def late
 265  *
 266  * This function works by first walking all of the uses of the given SSA
 267  * definition, ensuring that they are scheduled, and then computing the LCA
 268  * (least common ancestor) of its uses.  It then schedules this instruction
 269  * as close to the LCA as possible while trying to stay out of loops.
 270  */
 271 static bool
 272 gcm_schedule_late_def(nir_ssa_def *def, void *void_state)
 273 {
 274    struct gcm_state *state = void_state;
 275
 276    nir_block *lca = NULL;
 277
 278    struct set_entry *entry;
 279    set_foreach(def->uses, entry) {
 280       nir_instr *use_instr = (nir_instr *)entry->key;
 281
 282       gcm_schedule_late_instr(use_instr, state);
 283
 284       /* Phi instructions are a bit special.  SSA definitions don't have to
 285        * dominate the sources of the phi nodes that use them; instead, they
 286        * have to dominate the predecessor block corresponding to the phi
 287        * source.  We handle this by looking through the sources, finding
 288        * any that are usingg this SSA def, and using those blocks instead
 289        * of the one the phi lives in.
 290        */
 291       if (use_instr->type == nir_instr_type_phi) {
 292          nir_phi_instr *phi = nir_instr_as_phi(use_instr);
 293
 294          nir_foreach_phi_src(phi, phi_src) {
 295             if (phi_src->src.ssa == def)
 296                lca = nir_dominance_lca(lca, phi_src->pred);
 297          }
 298       } else {
 299          lca = nir_dominance_lca(lca, use_instr->block);
 300       }
 301    }
 302
 303    set_foreach(def->if_uses, entry) {
 304       nir_if *if_stmt = (nir_if *)entry->key;
 305
 306       /* For if statements, we consider the block to be the one immediately
 307        * preceding the if CF node.
 308        */
 309       nir_block *pred_block =
 310          nir_cf_node_as_block(nir_cf_node_prev(&if_stmt->cf_node));
 311
 312       lca = nir_dominance_lca(lca, pred_block);
 313    }
 314
 315    /* Some instructions may never be used.  We'll just leave them scheduled
 316     * early and let dead code clean them up.
 317     */
 318    if (lca == NULL)
 319       return true;
 320
 321    /* We know have the LCA of all of the uses.  If our invariants hold,
 322     * this is dominated by the block that we chose when scheduling early.
 323     * We now walk up the dominance tree and pick the lowest block that is
 324     * as far outside loops as we can get.
 325     */
 326    nir_block *best = lca;
 327    while (lca != def->parent_instr->block) {
 328       assert(lca);
 329       if (state->blocks[lca->index].loop_depth <
 330           state->blocks[best->index].loop_depth)
 331          best = lca;
 332       lca = lca->imm_dom;
 333    }
 334    def->parent_instr->block = best;
 335
 336    return true;
 337 }
 338
 339 /** Schedules an instruction late
 340  *
 341  * This function performs a depth-first search starting at the given
 342  * instruction and proceeding through its uses to schedule instructions as
 343  * late as they can reasonably go in the dominance tree.  The instructions
 344  * are "scheduled" by updating their instr->block field.
 345  *
 346  * The name of this function is actually a bit of a misnomer as it doesn't
 347  * schedule them "as late as possible" as the paper implies.  Instead, it
 348  * first finds the lates possible place it can schedule the instruction and
 349  * then possibly schedules it earlier than that.  The actual location is as
 350  * far down the tree as we can go while trying to stay out of loops.
 351  */
 352 static void
 353 gcm_schedule_late_instr(nir_instr *instr, struct gcm_state *state)
 354 {
 355    if (instr->pass_flags & GCM_INSTR_SCHEDULED_LATE)
 356       return;
 357
 358    instr->pass_flags |= GCM_INSTR_SCHEDULED_LATE;
 359
 360    /* Pinned instructions are already scheduled so we don't need to do
 361     * anything.  Also, bailing here keeps us from ever following phi nodes
 362     * which can be back-edges.
 363     */
 364    if (instr->pass_flags & GCM_INSTR_PINNED)
 365       return;
 366
 367    nir_foreach_ssa_def(instr, gcm_schedule_late_def, state);
 368 }
 369
 370 static void
 371 gcm_place_instr(nir_instr *instr, struct gcm_state *state);
 372
 373 static bool
 374 gcm_place_instr_def(nir_ssa_def *def, void *state)
 375 {
 376    struct set_entry *entry;
 377    set_foreach(def->uses, entry)
 378       gcm_place_instr((nir_instr *)entry->key, state);
 379
 380    return false;
 381 }
 382
 383 /** Places an instrution back into the program
 384  *
 385  * The earlier passes of GCM simply choose blocks for each instruction and
 386  * otherwise leave them alone.  This pass actually places the instructions
 387  * into their chosen blocks.
 388  *
 389  * To do so, we use a standard post-order depth-first search linearization
 390  * algorithm.  We walk over the uses of the given instruction and ensure
 391  * that they are placed and then place this instruction.  Because we are
 392  * working on multiple blocks at a time, we keep track of the last inserted
 393  * instruction per-block in the state structure's block_info array.  When
 394  * we insert an instruction in a block we insert it before the last
 395  * instruction inserted in that block rather than the last instruction
 396  * inserted globally.
 397  */
 398 static void
 399 gcm_place_instr(nir_instr *instr, struct gcm_state *state)
 400 {
 401    if (instr->pass_flags & GCM_INSTR_PLACED)
 402       return;
 403
 404    instr->pass_flags |= GCM_INSTR_PLACED;
 405
 406    /* Phi nodes are our once source of back-edges.  Since right now we are
 407     * only doing scheduling within blocks, we don't need to worry about
 408     * them since they are always at the top.  Just skip them completely.
 409     */
 410    if (instr->type == nir_instr_type_phi) {
 411       assert(instr->pass_flags & GCM_INSTR_PINNED);
 412       return;
 413    }
 414
 415    nir_foreach_ssa_def(instr, gcm_place_instr_def, state);
 416
 417    if (instr->pass_flags & GCM_INSTR_PINNED) {
 418       /* Pinned instructions have an implicit dependence on the pinned
 419        * instructions that come after them in the block.  Since the pinned
 420        * instructions will naturally "chain" together, we only need to
 421        * explicitly visit one of them.
 422        */
 423       for (nir_instr *after = nir_instr_next(instr);
 424            after;
 425            after = nir_instr_next(after)) {
 426          if (after->pass_flags & GCM_INSTR_PINNED) {
 427             gcm_place_instr(after, state);
 428             break;
 429          }
 430       }
 431    }
 432
 433    struct gcm_block_info *block_info = &state->blocks[instr->block->index];
 434    if (!(instr->pass_flags & GCM_INSTR_PINNED)) {
 435       exec_node_remove(&instr->node);
 436
 437       if (block_info->last_instr) {
 438          exec_node_insert_node_before(&block_info->last_instr->node,
 439                                       &instr->node);
 440       } else {
 441          /* Schedule it at the end of the block */
 442          nir_instr *jump_instr = nir_block_last_instr(instr->block);
 443          if (jump_instr && jump_instr->type == nir_instr_type_jump) {
 444             exec_node_insert_node_before(&jump_instr->node, &instr->node);
 445          } else {
 446             exec_list_push_tail(&instr->block->instr_list, &instr->node);
 447          }
 448       }
 449    }
 450
 451    block_info->last_instr = instr;
 452 }
 453
 454 static void
 455 opt_gcm_impl(nir_function_impl *impl)
 456 {
 457    struct gcm_state state;
 458
 459    state.impl = impl;
 460    state.instr = NULL;
 461    exec_list_make_empty(&state.instrs);
 462    state.blocks = rzalloc_array(NULL, struct gcm_block_info, impl->num_blocks);
 463
 464    nir_metadata_require(impl, nir_metadata_block_index |
 465                               nir_metadata_dominance);
 466
 467    gcm_build_block_info(&impl->body, &state, 0);
 468    nir_foreach_block(impl, gcm_pin_instructions_block, &state);
 469
 470    foreach_list_typed(nir_instr, instr, node, &state.instrs)
 471       gcm_schedule_early_instr(instr, &state);
 472
 473    foreach_list_typed(nir_instr, instr, node, &state.instrs)
 474       gcm_schedule_late_instr(instr, &state);
 475
 476    while (!exec_list_is_empty(&state.instrs)) {
 477       nir_instr *instr = exec_node_data(nir_instr,
 478                                         state.instrs.tail_pred, node);
 479       gcm_place_instr(instr, &state);
 480    }
 481
 482    ralloc_free(state.blocks);
 483 }
 484
 485 void
 486 nir_opt_gcm(nir_shader *shader)
 487 {
 488    nir_foreach_overload(shader, overload) {
 489       if (overload->impl)
 490          opt_gcm_impl(overload->impl);
 491    }
 492 }