src/gpu-compute/X86GPUTLB.py

   1 # Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
   2 # All rights reserved.
   3 #
   4 # For use for simulation and test purposes only
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   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are met:
   8 #
   9 # 1. Redistributions of source code must retain the above copyright notice,
  10 # this list of conditions and the following disclaimer.
  11 #
  12 # 2. Redistributions in binary form must reproduce the above copyright notice,
  13 # this list of conditions and the following disclaimer in the documentation
  14 # and/or other materials provided with the distribution.
  15 #
  16 # 3. Neither the name of the copyright holder nor the names of its
  17 # contributors may be used to endorse or promote products derived from this
  18 # software without specific prior written permission.
  19 #
  20 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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  29 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 # POSSIBILITY OF SUCH DAMAGE.
  31
  32 from m5.defines import buildEnv
  33 from m5.params import *
  34 from m5.proxy import *
  35
  36 from m5.objects.ClockedObject import ClockedObject
  37 from m5.SimObject import SimObject
  38
  39 if buildEnv['FULL_SYSTEM']:
  40     class X86PagetableWalker(SimObject):
  41         type = 'X86PagetableWalker'
  42         cxx_class = 'X86ISA::Walker'
  43         port = ResponsePort("Port for the hardware table walker")
  44         system = Param.System(Parent.any, "system object")
  45
  46 class X86GPUTLB(ClockedObject):
  47     type = 'X86GPUTLB'
  48     cxx_class = 'X86ISA::GpuTLB'
  49     cxx_header = 'gpu-compute/gpu_tlb.hh'
  50     size = Param.Int(64, "TLB size (number of entries)")
  51     assoc = Param.Int(64, "TLB associativity")
  52
  53     if buildEnv['FULL_SYSTEM']:
  54         walker = Param.X86PagetableWalker(X86PagetableWalker(),
  55                                           "page table walker")
  56
  57     hitLatency = Param.Int(2, "Latency of a TLB hit")
  58     missLatency1 = Param.Int(5, "Latency #1 of a TLB miss")
  59     missLatency2 = Param.Int(100, "Latency #2 of a TLB miss")
  60     maxOutstandingReqs = Param.Int(64, "# of maximum outstanding requests")
  61     slave = VectorSlavePort("Port on side closer to CPU/CU")
  62     master = VectorMasterPort("Port on side closer to memory")
  63     allocationPolicy = Param.Bool(True, "Allocate on an access")
  64     accessDistance = Param.Bool(False, "print accessDistance stats")
  65
  66 class TLBCoalescer(ClockedObject):
  67     type = 'TLBCoalescer'
  68     cxx_class = 'TLBCoalescer'
  69     cxx_header = 'gpu-compute/tlb_coalescer.hh'
  70     probesPerCycle = Param.Int(2, "Number of TLB probes per cycle")
  71     coalescingWindow = Param.Int(1, "Permit coalescing across that many ticks")
  72     slave = VectorSlavePort("Port on side closer to CPU/CU")
  73     master = VectorMasterPort("Port on side closer to memory")
  74     disableCoalescing = Param.Bool(False,"Dispable Coalescing")