dev, virtio: properly set PCI address space to use IOREG
[gem5.git] / src / gpu-compute / fetch_stage.cc
1 /*
2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Author: Anthony Gutierrez, Sooraj Puthoor
34 */
35
36 #include "gpu-compute/fetch_stage.hh"
37
38 #include "gpu-compute/compute_unit.hh"
39 #include "gpu-compute/wavefront.hh"
40
41 FetchStage::FetchStage(const ComputeUnitParams* p) : numSIMDs(p->num_SIMDs),
42 computeUnit(nullptr)
43 {
44 for (int j = 0; j < numSIMDs; ++j) {
45 FetchUnit newFetchUnit(p);
46 fetchUnit.push_back(newFetchUnit);
47 }
48 }
49
50 FetchStage::~FetchStage()
51 {
52 fetchUnit.clear();
53 }
54
55 void
56 FetchStage::init(ComputeUnit *cu)
57 {
58 computeUnit = cu;
59 _name = computeUnit->name() + ".FetchStage";
60
61 for (int j = 0; j < numSIMDs; ++j) {
62 fetchUnit[j].bindWaveList(&computeUnit->wfList[j]);
63 fetchUnit[j].init(computeUnit);
64 }
65 }
66
67 void
68 FetchStage::exec()
69 {
70 for (int j = 0; j < numSIMDs; ++j) {
71 fetchUnit[j].exec();
72 }
73 }
74
75 void
76 FetchStage::processFetchReturn(PacketPtr pkt)
77 {
78 ComputeUnit::SQCPort::SenderState *sender_state =
79 safe_cast<ComputeUnit::SQCPort::SenderState*>(pkt->senderState);
80
81 Wavefront *wavefront = sender_state->wavefront;
82
83 const unsigned num_instructions = pkt->req->getSize() /
84 sizeof(TheGpuISA::RawMachInst);
85
86 instFetchInstReturned.sample(num_instructions);
87 uint32_t simdId = wavefront->simdId;
88 fetchUnit[simdId].processFetchReturn(pkt);
89 }
90
91 void
92 FetchStage::fetch(PacketPtr pkt, Wavefront *wavefront)
93 {
94 fetchUnit[wavefront->simdId].fetch(pkt, wavefront);
95 }
96
97 void
98 FetchStage::regStats()
99 {
100 instFetchInstReturned
101 .init(1, 32, 1)
102 .name(name() + ".inst_fetch_instr_returned")
103 .desc("For each instruction fetch request recieved record how many "
104 "instructions you got from it")
105 ;
106 }