src/gpu-compute/global_memory_pipeline.hh

   1 /*
   2  * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
   3  * All rights reserved.
   4  *
   5  * For use for simulation and test purposes only
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright notice,
  14  * this list of conditions and the following disclaimer in the documentation
  15  * and/or other materials provided with the distribution.
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  * contributors may be used to endorse or promote products derived from this
  19  * software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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  33
  34 #ifndef __GLOBAL_MEMORY_PIPELINE_HH__
  35 #define __GLOBAL_MEMORY_PIPELINE_HH__
  36
  37 #include <queue>
  38 #include <string>
  39
  40 #include "gpu-compute/misc.hh"
  41 #include "params/ComputeUnit.hh"
  42 #include "sim/stats.hh"
  43
  44 /*
  45  * @file global_memory_pipeline.hh
  46  *
  47  * The global memory pipeline issues newly created global memory packets
  48  * from the pipeline to DTLB. The exec() method of the memory packet issues
  49  * the packet to the DTLB if there is space available in the return fifo.
  50  * This stage also retires previously issued loads and stores that have
  51  * returned from the memory sub-system.
  52  */
  53
  54 class ComputeUnit;
  55
  56 class GlobalMemPipeline
  57 {
  58   public:
  59     GlobalMemPipeline(const ComputeUnitParams *params);
  60     void init(ComputeUnit *cu);
  61     void exec();
  62
  63     std::queue<GPUDynInstPtr> &getGMStRespFIFO() { return gmReturnedStores; }
  64     std::queue<GPUDynInstPtr> &getGMLdRespFIFO() { return gmReturnedLoads; }
  65
  66     /**
  67      * find the next ready response to service. for OoO mode we
  68      * simply pop the oldest (based on when the response was
  69      * received) response in the response FIFOs. for in-order mode
  70      * we pop the oldest (in program order) response, and only if
  71      * it is marked as done.
  72      */
  73     GPUDynInstPtr getNextReadyResp();
  74
  75     /**
  76      * once a memory request is finished we remove it from the
  77      * buffer. this method determines which response buffer
  78      * we're using based on the mode (in-order vs. OoO).
  79      */
  80     void completeRequest(GPUDynInstPtr gpuDynInst);
  81
  82     /**
  83      * issues a request to the pipeline - i.e., enqueue it
  84      * in the request buffer.
  85      */
  86     void issueRequest(GPUDynInstPtr gpuDynInst);
  87
  88     /**
  89      * this method handles responses sent to this GM pipeline by the
  90      * CU. in the case of in-order delivery it simply marks the reqeust
  91      * as done in the ordered buffer to indicate that the requst is
  92      * finished. for out-of-order data delivery, the requests are enqueued
  93      * (in the order in which they are received) in the response FIFOs.
  94      */
  95     void handleResponse(GPUDynInstPtr gpuDynInst);
  96
  97     bool
  98     isGMLdRespFIFOWrRdy() const
  99     {
 100         return gmReturnedLoads.size() < gmQueueSize;
 101     }
 102
 103     bool
 104     isGMStRespFIFOWrRdy() const
 105     {
 106         return gmReturnedStores.size() < gmQueueSize;
 107     }
 108
 109     bool
 110     isGMReqFIFOWrRdy(uint32_t pendReqs=0) const
 111     {
 112         return (gmIssuedRequests.size() + pendReqs) < gmQueueSize;
 113     }
 114
 115     const std::string &name() const { return _name; }
 116     void regStats();
 117
 118     void
 119     incLoadVRFBankConflictCycles(int num_cycles)
 120     {
 121         loadVrfBankConflictCycles += num_cycles;
 122     }
 123
 124   private:
 125     ComputeUnit *computeUnit;
 126     std::string _name;
 127     int gmQueueSize;
 128     bool outOfOrderDataDelivery;
 129
 130     // number of cycles of delaying the update of a VGPR that is the
 131     // target of a load instruction (or the load component of an atomic)
 132     // The delay is due to VRF bank conflicts
 133     Stats::Scalar loadVrfBankConflictCycles;
 134     // Counters to track the inflight loads and stores
 135     // so that we can provide the proper backpressure
 136     // on the number of inflight memory operations.
 137     int inflightStores;
 138     int inflightLoads;
 139
 140     // The size of global memory.
 141     int globalMemSize;
 142
 143     /*
 144      * this buffer holds the memory responses when in-order data
 145      * deilvery is used - the responses are ordered by their unique
 146      * sequence number, which is monotonically increasing. when a
 147      * memory request returns its "done" flag is set to true. during
 148      * each tick the the GM pipeline will check if the oldest request
 149      * is finished, and if so it will be removed from the queue.
 150      *
 151      * key:   memory instruction's sequence ID
 152      *
 153      * value: pair holding the instruction pointer and a bool that
 154      *        is used to indicate whether or not the request has
 155      *        completed
 156      */
 157     std::map<uint64_t, std::pair<GPUDynInstPtr, bool>> gmOrderedRespBuffer;
 158
 159     // Global Memory Request FIFO: all global memory requests
 160     // are issued to this FIFO from the memory pipelines
 161     std::queue<GPUDynInstPtr> gmIssuedRequests;
 162
 163     // Globa Store Response FIFO: all responses of global memory
 164     // stores are sent to this FIFO from TCP
 165     std::queue<GPUDynInstPtr> gmReturnedStores;
 166
 167     // Global Load Response FIFO: all responses of global memory
 168     // loads are sent to this FIFO from TCP
 169     std::queue<GPUDynInstPtr> gmReturnedLoads;
 170 };
 171
 172 #endif // __GLOBAL_MEMORY_PIPELINE_HH__