2 * Copyright (c) 2015 Advanced Micro Devices, Inc.
5 * For use for simulation and test purposes only
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8 * modification, are permitted provided that the following conditions are met:
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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33 * Author: Anthony Gutierrez
36 #ifndef __GPU_STATIC_INST_HH__
37 #define __GPU_STATIC_INST_HH__
40 * @file gpu_static_inst.hh
42 * Defines the base class representing static instructions for the GPU. The
43 * instructions are "static" because they contain no dynamic instruction
44 * information. GPUStaticInst corresponds to the StaticInst class for the CPU
51 #include "enums/GPUStaticInstFlags.hh"
52 #include "enums/StorageClassType.hh"
53 #include "gpu-compute/gpu_dyn_inst.hh"
54 #include "gpu-compute/misc.hh"
60 class GPUStaticInst : public GPUStaticInstFlags
63 GPUStaticInst(const std::string &opcode);
64 void instAddr(int inst_addr) { _instAddr = inst_addr; }
65 int instAddr() const { return _instAddr; }
66 int nextInstAddr() const { return _instAddr + instSize(); }
68 void instNum(int num) { _instNum = num; }
70 int instNum() { return _instNum; }
72 void ipdInstNum(int num) { _ipdInstNum = num; }
74 int ipdInstNum() const { return _ipdInstNum; }
76 virtual void execute(GPUDynInstPtr gpuDynInst) = 0;
77 virtual void generateDisassembly() = 0;
78 const std::string& disassemble();
79 virtual int getNumOperands() = 0;
80 virtual bool isCondRegister(int operandIndex) = 0;
81 virtual bool isScalarRegister(int operandIndex) = 0;
82 virtual bool isVectorRegister(int operandIndex) = 0;
83 virtual bool isSrcOperand(int operandIndex) = 0;
84 virtual bool isDstOperand(int operandIndex) = 0;
85 virtual int getOperandSize(int operandIndex) = 0;
87 virtual int getRegisterIndex(int operandIndex,
88 GPUDynInstPtr gpuDynInst) = 0;
90 virtual int numDstRegOperands() = 0;
91 virtual int numSrcRegOperands() = 0;
93 virtual bool isValid() const = 0;
95 bool isALU() const { return _flags[ALU]; }
96 bool isBranch() const { return _flags[Branch]; }
97 bool isNop() const { return _flags[Nop]; }
98 bool isReturn() const { return _flags[Return]; }
101 isUnconditionalJump() const
103 return _flags[UnconditionalJump];
106 bool isSpecialOp() const { return _flags[SpecialOp]; }
107 bool isWaitcnt() const { return _flags[Waitcnt]; }
109 bool isBarrier() const { return _flags[MemBarrier]; }
110 bool isMemFence() const { return _flags[MemFence]; }
111 bool isMemRef() const { return _flags[MemoryRef]; }
112 bool isFlat() const { return _flags[Flat]; }
113 bool isLoad() const { return _flags[Load]; }
114 bool isStore() const { return _flags[Store]; }
119 return _flags[AtomicReturn] || _flags[AtomicNoReturn];
122 bool isAtomicNoRet() const { return _flags[AtomicNoReturn]; }
123 bool isAtomicRet() const { return _flags[AtomicReturn]; }
125 bool isScalar() const { return _flags[Scalar]; }
126 bool readsSCC() const { return _flags[ReadsSCC]; }
127 bool writesSCC() const { return _flags[WritesSCC]; }
128 bool readsVCC() const { return _flags[ReadsVCC]; }
129 bool writesVCC() const { return _flags[WritesVCC]; }
131 bool isAtomicAnd() const { return _flags[AtomicAnd]; }
132 bool isAtomicOr() const { return _flags[AtomicOr]; }
133 bool isAtomicXor() const { return _flags[AtomicXor]; }
134 bool isAtomicCAS() const { return _flags[AtomicCAS]; }
135 bool isAtomicExch() const { return _flags[AtomicExch]; }
136 bool isAtomicAdd() const { return _flags[AtomicAdd]; }
137 bool isAtomicSub() const { return _flags[AtomicSub]; }
138 bool isAtomicInc() const { return _flags[AtomicInc]; }
139 bool isAtomicDec() const { return _flags[AtomicDec]; }
140 bool isAtomicMax() const { return _flags[AtomicMax]; }
141 bool isAtomicMin() const { return _flags[AtomicMin]; }
146 return (_flags[KernArgSegment] || _flags[ArgSegment]) && _flags[Load];
152 return _flags[MemoryRef] && (_flags[GlobalSegment] ||
153 _flags[PrivateSegment] || _flags[ReadOnlySegment] ||
154 _flags[SpillSegment]);
160 return _flags[MemoryRef] && _flags[GroupSegment];
163 bool isArgSeg() const { return _flags[ArgSegment]; }
164 bool isGlobalSeg() const { return _flags[GlobalSegment]; }
165 bool isGroupSeg() const { return _flags[GroupSegment]; }
166 bool isKernArgSeg() const { return _flags[KernArgSegment]; }
167 bool isPrivateSeg() const { return _flags[PrivateSegment]; }
168 bool isReadOnlySeg() const { return _flags[ReadOnlySegment]; }
169 bool isSpillSeg() const { return _flags[SpillSegment]; }
171 bool isWorkitemScope() const { return _flags[WorkitemScope]; }
172 bool isWavefrontScope() const { return _flags[WavefrontScope]; }
173 bool isWorkgroupScope() const { return _flags[WorkgroupScope]; }
174 bool isDeviceScope() const { return _flags[DeviceScope]; }
175 bool isSystemScope() const { return _flags[SystemScope]; }
176 bool isNoScope() const { return _flags[NoScope]; }
178 bool isRelaxedOrder() const { return _flags[RelaxedOrder]; }
179 bool isAcquire() const { return _flags[Acquire]; }
180 bool isRelease() const { return _flags[Release]; }
181 bool isAcquireRelease() const { return _flags[AcquireRelease]; }
182 bool isNoOrder() const { return _flags[NoOrder]; }
185 * Coherence domain of a memory instruction. Only valid for
186 * machine ISA. The coherence domain specifies where it is
187 * possible to perform memory synchronization, e.g., acquire
188 * or release, from the shader kernel.
190 * isGloballyCoherent(): returns true if kernel is sharing memory
191 * with other work-items on the same device (GPU)
193 * isSystemCoherent(): returns true if kernel is sharing memory
194 * with other work-items on a different device (GPU) or the host (CPU)
196 bool isGloballyCoherent() const { return _flags[GloballyCoherent]; }
197 bool isSystemCoherent() const { return _flags[SystemCoherent]; }
199 virtual int instSize() const = 0;
201 // only used for memory instructions
203 initiateAcc(GPUDynInstPtr gpuDynInst)
205 fatal("calling initiateAcc() on a non-memory instruction.\n");
208 // only used for memory instructions
210 completeAcc(GPUDynInstPtr gpuDynInst)
212 fatal("calling completeAcc() on a non-memory instruction.\n");
215 virtual uint32_t getTargetPc() { return 0; }
217 static uint64_t dynamic_id_count;
219 // For flat memory accesses
220 Enums::StorageClassType executed_as;
222 void setFlag(Flags flag) { _flags[flag] = true; }
225 execLdAcq(GPUDynInstPtr gpuDynInst)
227 fatal("calling execLdAcq() on a non-load instruction.\n");
231 execSt(GPUDynInstPtr gpuDynInst)
233 fatal("calling execLdAcq() on a non-load instruction.\n");
237 execAtomic(GPUDynInstPtr gpuDynInst)
239 fatal("calling execAtomic() on a non-atomic instruction.\n");
243 execAtomicAcq(GPUDynInstPtr gpuDynInst)
245 fatal("calling execAtomicAcq() on a non-atomic instruction.\n");
249 const std::string opcode;
250 std::string disassembly;
254 * Identifier of the immediate post-dominator instruction.
258 std::bitset<Num_Flags> _flags;
261 class KernelLaunchStaticInst : public GPUStaticInst
264 KernelLaunchStaticInst() : GPUStaticInst("kernel_launch")
269 setFlag(SystemScope);
270 setFlag(GlobalSegment);
274 execute(GPUDynInstPtr gpuDynInst) override
276 fatal("kernel launch instruction should not be executed\n");
280 generateDisassembly() override
282 disassembly = opcode;
285 int getNumOperands() override { return 0; }
286 bool isCondRegister(int operandIndex) override { return false; }
287 bool isScalarRegister(int operandIndex) override { return false; }
288 bool isVectorRegister(int operandIndex) override { return false; }
289 bool isSrcOperand(int operandIndex) override { return false; }
290 bool isDstOperand(int operandIndex) override { return false; }
291 int getOperandSize(int operandIndex) override { return 0; }
294 getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
299 int numDstRegOperands() override { return 0; }
300 int numSrcRegOperands() override { return 0; }
301 bool isValid() const override { return true; }
302 int instSize() const override { return 0; }
305 #endif // __GPU_STATIC_INST_HH__